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[/] [or1k/] [tags/] [nog_patch_34/] [or1ksim/] [cpu/] [or32/] [execute.c] - Blame information for rev 626

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/* execute.c -- OR1K architecture dependent simulation
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Most of the OR1K simulation is done in here. */
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <ctype.h>
 
#include "config.h"
#include "arch.h"
#include "opcode/or32.h"
#include "branch_predict.h"
#include "abstract.h"
#include "labels.h"
#include "parse.h"
#include "execute.h"
#include "stats.h"
#include "except.h"
#include "sprs.h"
#include "sim-config.h"
#include "debug_unit.h"
 
/* Whether instructions set overflow flag */
#define SET_OV_FLAG     1
 
/* Whether arithmethic instructions set flag on zero */
#define ARITH_SET_FLAG  1
 
/* General purpose registers. */
machword reg[MAX_GPRS];
 
/* Instruction queue */
struct iqueue_entry iqueue[20];
 
/* Is current insn in execution a delay insn? */
int delay_insn;
 
/* Benchmark multi issue execution */
int multissue[20];
int supercycles;
int issued_per_cycle = 4;
int hazardwait = 0;
 
/* Whether break was hit - so we can step over a break */
static int break_just_hit = 0;
 
/* freemem 'pointer' */
extern unsigned long freemem;
 
/* Completition queue */
struct iqueue_entry icomplet[20];
 
/* Program counter (and translated PC) */
unsigned long pc;
unsigned long pc_phy;
 
/* Previous program counter */
unsigned long pcprev = 0;
 
/* Temporary program counter */
unsigned long pcnext;
 
/* Delay instruction effective address register */
unsigned long pcdelay;
 
/* CCR */
int flag;
 
/* CCR (for dependency calculation) */
char ccr_flag[10] = "flag";
 
/* Cycles counts fetch stages */
int cycles;
 
/* Each cycle has counter of mem_cycles; this value is joined with cycles
   at the end of the cycle; no sim originated memory accesses should be
   performed inbetween. */
int mem_cycles;
 
/* Instructions executed */
int instructions;
 
/* Load and store stalls */
int loadcycles, storecycles;
 
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;
static int sbuf_buf[MAX_SBUF_LEN] = {0};
static int sbuf_prev_cycles = 0;
 
/* Num cycles waiting for stores to complete */
int sbuf_wait_cyc = 0;
 
/* Number of total store cycles */
int sbuf_total_cyc = 0;
 
/* Local data needed for execution.  */
static struct iqueue_entry *cur;
static int next_delay_insn;
static int breakpoint;
static unsigned long *op;
static int num_op;
 
/* Implementation specific.
   Get an actual value of a specific register. */
 
unsigned long evalsim_reg32(int regno)
{
  if (regno < MAX_GPRS) {
    return reg[regno];
  } else {
    printf("\nABORT: read out of registers\n");
    cont_run = 0;
    return 0;
  }
}
 
/* Implementation specific.
   Set a specific register with value. */
 
void setsim_reg32(int regno, unsigned long value)
{
  if (regno == 0)               /* gpr0 is always zero */
    value = 0;
 
  if (regno < MAX_GPRS) {
    reg[regno] = value;
  } else {
    printf("\nABORT: write out of registers\n");
    cont_run = 0;
  }
}
 
/* Implementation specific.
   Get an actual value of a specific register. */
 
inline static unsigned long eval_reg32(int regno)
{
  if (regno < MAX_GPRS) {
    IFF(config.cpu.raw_range) {
      int delta = (cycles - raw_stats.reg[regno]);
      if ((unsigned long)delta < (unsigned long)config.cpu.raw_range)
        raw_stats.range[delta]++;
    }
    debug(9, "atoi ret1\n");
    return reg[regno];
  } else {
    printf("\nABORT: read out of registers\n");
    cont_run = 0;
    return 0;
  }
}
 
/* Implementation specific.
   Set a specific register with value. */
 
inline static void set_reg32(int regno, unsigned long value)
{
#if 0   
  if (strcmp(regstr, FRAME_REG) == 0) {
    printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc);
    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regno), value);
  }
 
  if (strcmp(regstr, STACK_REG) == 0) {
    printf("SP (%s) modified by insn at %x. ", STACK_REG, pc);
    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regmo), value);
  }
#endif
 
  if (regno < MAX_GPRS) {
    reg[regno] = value;
    IFF(config.cpu.raw_range)
      raw_stats.reg[regno] = cycles;
  } else {
    printf("\nABORT: write out of registers\n");
    cont_run = 0;
  }
}
 
/* Does srcoperand depend on computation of dstoperand? Return
   non-zero if yes.
 
 Cycle t                 Cycle t+1
dst: irrelevant         src: immediate                  always 0
dst: reg1 direct        src: reg2 direct                0 if reg1 != reg2
dst: reg1 disp          src: reg2 direct                always 0
dst: reg1 direct        src: reg2 disp                  0 if reg1 != reg2
dst: reg1 disp          src: reg2 disp                  always 1 (store must
                                                        finish before load)
dst: flag               src: flag                       always 1
*/
 
int depend_operands(prev, next)
     struct iqueue_entry *prev;
     struct iqueue_entry *next;
{
  /* Find destination type. */
  unsigned long type = 0;
  int i = 0;
  if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG
      && or32_opcodes[next->insn_index].flags & OR32_R_FLAG)
    return 1;
 
  while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))
    if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)
      {
        type = prev->op[i + MAX_OPERANDS];
        break;
      }
    else
      i++;
 
  /* We search all source operands - if we find confict => return 1 */
  i = 0;
  while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))
    if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))
      {
        if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS)
          if (type & OPTYPE_DIS)
            return 1;
          else if (next->op[i] == prev->op[i]
                   && (next->op[i + MAX_OPERANDS] & OPTYPE_REG))
            return 1;
        if (next->op[i] == prev->op[i]
            && (next->op[i + MAX_OPERANDS] & OPTYPE_REG)
            && (type & OPTYPE_REG))
          return 1;
        i++;
      }
    else
      i++;
  return 0;
}
 
/* Implementation specific.
   Parses and returns operands. */
 
static void
eval_operands (unsigned long insn, int insn_index, int* breakpoint)
{
  struct insn_op_struct *opd = op_start[insn_index];
  unsigned long data = 0;
  int dis = 0;
  int no = 0;
 
  while (1)
    {
      unsigned long tmp = 0, nbits = 0;
      while (1)
        {
          tmp |= ((insn  >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;
          nbits += opd->data;
          if (opd->type & OPTYPE_OP)
            break;
          opd++;
        }
 
      /* Do we have to sign extend? */
      if (opd->type & OPTYPE_SIG)
        {
          int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;
          if (tmp & (1 << sbit))
            tmp |= 0xFFFFFFFF << sbit;
        }
      if (opd->type & OPTYPE_DIS) {
        /* We have to read register later.  */
        data += tmp;
        dis = 1;
      } else
        {
          if (dis && (opd->type & OPTYPE_REG))
            op[no] = data + eval_reg32 (tmp);
          else
            op[no] = tmp;
          op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0);
          no++;
          data = 0;
          dis = 0;
        }
      if(opd->type & OPTYPE_LAST)
        return;
      opd++;
    }
  num_op = no;
}
 
/* Implementation specific.
   Evaluates source operand op_no. */
 
inline static unsigned long eval_operand32 (int op_no, int *breakpoint)
{
  debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
    /* memory accesses are not cached */
    return eval_mem32 (op[op_no], breakpoint);
  else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
    return eval_reg32 (op[op_no]);
  } else {
    return op[op_no];
  }
}
 
/* Implementation specific.
   Evaluates source operand op_no. */
 
static unsigned long eval_operand16 (int op_no, int *breakpoint)
{
  debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
    return eval_mem16 (op[op_no], breakpoint);
  }
  else {
    fprintf (stderr, "Invalid operand type.\n");
    exit (1);
  }
}
 
/* Implementation specific.
   Evaluates source operand op_no. */
 
static unsigned long eval_operand8 (int op_no, int *breakpoint)
{
  debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
    return eval_mem8 (op[op_no], breakpoint);
  else {
    fprintf (stderr, "Invalid operand type.\n");
    exit (1);
  }
}
 
/* Implementation specific.
   Set destination operand (register direct, register indirect
   (with displacement) with value. */
 
inline static void set_operand32(int op_no, unsigned long value, int* breakpoint)
{
  /* Mark this as destination operand.  */
  IFF (config.cpu.dependstats) op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
    set_mem32(op[op_no], value, breakpoint);
  } else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {
    set_reg32(op[op_no], value);
  } else {
    fprintf (stderr, "Invalid operand type.\n");
    exit (1);
  }
}
 
/* Implementation specific.
   Set destination operand (register direct, register indirect
   (with displacement) with value. */
 
void set_operand16(int op_no, unsigned long value, int* breakpoint)
{
  /* Mark this as destination operand.  */
  op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
    set_mem16(op[op_no], value, breakpoint);
  }
  else
    {
      fprintf (stderr, "Invalid operand type.\n");
      exit (1);
    }
}
 
/* Implementation specific.
   Set destination operand (register direct, register indirect
   (with displacement) with value. */
 
void set_operand8(int op_no, unsigned long value, int* breakpoint)
{
  /* Mark this as destination operand.  */
  op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)
    set_mem8(op[op_no], value, breakpoint);
  else
    {
      fprintf (stderr, "Invalid operand type.\n");
      exit (1);
    }
}
 
/* Sets a new SPR_SR_OV value, based on next register value */
static inline unsigned long set_ov_flag (unsigned long value)
{
#if SET_OV_FLAG
  value & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0);
#endif
  return value;
}
 
/* Modified by CZ 26/05/01 for new mode execution */
/* Fetch returns nonzero if instruction should NOT be executed.  */
static inline int fetch()
{
  struct mem_entry *entry;
  debug(5, "fetch()\n");
 
  /* Update the pc for pending exceptions, or get physical pc */
  if (!pending.valid)
    pc_phy = translate_vrt_to_phy_add(pc);
 
  if(pending.valid)
    except_handle_backend(pending.type, pending.address, pending.saved);
 
  if (CHECK_BREAKPOINTS) {
    /* MM: Check for breakpoint.  This has to be done in fetch cycle,
       because of peripheria.
       MM1709: if we cannot access the memory entry, we could not set the
       breakpoint earlier, so just chech the breakpoint list.  */
    if (has_breakpoint (pc_phy) && !break_just_hit) {
      break_just_hit = 1;
      return 1; /* Breakpoint set. */
    }
    break_just_hit = 0;
  }
  instructions++;
 
  pc_phy &= ~0x03;
 
  /* Fetch instruction. */
  iqueue[0].insn_addr = pc;
  iqueue[0].insn = eval_insn (pc_phy, &breakpoint);;
 
  /* update_pc will be called after execution */
 
  return 0;
}
 
/* This code actually updates the PC value.  */
static inline void update_pc ()
{
  pcprev = pc; /* Store value for later */
  pc = pcnext;
  pcnext = delay_insn ? pcdelay : pcnext + 4;
}
 
static inline void analysis ()
{
  if (config.cpu.dependstats)
    /* Instruction waits in completition buffer until retired. */
    memcpy (&icomplet[0], &iqueue[0], sizeof (struct iqueue_entry));
 
  if (config.sim.history) {
    int i;
 
    /* History of execution */
    for (i = HISTEXEC_LEN - 1; i; i--)
      histexec[i] = histexec[i - 1];
    histexec[0] = icomplet[0].insn_addr;        /* add last insn */
  }
}
 
/* Store buffer analysis - stores are accumulated and commited when IO is idle */
static inline sbuf_store () {
  int delta = cycles - sbuf_prev_cycles;
  int cyc = mem_cycles;
  sbuf_total_cyc += cyc;
  mem_cycles = 0;
 
  /* Take stores from buffer, that occured meanwhile */
  while (delta >= sbuf_buf[sbuf_tail] && sbuf_count) {
    delta -= sbuf_buf[sbuf_tail];
    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
    sbuf_count--;
  }
  if (sbuf_count)
    sbuf_buf[sbuf_tail] -= delta;
 
  /* Store buffer is full, take one out */
  if (sbuf_count >= config.cpu.sbuf_len) {
    sbuf_wait_cyc += sbuf_buf[sbuf_tail];
    mem_cycles += sbuf_buf[sbuf_tail];
    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
    sbuf_count--;
  }
  /* Put newest store in the buffer */
  sbuf_buf[sbuf_head] = cyc;
  sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;
  sbuf_count++;
  sbuf_prev_cycles = cycles;
}
 
/* Store buffer analysis - previous stores should commit, before any load */
static inline sbuf_load () {
  /* Wait for all stores to complete */
  while (sbuf_count > 0) {
    sbuf_wait_cyc += sbuf_buf[sbuf_tail];
    mem_cycles += sbuf_buf[sbuf_tail];
    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;
    sbuf_count--;
  }
}
 
/* Execution logger.  */
inline void dump_exe_log()
{
  unsigned long i = iqueue[0].insn_addr;
 
  if (i == 0xffffffff) return;
  fprintf(runtime.sim.fexe_log, "\nEXECUTED(): %.8lx:  ", i);
  fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));
  fprintf(runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));
  for(i = 0; i < MAX_GPRS; i++) {
    if (i % 4 == 0)
      fprintf(runtime.sim.fexe_log, "\n");
    fprintf(runtime.sim.fexe_log, "GPR%2u: %.8lx  ", i, reg[i]);
  }
  fprintf(runtime.sim.fexe_log, "\n");
  fprintf(runtime.sim.fexe_log, "SR   : %.8lx  ", mfspr(SPR_SR));
  fprintf(runtime.sim.fexe_log, "EPCR0: %.8lx  ", mfspr(SPR_EPCR_BASE));
  fprintf(runtime.sim.fexe_log, "EEAR0: %.8lx  ", mfspr(SPR_EEAR_BASE));
  fprintf(runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));
}
 
#if 0
void print_time (int cycles, char *output)
{
  int i = 0, c_ps = config.sim.clkcycle_ps;
  while (c_ps % 1000 == 0 && i < 2) {
    c_ps /= 1000;
    i++;
  }
  c_ps *= cycles;
  sprintf (output, "%i%cs", cycles, i == 0 ? 'p' : i == 1 ? 'n': 'u');
}
#endif
 
void dumpreg()
{
  int i;
  char temp[100];
 
  dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4, 1, 0);
  generate_time_pretty (temp, cycles);
  printf(" (executed) [time %s, #%i]\n", temp, instructions);
  if (config.cpu.superscalar)
    printf ("Superscalar CYCLES: %u", supercycles);
  if (config.cpu.hazards)
    printf ("  HAZARDWAIT: %u\n", hazardwait);
  else
    if (config.cpu.superscalar)
      printf ("\n");
 
  dumpmemory(pc, pc + 4, 1, 0);
  printf(" (next insn) %s", (delay_insn?"(delay insn)":""));
  for(i = 0; i < MAX_GPRS; i++) {
    if (i % 4 == 0)
      printf("\n");
    printf("GPR%.2u: %.8lx  ", i, evalsim_reg32(i));
  }
  printf("flag: %u\n", flag);
}
 
/* Address calculation changed by CZ on 27/05/01 */
static inline void decode_execute(struct iqueue_entry *current)
{
  int insn_index;
  next_delay_insn = 0;
  breakpoint = 0;
 
  if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy))
    breakpoint++;
 
  IFF (config.cpu.dependstats) current->func_unit = it_unknown;
 
  current->insn_index = insn_index = insn_decode(current->insn);
 
#ifndef HAS_EXECUTION
#error HAS_EXECUTION has to be defined in order to execute programs.
#endif
 
  cur = current;  /* globals; needed by eval/set_operand */
 
  if (insn_index < 0)
    l_invalid();
  else {
    op = &cur->op[0];
    eval_operands (cur->insn, insn_index, &breakpoint);
    or32_opcodes[insn_index].exec();
  }
 
  /* Check for range exception */
  if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))
    except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));
 
  if (config.cpu.dependstats) {
    iqueue[0].insn_index = insn_index;
    /* Dynamic, dependency stats. */
    adddstats(icomplet[0].insn_index, iqueue[0].insn_index, 1, check_depend());
 
    /* Dynamic, functional units stats. */
    addfstats(icomplet[0].func_unit, iqueue[0].func_unit, 1, check_depend());
 
    /* Dynamic, single stats. */
    addsstats(iqueue[0].insn_index, 1);
  }
 
  if (config.cpu.superscalar) {
    if ((cur->func_unit == it_branch) || (cur->func_unit == it_jump))
      storecycles += 0;
 
    if (cur->func_unit == it_store)
      storecycles += 1;
 
    if (cur->func_unit == it_load)
      loadcycles += 1;
#if 0        
    if ((icomplet[0].func_unit == it_load) && check_depend())
      loadcycles++;
#endif
 
    /* Pseudo multiple issue benchmark */
    if ((multissue[cur->func_unit] < 1) || (check_depend())
     || (issued_per_cycle < 1)) {
      int i;
      for (i = 0; i < 20; i++)
        multissue[i] = 2;
      issued_per_cycle = 2;
      supercycles++;
      if (check_depend())
        hazardwait++;
      multissue[it_unknown] = 2;
      multissue[it_shift] = 2;
      multissue[it_compare] = 1;
      multissue[it_branch] = 1;
      multissue[it_jump] = 1;
      multissue[it_extend] = 2;
      multissue[it_nop] = 2;
      multissue[it_move] = 2;
      multissue[it_movimm] = 2;
      multissue[it_arith] = 2;
      multissue[it_store] = 2;
      multissue[it_load] = 2;
    }
    multissue[cur->func_unit]--;
    issued_per_cycle--;
  }
  delay_insn = next_delay_insn;
 
  if(breakpoint)
    except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
}
 
void cpu_reset()
{
  int i;
  cycles = 0;
  instructions = 0;
  supercycles = 0;
  loadcycles = 0;
  storecycles = 0;
  for (i = 0; i < MAX_GPRS; i++)
    set_reg32 (i, 0);
  memset(iqueue, 0, sizeof(iqueue));
  memset(icomplet, 0, sizeof(icomplet));
 
  sbuf_head = 0;
  sbuf_tail = 0;
  sbuf_count = 0;
  sbuf_prev_cycles = 0;
 
  /* Cpu configuration */
  mtspr(SPR_UPR, config.cpu.upr);
  setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);
  setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);
  mtspr(SPR_SR, config.cpu.sr);
 
  pcnext = 0x0; /* MM1409: All programs should start at reset vector entry!  */
  printf ("Starting at 0x%08x\n", pcnext);
  pc = pcnext;
  pc_phy = pc;
  pcnext += 4;
  debug(1, "reset ...\n");
 
  /* MM1409: All programs should set their stack pointer!  */
  except_handle(EXCEPT_RESET, 0);
}
 
inline int cpu_clock ()
{
  if(fetch()) {
    printf ("Breakpoint hit.\n");
    cont_run = 0; /* memory breakpoint encountered */
    return 1;
  }
  decode_execute(&iqueue[0]);
  update_pc();
  analysis();
  if (config.sim.exe_log) dump_exe_log();
  return 0;
}
 
/******************************************
 *    Instruction specific functions.     *
 ******************************************/
 
void l_add() {
  signed long temp1;
  signed char temp4;
 
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  temp1 = (signed long)eval_operand32(2, &breakpoint)+(signed long)eval_operand32(1, &breakpoint);
  set_operand32(0, temp1, &breakpoint);
  set_ov_flag (temp1);
  if (ARITH_SET_FLAG) {
    flag = temp1 == 0;
    setsprbits(SPR_SR, SPR_SR_F, flag);
  }
 
  temp4 = temp1;
  if (temp4 == temp1)
    mstats.byteadd++;
}
void l_sw() {
  IFF (config.cpu.dependstats) cur->func_unit = it_store;
  set_operand32(0, eval_operand32(1, &breakpoint), &breakpoint);
  if (config.cpu.sbuf_len) sbuf_store (mem_cycles);
}
void l_sb() {
  IFF (config.cpu.dependstats) cur->func_unit = it_store;
  set_operand8(0, eval_operand32(1, &breakpoint), &breakpoint);
  if (config.cpu.sbuf_len) sbuf_store (mem_cycles);
}
void l_sh() {
  IFF (config.cpu.dependstats) cur->func_unit = it_store;
  set_operand16(0, eval_operand32(1, &breakpoint), &breakpoint);
  if (config.cpu.sbuf_len) sbuf_store (mem_cycles);
}
void l_lwz() {
  unsigned long val;
  IFF (config.cpu.dependstats) cur->func_unit = it_load;
  if (config.cpu.sbuf_len) sbuf_load ();
  val = eval_operand32(1, &breakpoint);
  /* If eval operand produced exception don't set anything */
  if (!pending.valid)
    set_operand32(0, val, &breakpoint);
}
void l_lbs() {
  signed char val;
  IFF (config.cpu.dependstats) cur->func_unit = it_load;
  if (config.cpu.sbuf_len) sbuf_load ();
  val = eval_operand8(1, &breakpoint);
  /* If eval opreand produced exception don't set anything */
  if (!pending.valid)
    set_operand32(0, val, &breakpoint);
}
void l_lbz() {
  unsigned char val;
  IFF (config.cpu.dependstats) cur->func_unit = it_load;
  if (config.cpu.sbuf_len) sbuf_load ();
  val = eval_operand8(1, &breakpoint);
  /* If eval opreand produced exception don't set anything */
  if (!pending.valid)
    set_operand32(0, val, &breakpoint);
}
void l_lhs() {
  signed short val;
  IFF (config.cpu.dependstats) cur->func_unit = it_load;
  if (config.cpu.sbuf_len) sbuf_load ();
  val = eval_operand16(1, &breakpoint);
  /* If eval opreand produced exception don't set anything */
  if (!pending.valid)
    set_operand32(0, val, &breakpoint);
}
void l_lhz() {
  unsigned short val;
  IFF (config.cpu.dependstats) cur->func_unit = it_load;
  if (config.cpu.sbuf_len) sbuf_load ();
  val = eval_operand16(1, &breakpoint);
  /* If eval opreand produced exception don't set anything */
  if (!pending.valid)
    set_operand32(0, val, &breakpoint);
}
void l_movhi() {
  IFF (config.cpu.dependstats) cur->func_unit = it_movimm;
  set_operand32(0, eval_operand32(1, &breakpoint) << 16, &breakpoint);
}
void l_and() {
  unsigned long temp1;
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  set_operand32(0, temp1 = set_ov_flag (eval_operand32(1, &breakpoint) & (unsigned)eval_operand32(2, &breakpoint)), &breakpoint);
  if (ARITH_SET_FLAG) {
    flag = temp1 == 0;
    setsprbits(SPR_SR, SPR_SR_F, flag);
  }
}
void l_or() {
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) | (unsigned)eval_operand32(2, &breakpoint)), &breakpoint);
}
void l_xor() {
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) ^ (signed)eval_operand32(2, &breakpoint)), &breakpoint);
}
void l_sub() {
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  set_operand32(0, set_ov_flag ((signed long)eval_operand32(1, &breakpoint) - (signed long)eval_operand32(2, &breakpoint)), &breakpoint);
}
/*int mcount = 0;*/
void l_mul() {
  signed long temp3, temp2, temp1;
 
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  set_operand32(0, set_ov_flag ((signed long)eval_operand32(1, &breakpoint) * (signed long)eval_operand32(2, &breakpoint)), &breakpoint);
  /*if (!(mcount++ & 1023)) {
    printf ("[%i]\n",mcount);
    }*/
}
void l_div() {
  signed long temp3, temp2, temp1;
 
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  temp3 = eval_operand32(2, &breakpoint);
  temp2 = eval_operand32(1, &breakpoint);
  if (temp3)
    temp1 = temp2 / temp3;
  else {
    except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
    return;
  }
  set_operand32(0, set_ov_flag (temp1), &breakpoint);
}
void l_divu() {
  unsigned long temp3, temp2, temp1;
 
  IFF (config.cpu.dependstats) cur->func_unit = it_arith;
  temp3 = eval_operand32(2, &breakpoint);
  temp2 = eval_operand32(1, &breakpoint);
  temp1 = temp2 / temp3;
  /* cycles += 16; */
  set_operand32(0, set_ov_flag (temp1), &breakpoint);
}
void l_sll() {
  int sign = 1;
  IFF (config.cpu.dependstats) cur->func_unit = it_shift;
  if ((signed)eval_operand32(1, &breakpoint) < 0)
    sign = -1;
  /* cycles += 2; */
  set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) << eval_operand32(2, &breakpoint)), &breakpoint);
}
void l_sra() {
  unsigned long sign = 0;
  IFF (config.cpu.dependstats) cur->func_unit = it_shift;
 
  if ((signed)eval_operand32(1, &breakpoint) < 0)
    sign = -1;
  /* cycles += 2; */
  set_operand32(0, set_ov_flag ((signed)eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
void l_srl() {
  IFF (config.cpu.dependstats) cur->func_unit = it_shift;
  /* cycles += 2; */
  set_operand32(0, set_ov_flag (eval_operand32(1, &breakpoint) >> eval_operand32(2, &breakpoint)), &breakpoint);
}
void l_bf() {
  if (config.bpb.enabled) {
    int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0;
    IFF (config.cpu.dependstats) cur->func_unit = it_branch;
    mstats.bf[flag][fwd]++;
    bpb_update(cur->insn_addr, flag);
  }
  if (flag) {
    debug(5, "\nl.bf relative: pc=%x pcnext=%x\n", pc, pcnext);
    pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
    btic_update(pcnext);
    next_delay_insn = 1;
  } else {
    btic_update(pc);
  }
}
void l_bnf() {
  if (config.bpb.enabled) {
    int fwd = (eval_operand32(0, &breakpoint) >= pc) ? 1 : 0;
    IFF (config.cpu.dependstats) cur->func_unit = it_branch;
    mstats.bnf[!flag][fwd]++;
    bpb_update(cur->insn_addr, flag == 0);
  }
  if (flag == 0) {
    debug(5, "\nl.bnf relative: pc=%x pcnext=%x\n", pc, pcnext);
    pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
    btic_update(pcnext);
    next_delay_insn = 1;
  } else {
    btic_update(pc);
  }
}
void l_j() {
  debug(5, "\nl.j relative: pc=%x pcnext=%x\n", pc, pcnext);
  pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
  IFF (config.cpu.dependstats) cur->func_unit = it_jump;
  next_delay_insn = 1;
}
void l_jal() {
  debug(5, "\nl.jal relative: pc=%x pcnext=%x\n", pc, pcnext);
  pcdelay = pc + (signed)eval_operand32(0, &breakpoint) * 4;
 
  IFF (config.cpu.dependstats) cur->func_unit = it_jump;
  set_reg32(LINK_REGNO, pc + 8);
  next_delay_insn = 1;
  if (config.sim.profile) {
    struct mem_entry *entry;
    struct label_entry *tmp;
    if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
      fprintf (runtime.sim.fprof, "+%08X %08X %08X %s\n", cycles, pc + 8, pcdelay, tmp->name);
    else
      fprintf (runtime.sim.fprof, "+%08X %08X %08X @%08X\n", cycles, pc + 8, pcdelay, pcdelay);
  }
}
void l_jalr() {
  IFF (config.cpu.dependstats) cur->func_unit = it_jump;
  pcdelay = eval_operand32(0, &breakpoint);
  set_reg32(LINK_REGNO, pc + 8);
  next_delay_insn = 1;
}
void l_jr() {
  IFF (config.cpu.dependstats) cur->func_unit = it_jump;
  pcdelay = eval_operand32(0, &breakpoint);
  next_delay_insn = 1;
  if (config.sim.profile)
    fprintf (runtime.sim.fprof, "-%08X %08X\n", cycles, pcdelay);
}
void l_rfe() {
  IFF (config.cpu.dependstats) cur->func_unit = it_exception;
  pcnext = mfspr(SPR_EPCR_BASE);
  mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
}
void l_nop() {
  unsigned long stackaddr;
  int k = eval_operand32(0, &breakpoint);
  IFF (config.cpu.dependstats) cur->func_unit = it_nop;
  switch (k) {
    case NOP_NOP:
      break;
    case NOP_EXIT:
      printf("exit(%d)\n", evalsim_reg32 (3));
      if (config.debug.gdb_enabled)
        set_stall_state (1);
      else
        cont_run = 0;
      break;
    case NOP_PRINTF:
      stackaddr = evalsim_reg32(4);
      simprintf(stackaddr, evalsim_reg32(3));
      debug(5, "simprintf %x\n", stackaddr);
      break;
    case NOP_REPORT:
      printf("report(0x%x);\n", evalsim_reg32(3));
    default:
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
      printf("report %i (0x%x);\n", k - NOP_REPORT_FIRST, evalsim_reg32(3));
      break;
  }
}
void l_sfeq() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = eval_operand32(0, &breakpoint) == eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfne() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = eval_operand32(0, &breakpoint) != eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfgts() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (signed)eval_operand32(0, &breakpoint) > (signed)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfges() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (signed)eval_operand32(0, &breakpoint) >= (signed)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sflts() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (signed)eval_operand32(0, &breakpoint) < (signed)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfles() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (signed)eval_operand32(0, &breakpoint) <= (signed)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfgtu() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (unsigned)eval_operand32(0, &breakpoint) > (unsigned)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfgeu() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (unsigned)eval_operand32(0, &breakpoint) >= (unsigned) eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfltu() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (unsigned)eval_operand32(0, &breakpoint) < (unsigned)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_sfleu() {
  IFF (config.cpu.dependstats) cur->func_unit = it_compare;
  flag = (unsigned)eval_operand32(0, &breakpoint) <= (unsigned)eval_operand32(1, &breakpoint);
  setsprbits(SPR_SR, SPR_SR_F, flag);
}
void l_extbs() {
  unsigned char x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (signed long)x, &breakpoint);
}
void l_extbz() {
  unsigned char x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (unsigned long)x, &breakpoint);
}
void l_exths() {
  unsigned short x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (signed long)x, &breakpoint);
}
void l_exthz() {
  unsigned short x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (unsigned long)x, &breakpoint);
}
void l_extws() {
  unsigned int x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (signed long)x, &breakpoint);
}
void l_extwz() {
  unsigned int x;
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  x = eval_operand32(1, &breakpoint);
  set_operand32(0, (unsigned long)x, &breakpoint);
}
void l_mtspr() {
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  if (mfspr(SPR_SR) & SPR_SR_SM)
    mtspr(eval_operand32(0, &breakpoint) + eval_operand32(2, &breakpoint), eval_operand32(1, &breakpoint));
  else {
    printf("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
    cont_run = 0;
  }
}
void l_mfspr() {
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  if (mfspr(SPR_SR) & SPR_SR_SM)
    set_operand32(0, mfspr(eval_operand32(1, &breakpoint) + eval_operand32(2, &breakpoint)), &breakpoint);
  else {
    set_operand32(0, 0, &breakpoint);
    printf("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
    cont_run = 0;
  }
}
void l_sys() {
  except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
}
void l_trap() {
  /* TODO: some SR related code here! */
  except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
}
void l_mac() {
  sprword lo, hi;
  LONGEST l;
  long x, y;
  IFF (config.cpu.dependstats) cur->func_unit = it_mac;
  lo = mfspr (SPR_MACLO);
  hi = mfspr (SPR_MACHI);
  x = eval_operand32(0, &breakpoint);
  y = eval_operand32(1, &breakpoint);
  printf ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
  l += (LONGEST) x * (LONGEST) y;
 
  /* This implementation is very fast - it needs only one cycle for mac.  */
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
  hi = ((LONGEST)l) >> 32;
  mtspr (SPR_MACLO, lo);
  mtspr (SPR_MACHI, hi);
  printf ("(%08x,%08x)\n", hi, lo);
}
void l_msb() {
  sprword lo, hi;
  LONGEST l;
  long x, y;
  IFF (config.cpu.dependstats) cur->func_unit = it_mac;
  lo = mfspr (SPR_MACLO);
  hi = mfspr (SPR_MACHI);
  x = eval_operand32(0, &breakpoint);
  y = eval_operand32(1, &breakpoint);
  printf ("[%08x,%08x]\t", (unsigned long)(x), (unsigned long)(y));
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
  l -= (LONGEST) eval_operand32(0, &breakpoint) * (LONGEST)eval_operand32(1, &breakpoint);
 
  /* This implementation is very fast - it needs only one cycle for msb.  */
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
  hi = ((LONGEST)l) >> 32;
  mtspr (SPR_MACLO, lo);
  mtspr (SPR_MACHI, hi);
  printf ("(%08x,%08x)\n", hi, lo);
}
void l_macrc() {
  sprword lo, hi;
  LONGEST l;
  IFF (config.cpu.dependstats) cur->func_unit = it_mac;
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
  lo =  mfspr (SPR_MACLO);
  hi =  mfspr (SPR_MACHI);
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
  l >>= 28;
  //printf ("<%08x>\n", (unsigned long)l);
  set_operand32(0, (long)l, &breakpoint);
  mtspr (SPR_MACLO, 0);
  mtspr (SPR_MACHI, 0);
}
void l_cmov() {
  IFF (config.cpu.dependstats) cur->func_unit = it_move;
  set_operand32 (0, flag ? eval_operand32(1, &breakpoint) : eval_operand32(2, &breakpoint), &breakpoint);
}
void l_cust1() {
  /*int destr = cur->insn >> 21;
    int src1r = cur->insn >> 15;
    int src2r = cur->insn >> 9;*/
}
void l_cust2() {
}
void l_cust3() {
}
void l_cust4() {
}
void l_invalid() {
  except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
}

Line No.	Rev	Author	Line
1	2	cvs	`/* execute.c -- OR1K architecture dependent simulation`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* Most of the OR1K simulation is done in here. */`
21
22			`#include <stdlib.h>`
23			`#include <stdio.h>`
24			`#include <string.h>`
25			`#include <ctype.h>`
26
27	123	markom	`#include "config.h"`
28	2	cvs	`#include "arch.h"`
29	133	markom	`#include "opcode/or32.h"`
30	2	cvs	`#include "branch_predict.h"`
31			`#include "abstract.h"`
32	261	markom	`#include "labels.h"`
33	2	cvs	`#include "parse.h"`
34			`#include "execute.h"`
35			`#include "stats.h"`
36	54	lampret	`#include "except.h"`
37			`#include "sprs.h"`
38	102	lampret	`#include "sim-config.h"`
39	123	markom	`#include "debug_unit.h"`
40	2	cvs
41	615	markom	`/* Whether instructions set overflow flag */`
42			`#define SET_OV_FLAG 1`
43
44			`/* Whether arithmethic instructions set flag on zero */`
45	620	markom	`#define ARITH_SET_FLAG 1`
46	615	markom
47	2	cvs	`/* General purpose registers. */`
48			`machword reg[MAX_GPRS];`
49
50			`/* Instruction queue */`
51			`struct iqueue_entry iqueue[20];`
52
53	83	lampret	`/* Is current insn in execution a delay insn? */`
54			`int delay_insn;`
55
56	2	cvs	`/* Benchmark multi issue execution */`
57			`int multissue[20];`
58			`int supercycles;`
59	6	lampret	`int issued_per_cycle = 4;`
60			`int hazardwait = 0;`
61	2	cvs
62	431	markom	`/* Whether break was hit - so we can step over a break */`
63			`static int break_just_hit = 0;`
64
65	68	lampret	`/* freemem 'pointer' */`
66			`extern unsigned long freemem;`
67
68	2	cvs	`/* Completition queue */`
69	138	markom	`struct iqueue_entry icomplet[20];`
70	2	cvs
71	77	lampret	`/* Program counter (and translated PC) */`
72	2	cvs	`unsigned long pc;`
73	77	lampret	`unsigned long pc_phy;`
74	2	cvs
75	378	markom	`/* Previous program counter */`
76	479	markom	`unsigned long pcprev = 0;`
77	378	markom
78	2	cvs	`/* Temporary program counter */`
79	83	lampret	`unsigned long pcnext;`
80	2	cvs
81	123	markom	`/* Delay instruction effective address register */`
82			`unsigned long pcdelay;`
83
84	2	cvs	`/* CCR */`
85			`int flag;`
86
87			`/* CCR (for dependency calculation) */`
88			`char ccr_flag[10] = "flag";`
89
90			`/* Cycles counts fetch stages */`
91			`int cycles;`
92
93	537	markom	`/* Each cycle has counter of mem_cycles; this value is joined with cycles`
94			`at the end of the cycle; no sim originated memory accesses should be`
95			`performed inbetween. */`
96			`int mem_cycles;`
97
98	535	markom	`/* Instructions executed */`
99			`int instructions;`
100
101	6	lampret	`/* Load and store stalls */`
102			`int loadcycles, storecycles;`
103
104	626	markom	`/* Store buffer analysis - stores are accumulated and commited when IO is idle */`
105			`static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;`
106			`static int sbuf_buf[MAX_SBUF_LEN] = {0};`
107			`static int sbuf_prev_cycles = 0;`
108
109			`/* Num cycles waiting for stores to complete */`
110			`int sbuf_wait_cyc = 0;`
111
112			`/* Number of total store cycles */`
113			`int sbuf_total_cyc = 0;`
114
115	138	markom	`/* Local data needed for execution. */`
116			`static struct iqueue_entry *cur;`
117			`static int next_delay_insn;`
118			`static int breakpoint;`
119			`static unsigned long *op;`
120			`static int num_op;`
121
122	2	cvs	`/* Implementation specific.`
123			`Get an actual value of a specific register. */`
124
125	560	markom	`unsigned long evalsim_reg32(int regno)`
126	2	cvs	`{`
127	138	markom	`if (regno < MAX_GPRS) {`
128	560	markom	`return reg[regno];`
129			`} else {`
130			`printf("\nABORT: read out of registers\n");`
131			`cont_run = 0;`
132			`return 0;`
133			`}`
134			`}`
135
136			`/* Implementation specific.`
137			`Set a specific register with value. */`
138
139			`void setsim_reg32(int regno, unsigned long value)`
140			`{`
141			`if (regno == 0) /* gpr0 is always zero */`
142			`value = 0;`
143
144			`if (regno < MAX_GPRS) {`
145			`reg[regno] = value;`
146			`} else {`
147			`printf("\nABORT: write out of registers\n");`
148			`cont_run = 0;`
149			`}`
150			`}`
151
152			`/* Implementation specific.`
153			`Get an actual value of a specific register. */`
154
155			`inline static unsigned long eval_reg32(int regno)`
156			`{`
157			`if (regno < MAX_GPRS) {`
158			`IFF(config.cpu.raw_range) {`
159	535	markom	`int delta = (cycles - raw_stats.reg[regno]);`
160	606	markom	`if ((unsigned long)delta < (unsigned long)config.cpu.raw_range)`
161	535	markom	`raw_stats.range[delta]++;`
162			`}`
163	344	markom	`debug(9, "atoi ret1\n");`
164	138	markom	`return reg[regno];`
165			`} else {`
166	393	markom	`printf("\nABORT: read out of registers\n");`
167	138	markom	`cont_run = 0;`
168			`return 0;`
169			`}`
170	2	cvs	`}`
171
172			`/* Implementation specific.`
173			`Set a specific register with value. */`
174
175	560	markom	`inline static void set_reg32(int regno, unsigned long value)`
176	2	cvs	`{`
177	262	markom	`#if 0`
178	138	markom	`if (strcmp(regstr, FRAME_REG) == 0) {`
179			`printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc);`
180			`printf("Old:%.8lx New:%.8lx\n", eval_reg(regno), value);`
181			`}`
182
183			`if (strcmp(regstr, STACK_REG) == 0) {`
184			`printf("SP (%s) modified by insn at %x. ", STACK_REG, pc);`
185			`printf("Old:%.8lx New:%.8lx\n", eval_reg(regmo), value);`
186			`}`
187	2	cvs	`#endif`
188	560	markom
189	138	markom	`if (regno < MAX_GPRS) {`
190			`reg[regno] = value;`
191	560	markom	`IFF(config.cpu.raw_range)`
192	535	markom	`raw_stats.reg[regno] = cycles;`
193	138	markom	`} else {`
194	393	markom	`printf("\nABORT: write out of registers\n");`
195	138	markom	`cont_run = 0;`
196			`}`
197	2	cvs	`}`
198
199			`/* Does srcoperand depend on computation of dstoperand? Return`
200			`non-zero if yes.`
201
202	262	markom	`Cycle t Cycle t+1`
203			`dst: irrelevant src: immediate always 0`
204			`dst: reg1 direct src: reg2 direct 0 if reg1 != reg2`
205			`dst: reg1 disp src: reg2 direct always 0`
206			`dst: reg1 direct src: reg2 disp 0 if reg1 != reg2`
207			`dst: reg1 disp src: reg2 disp always 1 (store must`
208			`finish before load)`
209	138	markom	`dst: flag src: flag always 1`
210	2	cvs	`*/`
211
212	138	markom	`int depend_operands(prev, next)`
213			`struct iqueue_entry *prev;`
214			`struct iqueue_entry *next;`
215	2	cvs	`{`
216	138	markom	`/* Find destination type. */`
217			`unsigned long type = 0;`
218			`int i = 0;`
219			`if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG`
220			`&& or32_opcodes[next->insn_index].flags & OR32_R_FLAG)`
221			`return 1;`
222	2	cvs
223	138	markom	`while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))`
224			`if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)`
225			`{`
226	262	markom	`type = prev->op[i + MAX_OPERANDS];`
227			`break;`
228	138	markom	`}`
229			`else`
230			`i++;`
231	560	markom
232	138	markom	`/* We search all source operands - if we find confict => return 1 */`
233			`i = 0;`
234			`while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))`
235			`if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))`
236			`{`
237	262	markom	`if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS)`
238			`if (type & OPTYPE_DIS)`
239			`return 1;`
240			`else if (next->op[i] == prev->op[i]`
241			`&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG))`
242			`return 1;`
243			`if (next->op[i] == prev->op[i]`
244			`&& (next->op[i + MAX_OPERANDS] & OPTYPE_REG)`
245			`&& (type & OPTYPE_REG))`
246			`return 1;`
247			`i++;`
248	138	markom	`}`
249			`else`
250			`i++;`
251			`return 0;`
252			`}`
253	2	cvs
254	138	markom	`/* Implementation specific.`
255			`Parses and returns operands. */`
256	2	cvs
257	138	markom	`static void`
258			`eval_operands (unsigned long insn, int insn_index, int* breakpoint)`
259			`{`
260			`struct insn_op_struct *opd = op_start[insn_index];`
261			`unsigned long data = 0;`
262			`int dis = 0;`
263			`int no = 0;`
264	560	markom
265	138	markom	`while (1)`
266			`{`
267			`unsigned long tmp = 0, nbits = 0;`
268			`while (1)`
269	262	markom	`{`
270			`tmp \|= ((insn >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;`
271			`nbits += opd->data;`
272			`if (opd->type & OPTYPE_OP)`
273			`break;`
274			`opd++;`
275			`}`
276	2	cvs
277	138	markom	`/* Do we have to sign extend? */`
278			`if (opd->type & OPTYPE_SIG)`
279	262	markom	`{`
280			`int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;`
281			`if (tmp & (1 << sbit))`
282			`tmp \|= 0xFFFFFFFF << sbit;`
283			`}`
284	138	markom	`if (opd->type & OPTYPE_DIS) {`
285	262	markom	`/* We have to read register later. */`
286			`data += tmp;`
287			`dis = 1;`
288	138	markom	`} else`
289	262	markom	`{`
290			`if (dis && (opd->type & OPTYPE_REG))`
291	560	markom	`op[no] = data + eval_reg32 (tmp);`
292	262	markom	`else`
293			`op[no] = tmp;`
294			`op[no + MAX_OPERANDS] = opd->type \| (dis ? OPTYPE_DIS : 0);`
295			`no++;`
296			`data = 0;`
297			`dis = 0;`
298			`}`
299	138	markom	`if(opd->type & OPTYPE_LAST)`
300	262	markom	`return;`
301	138	markom	`opd++;`
302			`}`
303			`num_op = no;`
304	2	cvs	`}`
305
306			`/* Implementation specific.`
307	138	markom	`Evaluates source operand op_no. */`
308
309	560	markom	`inline static unsigned long eval_operand32 (int op_no, int *breakpoint)`
310	2	cvs	`{`
311	344	markom	`debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);`
312	538	markom	`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)`
313	560	markom	`/* memory accesses are not cached */`
314	138	markom	`return eval_mem32 (op[op_no], breakpoint);`
315	560	markom	`else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {`
316			`return eval_reg32 (op[op_no]);`
317			`} else {`
318	138	markom	`return op[op_no];`
319	560	markom	`}`
320	2	cvs	`}`
321
322			`/* Implementation specific.`
323	221	markom	`Evaluates source operand op_no. */`
324
325	560	markom	`static unsigned long eval_operand16 (int op_no, int *breakpoint)`
326	221	markom	`{`
327	344	markom	`debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);`
328	458	simons	`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {`
329	221	markom	`return eval_mem16 (op[op_no], breakpoint);`
330	458	simons	`}`
331	221	markom	`else {`
332			`fprintf (stderr, "Invalid operand type.\n");`
333			`exit (1);`
334			`}`
335			`}`
336
337			`/* Implementation specific.`
338			`Evaluates source operand op_no. */`
339
340	560	markom	`static unsigned long eval_operand8 (int op_no, int *breakpoint)`
341	221	markom	`{`
342	344	markom	`debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);`
343	221	markom	`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)`
344			`return eval_mem8 (op[op_no], breakpoint);`
345			`else {`
346			`fprintf (stderr, "Invalid operand type.\n");`
347			`exit (1);`
348			`}`
349			`}`
350
351			`/* Implementation specific.`
352	2	cvs	`Set destination operand (register direct, register indirect`
353			`(with displacement) with value. */`
354
355	560	markom	`inline static void set_operand32(int op_no, unsigned long value, int* breakpoint)`
356	2	cvs	`{`
357	138	markom	`/* Mark this as destination operand. */`
358	560	markom	`IFF (config.cpu.dependstats) op[op_no + MAX_OPERANDS] \|= OPTYPE_DST;`
359	458	simons	`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {`
360	138	markom	`set_mem32(op[op_no], value, breakpoint);`
361	560	markom	`} else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {`
362	138	markom	`set_reg32(op[op_no], value);`
363	560	markom	`} else {`
364			`fprintf (stderr, "Invalid operand type.\n");`
365			`exit (1);`
366	458	simons	`}`
367	2	cvs	`}`
368
369	221	markom	`/* Implementation specific.`
370			`Set destination operand (register direct, register indirect`
371			`(with displacement) with value. */`
372
373			`void set_operand16(int op_no, unsigned long value, int* breakpoint)`
374			`{`
375			`/* Mark this as destination operand. */`
376	560	markom	`op[op_no + MAX_OPERANDS] \|= OPTYPE_DST;`
377	458	simons	`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {`
378	221	markom	`set_mem16(op[op_no], value, breakpoint);`
379	458	simons	`}`
380	574	markom	`else`
381	221	markom	`{`
382			`fprintf (stderr, "Invalid operand type.\n");`
383			`exit (1);`
384			`}`
385			`}`
386
387			`/* Implementation specific.`
388			`Set destination operand (register direct, register indirect`
389			`(with displacement) with value. */`
390
391			`void set_operand8(int op_no, unsigned long value, int* breakpoint)`
392			`{`
393			`/* Mark this as destination operand. */`
394			`op[op_no + MAX_OPERANDS] \|= OPTYPE_DST;`
395			`if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)`
396			`set_mem8(op[op_no], value, breakpoint);`
397			`else`
398			`{`
399			`fprintf (stderr, "Invalid operand type.\n");`
400			`exit (1);`
401			`}`
402			`}`
403
404	605	markom	`/* Sets a new SPR_SR_OV value, based on next register value */`
405			`static inline unsigned long set_ov_flag (unsigned long value)`
406			`{`
407	615	markom	`#if SET_OV_FLAG`
408	605	markom	`value & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0);`
409	615	markom	`#endif`
410	605	markom	`return value;`
411			`}`
412
413	123	markom	`/* Modified by CZ 26/05/01 for new mode execution */`
414			`/* Fetch returns nonzero if instruction should NOT be executed. */`
415	557	markom	`static inline int fetch()`
416			`{`
417	221	markom	`struct mem_entry *entry;`
418	344	markom	`debug(5, "fetch()\n");`
419	123	markom
420	557	markom	`/* Update the pc for pending exceptions, or get physical pc */`
421	574	markom	`if (!pending.valid)`
422			`pc_phy = translate_vrt_to_phy_add(pc);`
423
424	557	markom	`if(pending.valid)`
425			`except_handle_backend(pending.type, pending.address, pending.saved);`
426	464	simons
427	557	markom	`if (CHECK_BREAKPOINTS) {`
428			`/* MM: Check for breakpoint. This has to be done in fetch cycle,`
429			`because of peripheria.`
430			`MM1709: if we cannot access the memory entry, we could not set the`
431			`breakpoint earlier, so just chech the breakpoint list. */`
432			`if (has_breakpoint (pc_phy) && !break_just_hit) {`
433			`break_just_hit = 1;`
434			`return 1; /* Breakpoint set. */`
435			`}`
436			`break_just_hit = 0;`
437	431	markom	`}`
438	535	markom	`instructions++;`
439	378	markom
440	538	markom	`pc_phy &= ~0x03;`
441
442	378	markom	`/* Fetch instruction. */`
443	560	markom	`iqueue[0].insn_addr = pc;`
444			`iqueue[0].insn = eval_insn (pc_phy, &breakpoint);;`
445	557	markom
446	378	markom	`/* update_pc will be called after execution */`
447	77	lampret
448	378	markom	`return 0;`
449	2	cvs	`}`
450
451	479	markom	`/* This code actually updates the PC value. */`
452	626	markom	`static inline void update_pc ()`
453	142	chris	`{`
454	479	markom	`pcprev = pc; /* Store value for later */`
455			`pc = pcnext;`
456			`pcnext = delay_insn ? pcdelay : pcnext + 4;`
457	2	cvs	`}`
458
459	626	markom	`static inline void analysis ()`
460	2	cvs	`{`
461	394	markom	`if (config.cpu.dependstats)`
462	123	markom	`/* Instruction waits in completition buffer until retired. */`
463	138	markom	`memcpy (&icomplet[0], &iqueue[0], sizeof (struct iqueue_entry));`
464
465	394	markom	`if (config.sim.history) {`
466	263	markom	`int i;`
467
468	123	markom	`/* History of execution */`
469			`for (i = HISTEXEC_LEN - 1; i; i--)`
470			`histexec[i] = histexec[i - 1];`
471	262	markom	`histexec[0] = icomplet[0].insn_addr; /* add last insn */`
472	123	markom	`}`
473	2	cvs	`}`
474
475	626	markom	`/* Store buffer analysis - stores are accumulated and commited when IO is idle */`
476			`static inline sbuf_store () {`
477			`int delta = cycles - sbuf_prev_cycles;`
478			`int cyc = mem_cycles;`
479			`sbuf_total_cyc += cyc;`
480			`mem_cycles = 0;`
481
482			`/* Take stores from buffer, that occured meanwhile */`
483			`while (delta >= sbuf_buf[sbuf_tail] && sbuf_count) {`
484			`delta -= sbuf_buf[sbuf_tail];`
485			`sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;`
486			`sbuf_count--;`
487			`}`
488			`if (sbuf_count)`
489			`sbuf_buf[sbuf_tail] -= delta;`
490
491			`/* Store buffer is full, take one out */`
492			`if (sbuf_count >= config.cpu.sbuf_len) {`
493			`sbuf_wait_cyc += sbuf_buf[sbuf_tail];`
494			`mem_cycles += sbuf_buf[sbuf_tail];`
495			`sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;`
496			`sbuf_count--;`
497			`}`
498			`/* Put newest store in the buffer */`
499			`sbuf_buf[sbuf_head] = cyc;`
500			`sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;`

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