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/* 16450.c -- Simulation of 8250/16450 serial UART
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data
   via file streams, we can't simulate modem control lines coming from the
   DCE and similar details of communication with the DCE.
 
   This simulated UART device is intended for basic UART device driver
   verification. From device driver perspective this device looks like a
   regular UART but never reports and modem control lines changes (the
   only DCE responses are incoming characters from the file stream).
*/
 
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "16450.h"
#include "sim-config.h"
#include "pic.h"
#include "vapi.h"
#include "sched.h"
#include "channel.h"
#include "debug.h"
 
#define MIN(a,b) ((a) < (b) ? (a) : (b))
 
/* Number of clock cycles (one clock cycle is one call to the uart_clock())
   before a single character is transmitted or received. */
static unsigned long char_clks(int dll, int dlh, int lcr)
{
  float bauds_per_char = 1.;
  unsigned long char_clks = ((dlh << 8) + dll);
 
  if (lcr & UART_LCR_PARITY)
    bauds_per_char = bauds_per_char + 1.;
 
  /* stop bits 1 or two */
  if (lcr & UART_LCR_STOP)
    bauds_per_char = bauds_per_char + 2.;
  else
    if ((lcr & 0x3) != 0)
      bauds_per_char = bauds_per_char + 1.;
    else
      bauds_per_char = bauds_per_char + 1.5;
 
  bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));
 
  return char_clks * bauds_per_char;
}
 
/* Set a specific UART register with value. */
void uart_write_byte(oraddr_t addr, uint32_t value, void *dat)
{
  struct dev_16450 *uart = dat;
 
  debug(4, "uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        uart->regs.dll = value;
        uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
        return;
      case UART_DLH:
        uart->regs.dlh = value;
        return;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_TXBUF:
      if (uart->istat.txbuf_full < uart->fifo_len) {
        uart->istat.txbuf_full++;
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
        uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;
      } else
        uart->regs.txbuf[uart->istat.txbuf_head] = value;
 
      uart->regs.lsr &= ~(UART_LSR_TXSERE | UART_LSR_TXBUFE);
      if (uart->regs.iir & UART_IIR_THRI)
        uart->istat.thre_int = 0;
      break;
    case UART_FCR:
      uart->regs.fcr = value & UART_VALID_FCR;
      if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))
       || (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))
        value |= UART_FCR_RRXFI | UART_FCR_RTXFI;
      uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;
      if (value & UART_FCR_RTXFI) {
        uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
        uart->istat.txbuf_full = 0;
        uart->regs.lsr |= UART_LSR_TXBUFE;
 
        // For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty
        uart->istat.thre_int = (uart->fifo_len == 16);
      }
      if (value & UART_FCR_RRXFI) {
        uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
        uart->istat.rxbuf_full = 0;
        uart->regs.lsr &= ~UART_LSR_RDRDY;
      }
      break;
    case UART_IER:
      uart->regs.ier = value & UART_VALID_IER;
      break;
    case UART_LCR:
      uart->regs.lcr = value & UART_VALID_LCR;
      uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);
      break;
    case UART_MCR:
      uart->regs.mcr = value & UART_VALID_MCR;
      break;
    case UART_SCR:
      uart->regs.scr = value;
      break;
    default:
      debug(1, "write out of range (addr %x)\n", addr);
  }
}
 
/* Read a specific UART register. */
uint32_t uart_read_byte(oraddr_t addr, void *dat)
{
  struct dev_16450 *uart = dat;
  uint8_t value = 0;
 
  debug(4, "uart_read_byte(%"PRIxADDR")", addr);
 
  if (uart->regs.lcr & UART_LCR_DLAB) {
    switch (addr % UART_ADDR_SPACE) {
      case UART_DLL:
        value = uart->regs.dll;
        debug(4, "= %"PRIx8"\n", value);
        return value;
      case UART_DLH:
        value = uart->regs.dlh;
        debug(4, "= %"PRIx8"\n", value);
        return value;
    }
  }
 
  switch (addr % UART_ADDR_SPACE) {
    case UART_RXBUF:
      { /* Print out FIFO for debugging */
        int i;
        debug(4, "(%i/%i,%i,%i:", uart->istat.rxbuf_full, uart->fifo_len,
                  uart->istat.rxbuf_head, uart->istat.rxbuf_tail);
        for (i = 0; i < uart->istat.rxbuf_full; i++)
          debug(4, "%02x ", uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);
        debug(4, ")");
      }
      if (uart->istat.rxbuf_full) {
        value = uart->regs.rxbuf[uart->istat.rxbuf_tail];
        uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;
        uart->istat.rxbuf_full--;
      }
 
      if (uart->istat.rxbuf_full)
        uart->regs.lsr |= UART_LSR_RDRDY;
      else
        uart->regs.lsr &= ~UART_LSR_RDRDY;
 
      uart->istat.timeout_count = 0;
      break;
    case UART_IER:
      value = uart->regs.ier & UART_VALID_IER;
      break;
    case UART_IIR:
      value = (uart->regs.iir & UART_VALID_IIR) | 0xc0;
      if (uart->regs.iir & UART_IIR_THRI)
        uart->istat.thre_int = 0;
      break;
    case UART_LCR:
      value = uart->regs.lcr & UART_VALID_LCR;
      break;
    case UART_MCR:
      value = 0;
      break;
    case UART_LSR:
      value = uart->regs.lsr & UART_VALID_LSR;
      uart->regs.lsr &=
        ~(UART_LSR_OVRRUN | UART_LSR_BREAK | UART_LSR_PARITY
         | UART_LSR_FRAME | UART_LSR_RXERR);
      break;
    case UART_MSR:
      value = uart->regs.msr & UART_VALID_MSR;
      uart->regs.msr = 0;
      break;
    case UART_SCR:
      value = uart->regs.scr;
      break;
    default:
      debug(1, "read out of range (addr %"PRIxADDR")\n", addr);
  }
  debug(4, " = %"PRIx8"\n", value);
  return value;
}
 
/* Function that handles incoming VAPI data.  */
void uart_vapi_read (unsigned long id, unsigned long data, void *dat)
{
  struct dev_16450 *uart = dat;
  debug(4, "UART: id %08lx, data %08lx\n", id, data);
  uart->vapi_buf[uart->vapi_buf_head_ptr] = data;
  uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;
  if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {
    fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");
    exit (1);
  }
}
 
static void send_char (struct dev_16450 *uart, int bits_send)
{
  PRINTF ("%c", (char)uart->iregs.txser);
  debug(4, "TX \'%c\' via UART at %"PRIxADDR"...\n", (char)uart->iregs.txser,
        uart->baseaddr);
  if (uart->regs.mcr & UART_MCR_LOOP)
    uart->iregs.loopback = uart->iregs.txser;
  else {
    /* Send to either VAPI or to file */
    if (uart->vapi_id) {
      int par, pe, fe, nbits;
      int j, data;
      unsigned long packet = 0;
 
      nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);
      /* Encode a packet */
      packet = uart->iregs.txser & ((1 << nbits) - 1);
 
      /* Calculate parity */
      for (j = 0, par = 0; j < nbits; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->regs.lcr & UART_LCR_PARITY) {
        if (uart->regs.lcr & UART_LCR_SPAR) {
          packet |= 1 << nbits;
        } else {
          if (uart->regs.lcr & UART_LCR_EPAR)
            packet |= par << nbits;
          else
            packet |= (par ^ 1) << nbits;
        }
        nbits++;
      }
      packet |= 1 << (nbits++);
      if (uart->regs.lcr & UART_LCR_STOP)
        packet |= 1 << (nbits++);
 
      /* Decode a packet */
      nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;
      data = packet & ((1 << nbits) - 1);
 
      /* Calculate parity, including parity bit */
      for (j = 0, par = 0; j < nbits + 1; j++)
        par ^= (packet >> j) & 1;
 
      if (uart->vapi.lcr & UART_LCR_PARITY) {
        if (uart->vapi.lcr & UART_LCR_SPAR) {
          pe = !((packet >> nbits) & 1);
        } else {
          if (uart->vapi.lcr & UART_LCR_EPAR)
            pe = par != 0;
          else
            pe = par != 1;
        }
        nbits++;
      } else
        pe = 0;
 
      fe = ((packet >> (nbits++)) & 1) ^ 1;
      if (uart->vapi.lcr & UART_LCR_STOP)
        fe |= ((packet >> (nbits++)) & 1) ^ 1;
 
      debug (4, "lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);
      data |= (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.lcr << 8);
      PRINTF ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
      debug (4, "vapi_send (%08lx, %08x)\n", uart->vapi_id, data);
      vapi_send (uart->vapi_id, data);
    } else {
      char buffer[1] = { uart->iregs.txser & 0xFF };
      channel_write(uart->channel, buffer, 1);
    }
  }
  uart->istat.txser_full = 0;
  uart->istat.txser_clks = 0;
}
 
/* Adds a character to the FIFO */
 
void uart_add_char (struct dev_16450 *uart, int ch)
{
  if (uart->istat.rxbuf_full + 1 > uart->fifo_len)
    uart->regs.lsr |= UART_LSR_OVRRUN | UART_LSR_RXERR;
  else {
    debug(4, "add %02x\n", ch);
    uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;
    uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;
    uart->istat.rxbuf_full++;
  }
  uart->regs.lsr |= UART_LSR_RDRDY;
  uart->istat.timeout_count = 0;
}
 
/* Simulation hook. Must be called every clock cycle to simulate all UART
   devices. It does internal functional UART simulation. */
void uart_clock16 (void *dat)
{
  struct dev_16450 *uart = dat;
  int retval;
 
  /* Schedule for later */
  SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
 
  /* If VAPI is not selected, UART communicates with two file streams;
     if VAPI is selected, we use VAPI streams.  */
  /* if txfs is corrupted, skip this uart. */
  if (!uart->vapi_id && !channel_ok(uart->channel)) return;
 
  if (uart->vapi.next_break_cnt >= 0)
    if (--uart->vapi.next_break_cnt < 0) {
      if (!(uart->vapi.cur_break = uart->vapi.next_break))
        uart->istat.break_set = 0;
    }
 
  /***************** Transmit *****************/
  if (!uart->istat.txser_full) {
//      uart->regs.lsr |= UART_LSR_TXBUFE;
    if (uart->istat.txbuf_full) {
      uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];
      uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;
      uart->istat.txser_full = 1;
      uart->istat.txbuf_full--;
      uart->regs.lsr &= ~UART_LSR_TXSERE;
 
      // When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,
      // the THRE interrupt is raised when THR transitions from full to empty.
      if (!uart->istat.txbuf_full) {
        uart->istat.thre_int = 1;
        uart->regs.lsr |= UART_LSR_TXBUFE;
      }
    } else {
      uart->regs.lsr |= UART_LSR_TXSERE;
    }
  } else if (uart->char_clks <= uart->istat.txser_clks++) {
    send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */
  } else {
    /* We are still sending char here*/
 
    /* Check if we set the break bit */
    if (uart->regs.lcr & UART_LCR_SBC) {
      if (!uart->vapi.break_sent) {
#if 0
        /* Send broken frame */
        int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;
        send_char(i, nbits_sent);
#endif
        /* Send one break signal */
        vapi_send (uart->vapi_id, UART_LCR_SBC << 8);
        uart->vapi.break_sent = 1;
      }
      /* mark as character was sent */
      uart->istat.txser_full = 0;
      uart->istat.txser_clks = 0;
    } else
      uart->vapi.break_sent = 0;
 
  }
 
  /***************** Receive *****************/
 
  /* Is there a break? */
  if (uart->vapi.cur_break) {
    uart->vapi.cur_break_cnt++;
    if (uart->vapi.cur_break_cnt > UART_BREAK_COUNT * uart->vapi.char_clks) {
      if (!uart->istat.break_set) {
        unsigned lsr;
        uart->istat.break_set = 1;
        lsr = UART_LSR_BREAK | UART_LSR_RXERR | UART_LSR_RDRDY;
        PRINTF ("[%x]\n", uart->regs.lsr);
        uart->istat.rxser_full = 0;
        uart->istat.rxser_clks = 0;
        uart_add_char (uart, lsr << 8);
      } else
        uart->vapi.cur_break_cnt = 0;
    }
    if (uart->istat.rxser_full) {
      uart->istat.rxser_full = 0;
      uart->istat.rxser_clks = 0;
    }
  } else {
    if (uart->istat.rxser_full) {
      if (uart->char_clks <= uart->istat.rxser_clks++) {
        /* Set unused character bits to zero and allow lsr register in fifo */
        uart->iregs.rxser &= ((1 << ((uart->regs.lcr & 3) + 5)) - 1) | 0xff00;
        debug(4, "Receiving 0x%02lx'%c' via UART (at %"PRIxADDR"...\n",
              uart->iregs.rxser, (char)uart->iregs.rxser, uart->baseaddr);
        PRINTF ("%c", (char)uart->iregs.rxser);
        uart->istat.rxser_full = 0;
        uart->istat.rxser_clks = 0;
        uart_add_char (uart, uart->iregs.rxser);
      }
    }
  }
 
  /* Check if there is something waiting, and put it into rxser */
  if (uart->regs.mcr & UART_MCR_LOOP) {
    uart->iregs.rxser = uart->iregs.loopback;
    uart->istat.rxser_full = 1;
  } else {
    if (!uart->vapi_id) {
      if(uart->istat.rxser_full == 0) {
        if (uart->slowdown)
          uart->slowdown--;
        else {
          char buffer[1];
          retval = channel_read(uart->channel, buffer, 1);
          if(retval < 0)
                  perror(uart->channel_str);
          else if(retval > 0) {
            uart->iregs.rxser = (unsigned char)buffer[0];
            uart->istat.rxser_full = 1;
          } else
            uart->slowdown = UART_FGETC_SLOWDOWN;
        }
      }
    } else { /* VAPI */
      int received = 0;
      /* do not handle commands while receiving */
      if (uart->istat.rxser_full) return;
      while (!received) {
        if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {
          unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];
          debug(4, "Handling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,
                uart->vapi_buf_tail_ptr);
          uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;
          switch (data >> 24) {
            case 0x00:
              uart->vapi.lcr = (data >> 8) & 0xff;
              /* Put data into rx fifo */
              uart->iregs.rxser = data & 0xff;
              uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);
              if ((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)
               || uart->vapi.char_clks != uart->char_clks
               || uart->vapi.skew < -MAX_SKEW || uart->vapi.skew > MAX_SKEW) {
                debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",
                      uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);
                /* Set error bits */
                uart->iregs.rxser |= (UART_LSR_FRAME | UART_LSR_RXERR) << 8;
                if (uart->regs.lcr & UART_LCR_PARITY) uart->iregs.rxser |= UART_LSR_PARITY << 8;
              }
              uart->istat.rxser_full = 1;
              received = 1;
              break;
            case 0x01:
              uart->vapi.dll = (data >> 0) & 0xff;
              uart->vapi.dlh = (data >> 8) & 0xff;
              break;
            case 0x02:
              uart->vapi.lcr = (data >> 8) & 0xff;
              break;
            case 0x03:
              uart->vapi.skew = (signed short)(data & 0xffff);
              break;
            case 0x04:
              uart->vapi.next_break_cnt = data & 0xffff;
              uart->vapi.next_break = (data >> 16) & 1;
              break;
            default:
              debug (0, "WARNING: Invalid vapi command %02lx\n", data >> 24);
              break;
          }
        } else break;
      }
    }
  }
 
  /***************** Loopback *****************/
  if (uart->regs.mcr & UART_MCR_LOOP) {
    debug(5, "uart_clock: Loopback\n");
    if ((uart->regs.mcr & UART_MCR_AUX2) !=
        ((uart->regs.msr & UART_MSR_DCD) >> 4))
      uart->regs.msr |= UART_MSR_DDCD;
    if ((uart->regs.mcr & UART_MCR_AUX1) <
        ((uart->regs.msr & UART_MSR_RI) >> 4))
      uart->regs.msr |= UART_MSR_TERI;
    if ((uart->regs.mcr & UART_MCR_RTS) !=
        ((uart->regs.msr & UART_MSR_CTS) >> 3))
      uart->regs.msr |= UART_MSR_DCTS;
    if ((uart->regs.mcr & UART_MCR_DTR) !=
        ((uart->regs.msr & UART_MSR_DSR) >> 5))
      uart->regs.msr |= UART_MSR_DDSR;
    uart->regs.msr &= ~(UART_MSR_DCD | UART_MSR_RI
              | UART_MSR_DSR | UART_MSR_CTS);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);
    uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);
  }
 
  if (uart->regs.lsr & UART_LSR_RDRDY)
    uart->istat.timeout_count++;
 
  /* Update LSR error bits from the ones from rx FIFO */
  if (uart->istat.rxbuf_full) {
    uart->regs.lsr |= uart->regs.rxbuf[uart->istat.rxbuf_tail] >> 8;
    /* we must delete the lsr status, so that we can clear it from lsr */
    uart->regs.rxbuf[uart->istat.rxbuf_tail] &= 0xff;
  }
 
  /* Interrupt detection in proper priority order. */
  uart->regs.iir = UART_IIR_NO_INT;
  if (uart->regs.ier & UART_IER_RLSI &&                    /* Receiver LS */
      uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY
        | UART_LSR_FRAME | UART_LSR_BREAK)) {
    uart->regs.iir = UART_IIR_RLSI;
  } else if ((uart->regs.ier & UART_IER_RDI)               /* RD available */
      && (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER(uart->regs.fcr >> 6))
      && (uart->regs.lsr & UART_LSR_RDRDY)) {
    uart->regs.iir = UART_IIR_RDI;
  } else if ((uart->regs.ier & UART_IER_RDI)               /* timeout */
      && (uart->istat.timeout_count >= UART_CHAR_TIMEOUT * uart->char_clks)
      && (uart->istat.rxbuf_head != uart->istat.rxbuf_tail)) {
    uart->regs.iir = UART_IIR_CTI;
  } else if (uart->regs.ier & UART_IER_THRI &&             /* Transm. empty */
      uart->istat.thre_int == 1) {
    uart->regs.iir = UART_IIR_THRI;
  } else if (uart->regs.ier & UART_IER_MSI &&              /* Modem status */
      uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR
        | UART_MSR_TERI | UART_MSR_DDCD)) {
    uart->regs.iir = UART_IIR_MSI;
  }
  if (!(uart->regs.iir & UART_IIR_NO_INT)) {
    debug (4, "uart->regs.iir = %i\t", uart->regs.iir);
    report_interrupt(uart->irq);
  }
}
 
/* Reset.  It initializes all registers of all UART devices to zero values,
   (re)opens all RX/TX file streams and places devices in memory address
   space.  */
void uart_reset(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if (uart->channel_str && uart->channel_str[0]) { /* Try to create stream. */
    if(uart->channel)
      channel_close(uart->channel);
    else
      uart->channel = channel_init(uart->channel_str);
    if(channel_open(uart->channel) < 0) {
      debug (0, "WARNING: UART has problems with channel \"%s\".\n", uart->channel_str);
    } else if (config.sim.verbose)
      PRINTF("UART at 0x%"PRIxADDR" uses ", uart->baseaddr);
  } else {
    debug (0, "WARNING: UART at %"PRIxADDR" has no vapi nor channel specified\n", uart->baseaddr);
  }
 
  if (uart->uart16550)
    uart->fifo_len = 16;
  else
    uart->fifo_len = 1;
 
  uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;
  uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;
 
  uart->istat.txser_full = uart->istat.rxser_full = 0;
  uart->istat.txbuf_full = uart->istat.rxbuf_full = 0;
 
  uart->istat.txser_clks = uart->istat.rxser_clks = 0;
 
  uart->istat.thre_int = 0;
  uart->istat.break_set = 0;
  uart->istat.timeout_count = 0;
 
  // For FIFO-mode only, THRE interrupt is set when both THR and FIFO are empty
  uart->istat.thre_int = (uart->fifo_len == 16);
 
  uart->char_clks = 0;
  uart->slowdown = UART_FGETC_SLOWDOWN;
 
  uart->iregs.txser = 0;
  uart->iregs.rxser = 0;
  uart->iregs.loopback = 0;
 
  memset(uart->regs.txbuf, 0, sizeof(uart->regs.txbuf));
  memset(uart->regs.rxbuf, 0, sizeof(uart->regs.rxbuf));
 
  uart->regs.lcr = UART_LCR_RESET;
  uart->regs.dll = 0;
  uart->regs.dlh = 0;
  uart->regs.ier = 0;
  uart->regs.iir = 0;
  uart->regs.fcr = 0;
  uart->regs.lcr = UART_LCR_RESET;
  uart->regs.mcr = 0;
  uart->regs.lsr = 0;
  uart->regs.msr = 0;
  uart->regs.scr = 0;
 
  uart->vapi.cur_break = uart->vapi.cur_break_cnt = uart->vapi.next_break = 0;
  uart->vapi.next_break_cnt = -1;
  uart->vapi.break_sent = 0;
  uart->vapi.skew = 0;
  uart->vapi.lcr = 0;
  uart->vapi.dll = 0;
  uart->vapi.char_clks = 0;
 
  uart->vapi_buf_head_ptr = 0;
  uart->vapi_buf_tail_ptr = 0;
  memset(uart->vapi_buf, 0, sizeof(uart->vapi_buf));
 
  SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);
}
 
/* Print register values on stdout. */
void uart_status(void *dat)
{
  struct dev_16450 *uart = dat;
  int i;
 
  PRINTF("\nUART visible registers at 0x%"PRIxADDR":\n", uart->baseaddr);
  PRINTF("RXBUF: ");
  for (i = uart->istat.rxbuf_head; i != uart->istat.rxbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.rxbuf[i]);
  PRINTF("TXBUF: ");
  for (i = uart->istat.txbuf_head; i != uart->istat.txbuf_tail; i = (i + 1) % uart->fifo_len)
    PRINTF (" %.2x", uart->regs.txbuf[i]);
  PRINTF("\n");
  PRINTF("DLL  : %.2x  DLH  : %.2x\n", uart->regs.dll, uart->regs.dlh);
  PRINTF("IER  : %.2x  IIR  : %.2x\n", uart->regs.ier, uart->regs.iir);
  PRINTF("LCR  : %.2x  MCR  : %.2x\n", uart->regs.lcr, uart->regs.mcr);
  PRINTF("LSR  : %.2x  MSR  : %.2x\n", uart->regs.lsr, uart->regs.msr);
  PRINTF("SCR  : %.2x\n", uart->regs.scr);
 
  PRINTF("\nInternal registers (sim debug):\n");
  PRINTF("RXSER: %.2lx  TXSER: %.2lx\n", uart->iregs.rxser, uart->iregs.txser);
 
  PRINTF("\nInternal status (sim debug):\n");
  PRINTF("char_clks: %ld\n", uart->char_clks);
  PRINTF("rxser_clks: %ld  txser_clks: %ld\n", uart->istat.rxser_clks,
         uart->istat.txser_clks);
  PRINTF("rxser: %d  txser: %d\n", uart->istat.rxser_full, uart->istat.txser_full);
  PRINTF("rxbuf_full: %d  txbuf_full: %d\n", uart->istat.rxbuf_full, uart->istat.txbuf_full);
  PRINTF("Using IRQ%i\n", uart->irq);
  if (uart->vapi_id)
    PRINTF ("Connected to vapi ID=%lx\n\n", uart->vapi_id);
  /* TODO: replace by a channel_status
  else
    PRINTF("RX fs: %p  TX fs: %p\n\n", uart->rxfs, uart->txfs);
  */
}
 
/*---------------------------------------------------[ UART configuration ]---*/
void uart_baseaddr(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->baseaddr = val.addr_val;
}
 
void uart_jitter(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->jitter = val.int_val;
}
 
void uart_irq(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->irq = val.int_val;
}
 
void uart_16550(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->uart16550 = val.int_val;
}
 
void uart_channel(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  if(!(uart->channel_str = strdup(val.str_val))) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
}
 
void uart_newway(union param_val val, void *dat)
{
  CONFIG_ERROR(" txfile and rxfile and now obsolete.\n\tUse 'channel = \"file:rxfile,txfile\"' instead.");
  exit(1);
}
 
void uart_vapi_id(union param_val val, void *dat)
{
  struct dev_16450 *uart = dat;
  uart->vapi_id = val.int_val;
}
 
void *uart_sec_start(void)
{
  struct dev_16450 *new = malloc(sizeof(struct dev_16450));
 
  if(!new) {
    fprintf(stderr, "Peripheral 16450: Run out of memory\n");
    exit(-1);
  }
 
  new->channel_str = NULL;
  new->channel = NULL;
  new->vapi_id = 0;
 
  return new;
}
 
void uart_sec_end(void *dat)
{
  struct dev_16450 *uart = dat;
 
  if(uart->vapi_id)
    vapi_install_handler(uart->vapi_id, uart_vapi_read, dat);
  register_memoryarea(uart->baseaddr, UART_ADDR_SPACE, 1, 0, uart_read_byte,
                      uart_write_byte, dat);
  reg_sim_reset(uart_reset, dat);
  reg_sim_stat(uart_status, dat);
}
 
void reg_uart_sec(void)
{
  struct config_section *sec = reg_config_sec("uart", uart_sec_start,
                                              uart_sec_end);
 
  reg_config_param(sec, "baseaddr", paramt_addr, uart_baseaddr);
  reg_config_param(sec, "irq", paramt_int, uart_irq);
  reg_config_param(sec, "16550", paramt_int, uart_16550);
  reg_config_param(sec, "jitter", paramt_int, uart_jitter);
  reg_config_param(sec, "channel", paramt_str, uart_channel);
  reg_config_param(sec, "txfile", paramt_str, uart_newway);
  reg_config_param(sec, "rxfile", paramt_str, uart_newway);
  reg_config_param(sec, "vapi_id", paramt_int, uart_vapi_id);
}

Line No.	Rev	Author	Line
1	31	lampret	`/* 16450.c -- Simulation of 8250/16450 serial UART`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* This is functional simulation of 8250/16450 UARTs. Since we RX/TX data`
21			`via file streams, we can't simulate modem control lines coming from the`
22			`DCE and similar details of communication with the DCE.`
23
24			`This simulated UART device is intended for basic UART device driver`
25			`verification. From device driver perspective this device looks like a`
26			`regular UART but never reports and modem control lines changes (the`
27			`only DCE responses are incoming characters from the file stream).`
28			`*/`
29
30			`#include <stdlib.h>`
31			`#include <stdio.h>`
32			`#include <string.h>`
33
34	1350	nogj	`#include "config.h"`
35
36			`#ifdef HAVE_INTTYPES_H`
37			`#include <inttypes.h>`
38			`#endif`
39
40			`#include "port.h"`
41			`#include "arch.h"`
42	235	erez	`#include "abstract.h"`
43	31	lampret	`#include "16450.h"`
44			`#include "sim-config.h"`
45	102	lampret	`#include "pic.h"`
46	336	markom	`#include "vapi.h"`
47	805	markom	`#include "sched.h"`
48	1073	rprescott	`#include "channel.h"`
49	1308	phoenix	`#include "debug.h"`
50	31	lampret
51	409	markom	`#define MIN(a,b) ((a) < (b) ? (a) : (b))`
52
53	31	lampret	`/* Number of clock cycles (one clock cycle is one call to the uart_clock())`
54			`before a single character is transmitted or received. */`
55	355	markom	`static unsigned long char_clks(int dll, int dlh, int lcr)`
56	31	lampret	`{`
57	409	markom	`float bauds_per_char = 1.;`
58	806	markom	`unsigned long char_clks = ((dlh << 8) + dll);`
59	355	markom
60			`if (lcr & UART_LCR_PARITY)`
61			`bauds_per_char = bauds_per_char + 1.;`
62	31	lampret
63	355	markom	`/* stop bits 1 or two */`
64			`if (lcr & UART_LCR_STOP)`
65			`bauds_per_char = bauds_per_char + 2.;`
66			`else`
67			`if ((lcr & 0x3) != 0)`
68			`bauds_per_char = bauds_per_char + 1.;`
69			`else`
70			`bauds_per_char = bauds_per_char + 1.5;`
71
72			`bauds_per_char = bauds_per_char + (5. + (lcr & 0x3));`
73
74			`return char_clks * bauds_per_char;`
75	31	lampret	`}`
76
77			`/* Set a specific UART register with value. */`
78	1359	nogj	`void uart_write_byte(oraddr_t addr, uint32_t value, void *dat)`
79	31	lampret	`{`
80	1367	nogj	`struct dev_16450 *uart = dat;`
81	355	markom
82	1350	nogj	`debug(4, "uart_write_byte(%"PRIxADDR",%02"PRIx32")\n", addr, value);`
83	341	markom
84	1367	nogj	`if (uart->regs.lcr & UART_LCR_DLAB) {`
85	355	markom	`switch (addr % UART_ADDR_SPACE) {`
86			`case UART_DLL:`
87	1367	nogj	`uart->regs.dll = value;`
88			`uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);`
89	355	markom	`return;`
90			`case UART_DLH:`
91	1367	nogj	`uart->regs.dlh = value;`
92	355	markom	`return;`
93			`}`
94			`}`
95
96			`switch (addr % UART_ADDR_SPACE) {`
97			`case UART_TXBUF:`
98	1367	nogj	`if (uart->istat.txbuf_full < uart->fifo_len) {`
99			`uart->istat.txbuf_full++;`
100			`uart->regs.txbuf[uart->istat.txbuf_head] = value;`
101			`uart->istat.txbuf_head = (uart->istat.txbuf_head + 1) % uart->fifo_len;`
102	355	markom	`} else`
103	1367	nogj	`uart->regs.txbuf[uart->istat.txbuf_head] = value;`
104	341	markom
105	1367	nogj	`uart->regs.lsr &= ~(UART_LSR_TXSERE \| UART_LSR_TXBUFE);`
106			`if (uart->regs.iir & UART_IIR_THRI)`
107			`uart->istat.thre_int = 0;`
108	355	markom	`break;`
109	409	markom	`case UART_FCR:`
110	1367	nogj	`uart->regs.fcr = value & UART_VALID_FCR;`
111			`if ((uart->fifo_len == 1 && (value & UART_FCR_FIE))`
112			`\|\| (uart->fifo_len != 1 && !(value & UART_FCR_FIE)))`
113	409	markom	`value \|= UART_FCR_RRXFI \| UART_FCR_RTXFI;`
114	1367	nogj	`uart->fifo_len = (value & UART_FCR_FIE) ? 16 : 1;`
115	409	markom	`if (value & UART_FCR_RTXFI) {`
116	1367	nogj	`uart->istat.txbuf_head = uart->istat.txbuf_tail = 0;`
117			`uart->istat.txbuf_full = 0;`
118			`uart->regs.lsr \|= UART_LSR_TXBUFE;`
119	1145	sfurman
120			`// For FIFO-mode only, THRE interrupt is set when THR and FIFO are empty`
121	1367	nogj	`uart->istat.thre_int = (uart->fifo_len == 16);`
122	409	markom	`}`
123			`if (value & UART_FCR_RRXFI) {`
124	1367	nogj	`uart->istat.rxbuf_head = uart->istat.rxbuf_tail = 0;`
125			`uart->istat.rxbuf_full = 0;`
126			`uart->regs.lsr &= ~UART_LSR_RDRDY;`
127	409	markom	`}`
128			`break;`
129	355	markom	`case UART_IER:`
130	1367	nogj	`uart->regs.ier = value & UART_VALID_IER;`
131	355	markom	`break;`
132			`case UART_LCR:`
133	1367	nogj	`uart->regs.lcr = value & UART_VALID_LCR;`
134			`uart->char_clks = char_clks(uart->regs.dll, uart->regs.dlh, uart->regs.lcr);`
135	355	markom	`break;`
136			`case UART_MCR:`
137	1367	nogj	`uart->regs.mcr = value & UART_VALID_MCR;`
138	355	markom	`break;`
139			`case UART_SCR:`
140	1367	nogj	`uart->regs.scr = value;`
141	355	markom	`break;`
142			`default:`
143			`debug(1, "write out of range (addr %x)\n", addr);`
144			`}`
145	31	lampret	`}`
146
147			`/* Read a specific UART register. */`
148	1359	nogj	`uint32_t uart_read_byte(oraddr_t addr, void *dat)`
149	31	lampret	`{`
150	1367	nogj	`struct dev_16450 *uart = dat;`
151	1350	nogj	`uint8_t value = 0;`
152	355	markom
153	1350	nogj	`debug(4, "uart_read_byte(%"PRIxADDR")", addr);`
154	355	markom
155	1367	nogj	`if (uart->regs.lcr & UART_LCR_DLAB) {`
156	355	markom	`switch (addr % UART_ADDR_SPACE) {`
157			`case UART_DLL:`
158	1367	nogj	`value = uart->regs.dll;`
159	1350	nogj	`debug(4, "= %"PRIx8"\n", value);`
160	355	markom	`return value;`
161			`case UART_DLH:`
162	1367	nogj	`value = uart->regs.dlh;`
163	1350	nogj	`debug(4, "= %"PRIx8"\n", value);`
164	355	markom	`return value;`
165			`}`
166			`}`
167
168			`switch (addr % UART_ADDR_SPACE) {`
169			`case UART_RXBUF:`
170	409	markom	`{ /* Print out FIFO for debugging */`
171			`int i;`
172	1367	nogj	`debug(4, "(%i/%i,%i,%i:", uart->istat.rxbuf_full, uart->fifo_len,`
173			`uart->istat.rxbuf_head, uart->istat.rxbuf_tail);`
174			`for (i = 0; i < uart->istat.rxbuf_full; i++)`
175			`debug(4, "%02x ", uart->regs.rxbuf[(uart->istat.rxbuf_tail + i) % uart->fifo_len]);`
176	409	markom	`debug(4, ")");`
177			`}`
178	1367	nogj	`if (uart->istat.rxbuf_full) {`
179			`value = uart->regs.rxbuf[uart->istat.rxbuf_tail];`
180			`uart->istat.rxbuf_tail = (uart->istat.rxbuf_tail + 1) % uart->fifo_len;`
181			`uart->istat.rxbuf_full--;`
182	355	markom	`}`
183
184	1367	nogj	`if (uart->istat.rxbuf_full)`
185			`uart->regs.lsr \|= UART_LSR_RDRDY;`
186	355	markom	`else`
187	1367	nogj	`uart->regs.lsr &= ~UART_LSR_RDRDY;`
188	409	markom
189	1367	nogj	`uart->istat.timeout_count = 0;`
190	355	markom	`break;`
191			`case UART_IER:`
192	1367	nogj	`value = uart->regs.ier & UART_VALID_IER;`
193	355	markom	`break;`
194			`case UART_IIR:`
195	1367	nogj	`value = (uart->regs.iir & UART_VALID_IIR) \| 0xc0;`
196			`if (uart->regs.iir & UART_IIR_THRI)`
197			`uart->istat.thre_int = 0;`
198	355	markom	`break;`
199			`case UART_LCR:`
200	1367	nogj	`value = uart->regs.lcr & UART_VALID_LCR;`
201	355	markom	`break;`
202			`case UART_MCR:`
203			`value = 0;`
204			`break;`
205			`case UART_LSR:`
206	1367	nogj	`value = uart->regs.lsr & UART_VALID_LSR;`
207			`uart->regs.lsr &=`
208	409	markom	`~(UART_LSR_OVRRUN \| UART_LSR_BREAK \| UART_LSR_PARITY`
209			`\| UART_LSR_FRAME \| UART_LSR_RXERR);`
210	355	markom	`break;`
211			`case UART_MSR:`
212	1367	nogj	`value = uart->regs.msr & UART_VALID_MSR;`
213			`uart->regs.msr = 0;`
214	355	markom	`break;`
215			`case UART_SCR:`
216	1367	nogj	`value = uart->regs.scr;`
217	355	markom	`break;`
218			`default:`
219	1350	nogj	`debug(1, "read out of range (addr %"PRIxADDR")\n", addr);`
220	355	markom	`}`
221	1350	nogj	`debug(4, " = %"PRIx8"\n", value);`
222	355	markom	`return value;`
223	31	lampret	`}`
224
225	336	markom	`/* Function that handles incoming VAPI data. */`
226	1366	nogj	`void uart_vapi_read (unsigned long id, unsigned long data, void *dat)`
227	336	markom	`{`
228	1367	nogj	`struct dev_16450 *uart = dat;`
229	1350	nogj	`debug(4, "UART: id %08lx, data %08lx\n", id, data);`
230	1367	nogj	`uart->vapi_buf[uart->vapi_buf_head_ptr] = data;`
231			`uart->vapi_buf_head_ptr = (uart->vapi_buf_head_ptr + 1) % UART_VAPI_BUF_LEN;`
232			`if (uart->vapi_buf_tail_ptr == uart->vapi_buf_head_ptr) {`
233	341	markom	`fprintf (stderr, "FATAL: uart VAPI buffer to small.\n");`
234			`exit (1);`
235			`}`
236			`}`
237	336	markom
238	1367	nogj	`static void send_char (struct dev_16450 *uart, int bits_send)`
239	409	markom	`{`
240	1367	nogj	`PRINTF ("%c", (char)uart->iregs.txser);`
241			`debug(4, "TX \'%c\' via UART at %"PRIxADDR"...\n", (char)uart->iregs.txser,`
242			`uart->baseaddr);`
243			`if (uart->regs.mcr & UART_MCR_LOOP)`
244			`uart->iregs.loopback = uart->iregs.txser;`
245	409	markom	`else {`
246			`/* Send to either VAPI or to file */`
247	1367	nogj	`if (uart->vapi_id) {`
248	409	markom	`int par, pe, fe, nbits;`
249			`int j, data;`
250			`unsigned long packet = 0;`
251
252	1367	nogj	`nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);`
253	409	markom	`/* Encode a packet */`
254	1367	nogj	`packet = uart->iregs.txser & ((1 << nbits) - 1);`
255	409	markom
256			`/* Calculate parity */`
257			`for (j = 0, par = 0; j < nbits; j++)`
258			`par ^= (packet >> j) & 1;`
259
260	1367	nogj	`if (uart->regs.lcr & UART_LCR_PARITY) {`
261			`if (uart->regs.lcr & UART_LCR_SPAR) {`
262	409	markom	`packet \|= 1 << nbits;`
263			`} else {`
264	1367	nogj	`if (uart->regs.lcr & UART_LCR_EPAR)`
265	409	markom	`packet \|= par << nbits;`
266			`else`
267			`packet \|= (par ^ 1) << nbits;`
268			`}`
269			`nbits++;`
270			`}`
271			`packet \|= 1 << (nbits++);`
272	1367	nogj	`if (uart->regs.lcr & UART_LCR_STOP)`
273	409	markom	`packet \|= 1 << (nbits++);`
274
275			`/* Decode a packet */`
276	1367	nogj	`nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;`
277	409	markom	`data = packet & ((1 << nbits) - 1);`
278
279			`/* Calculate parity, including parity bit */`
280			`for (j = 0, par = 0; j < nbits + 1; j++)`
281			`par ^= (packet >> j) & 1;`
282
283	1367	nogj	`if (uart->vapi.lcr & UART_LCR_PARITY) {`
284			`if (uart->vapi.lcr & UART_LCR_SPAR) {`
285	409	markom	`pe = !((packet >> nbits) & 1);`
286			`} else {`
287	1367	nogj	`if (uart->vapi.lcr & UART_LCR_EPAR)`
288	409	markom	`pe = par != 0;`
289			`else`
290			`pe = par != 1;`
291			`}`
292			`nbits++;`
293			`} else`
294			`pe = 0;`
295
296			`fe = ((packet >> (nbits++)) & 1) ^ 1;`
297	1367	nogj	`if (uart->vapi.lcr & UART_LCR_STOP)`
298	409	markom	`fe \|= ((packet >> (nbits++)) & 1) ^ 1;`
299
300	1367	nogj	`debug (4, "lcr vapi %02x, uart %02x\n", uart->vapi.lcr, uart->regs.lcr);`
301			`data \|= (uart->vapi.lcr << 8) \| (pe << 16) \| (fe << 17) \| (uart->vapi.lcr << 8);`
302			`PRINTF ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);`
303			`debug (4, "vapi_send (%08lx, %08x)\n", uart->vapi_id, data);`
304			`vapi_send (uart->vapi_id, data);`
305	409	markom	`} else {`
306	1367	nogj	`char buffer[1] = { uart->iregs.txser & 0xFF };`
307			`channel_write(uart->channel, buffer, 1);`
308	409	markom	`}`
309			`}`
310	1367	nogj	`uart->istat.txser_full = 0;`
311			`uart->istat.txser_clks = 0;`
312	409	markom	`}`
313
314	411	markom	`/* Adds a character to the FIFO */`
315
316	1367	nogj	`void uart_add_char (struct dev_16450 *uart, int ch)`
317	411	markom	`{`
318	1367	nogj	`if (uart->istat.rxbuf_full + 1 > uart->fifo_len)`
319			`uart->regs.lsr \|= UART_LSR_OVRRUN \| UART_LSR_RXERR;`
320	411	markom	`else {`
321			`debug(4, "add %02x\n", ch);`
322	1367	nogj	`uart->regs.rxbuf[uart->istat.rxbuf_head] = ch;`
323			`uart->istat.rxbuf_head = (uart->istat.rxbuf_head + 1) % uart->fifo_len;`
324			`uart->istat.rxbuf_full++;`
325	411	markom	`}`
326	1367	nogj	`uart->regs.lsr \|= UART_LSR_RDRDY;`
327			`uart->istat.timeout_count = 0;`
328	411	markom	`}`
329
330	806	markom	`/* Simulation hook. Must be called every clock cycle to simulate all UART`
331			`devices. It does internal functional UART simulation. */`
332	1367	nogj	`void uart_clock16 (void *dat)`
333	806	markom	`{`
334	1367	nogj	`struct dev_16450 *uart = dat;`
335	806	markom	`int retval;`
336	1073	rprescott
337	821	markom	`/* Schedule for later */`
338	1390	nogj	`SCHED_ADD (uart_clock16, dat, UART_CLOCK_DIVIDER);`
339	821	markom
340	806	markom	`/* If VAPI is not selected, UART communicates with two file streams;`
341			`if VAPI is selected, we use VAPI streams. */`
342			`/* if txfs is corrupted, skip this uart. */`
343	1367	nogj	`if (!uart->vapi_id && !channel_ok(uart->channel)) return;`
344	806	markom
345	1367	nogj	`if (uart->vapi.next_break_cnt >= 0)`
346			`if (--uart->vapi.next_break_cnt < 0) {`
347			`if (!(uart->vapi.cur_break = uart->vapi.next_break))`
348			`uart->istat.break_set = 0;`
349	806	markom	`}`
350	821	markom
351	806	markom	`/*************** Transmit ***************/`
352	1367	nogj	`if (!uart->istat.txser_full) {`
353			`// uart->regs.lsr \|= UART_LSR_TXBUFE;`
354			`if (uart->istat.txbuf_full) {`
355			`uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];`
356			`uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;`
357			`uart->istat.txser_full = 1;`
358			`uart->istat.txbuf_full--;`
359			`uart->regs.lsr &= ~UART_LSR_TXSERE;`
360	1143	sfurman
361			`// When UART is in either character mode, i.e. 16450 emulation mode, or FIFO mode,`
362			`// the THRE interrupt is raised when THR transitions from full to empty.`
363	1367	nogj	`if (!uart->istat.txbuf_full) {`
364			`uart->istat.thre_int = 1;`
365			`uart->regs.lsr \|= UART_LSR_TXBUFE;`
366	1143	sfurman	`}`
367	806	markom	`} else {`
368	1367	nogj	`uart->regs.lsr \|= UART_LSR_TXSERE;`
369	806	markom	`}`
370	1367	nogj	`} else if (uart->char_clks <= uart->istat.txser_clks++) {`
371			`send_char(uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5); /* We've sent all bits */`
372	806	markom	`} else {`
373			`/* We are still sending char here*/`
374
375			`/* Check if we set the break bit */`
376	1367	nogj	`if (uart->regs.lcr & UART_LCR_SBC) {`
377			`if (!uart->vapi.break_sent) {`
378	806	markom	`#if 0`
379			`/* Send broken frame */`
380	1367	nogj	`int nbits_sent = ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks - 1) / uart->char_clks;`
381	806	markom	`send_char(i, nbits_sent);`
382			`#endif`
383			`/* Send one break signal */`
384	1367	nogj	`vapi_send (uart->vapi_id, UART_LCR_SBC << 8);`
385			`uart->vapi.break_sent = 1;`
386	806	markom	`}`
387			`/* mark as character was sent */`
388	1367	nogj	`uart->istat.txser_full = 0;`
389			`uart->istat.txser_clks = 0;`
390	806	markom	`} else`
391	1367	nogj	`uart->vapi.break_sent = 0;`
392	1143	sfurman
393	806	markom	`}`
394	1143	sfurman
395	806	markom	`/*************** Receive ***************/`
396
397			`/* Is there a break? */`
398	1367	nogj	`if (uart->vapi.cur_break) {`
399			`uart->vapi.cur_break_cnt++;`
400			`if (uart->vapi.cur_break_cnt > UART_BREAK_COUNT * uart->vapi.char_clks) {`
401			`if (!uart->istat.break_set) {`
402	806	markom	`unsigned lsr;`
403	1367	nogj	`uart->istat.break_set = 1;`
404	806	markom	`lsr = UART_LSR_BREAK \| UART_LSR_RXERR \| UART_LSR_RDRDY;`
405	1367	nogj	`PRINTF ("[%x]\n", uart->regs.lsr);`
406			`uart->istat.rxser_full = 0;`
407			`uart->istat.rxser_clks = 0;`
408			`uart_add_char (uart, lsr << 8);`
409	806	markom	`} else`
410	1367	nogj	`uart->vapi.cur_break_cnt = 0;`
411	806	markom	`}`
412	1367	nogj	`if (uart->istat.rxser_full) {`
413			`uart->istat.rxser_full = 0;`
414			`uart->istat.rxser_clks = 0;`
415	806	markom	`}`
416			`} else {`
417	1367	nogj	`if (uart->istat.rxser_full) {`
418			`if (uart->char_clks <= uart->istat.rxser_clks++) {`
419	806	markom	`/* Set unused character bits to zero and allow lsr register in fifo */`
420	1367	nogj	`uart->iregs.rxser &= ((1 << ((uart->regs.lcr & 3) + 5)) - 1) \| 0xff00;`
421			`debug(4, "Receiving 0x%02lx'%c' via UART (at %"PRIxADDR"...\n",`
422			`uart->iregs.rxser, (char)uart->iregs.rxser, uart->baseaddr);`
423			`PRINTF ("%c", (char)uart->iregs.rxser);`
424			`uart->istat.rxser_full = 0;`
425			`uart->istat.rxser_clks = 0;`
426			`uart_add_char (uart, uart->iregs.rxser);`
427	806	markom	`}`
428			`}`
429			`}`
430
431			`/* Check if there is something waiting, and put it into rxser */`
432	1367	nogj	`if (uart->regs.mcr & UART_MCR_LOOP) {`
433			`uart->iregs.rxser = uart->iregs.loopback;`
434			`uart->istat.rxser_full = 1;`
435	806	markom	`} else {`
436	1367	nogj	`if (!uart->vapi_id) {`
437			`if(uart->istat.rxser_full == 0) {`
438			`if (uart->slowdown)`
439			`uart->slowdown--;`
440	1073	rprescott	`else {`
441			`char buffer[1];`
442	1367	nogj	`retval = channel_read(uart->channel, buffer, 1);`
443	1073	rprescott	`if(retval < 0)`
444	1367	nogj	`perror(uart->channel_str);`
445	1073	rprescott	`else if(retval > 0) {`
446	1367	nogj	`uart->iregs.rxser = (unsigned char)buffer[0];`
447			`uart->istat.rxser_full = 1;`
448	1073	rprescott	`} else`
449	1367	nogj	`uart->slowdown = UART_FGETC_SLOWDOWN;`
450	1073	rprescott	`}`
451	806	markom	`}`
452			`} else { /* VAPI */`
453			`int received = 0;`
454			`/* do not handle commands while receiving */`
455	1367	nogj	`if (uart->istat.rxser_full) return;`
456	806	markom	`while (!received) {`
457	1367	nogj	`if (uart->vapi_buf_head_ptr != uart->vapi_buf_tail_ptr) {`
458			`unsigned long data = uart->vapi_buf[uart->vapi_buf_tail_ptr];`
459			`debug(4, "Handling: %08lx (%i,%i)\n", data, uart->vapi_buf_head_ptr,`
460			`uart->vapi_buf_tail_ptr);`
461			`uart->vapi_buf_tail_ptr = (uart->vapi_buf_tail_ptr + 1) % UART_VAPI_BUF_LEN;`
462	806	markom	`switch (data >> 24) {`
463			`case 0x00:`
464	1367	nogj	`uart->vapi.lcr = (data >> 8) & 0xff;`
465	806	markom	`/* Put data into rx fifo */`
466	1367	nogj	`uart->iregs.rxser = data & 0xff;`
467			`uart->vapi.char_clks = char_clks (uart->vapi.dll, uart->vapi.dlh, uart->vapi.lcr);`
468			`if ((uart->vapi.lcr & ~UART_LCR_SBC) != (uart->regs.lcr & ~UART_LCR_SBC)`
469			`\|\| uart->vapi.char_clks != uart->char_clks`
470			`\|\| uart->vapi.skew < -MAX_SKEW \|\| uart->vapi.skew > MAX_SKEW) {`
471	806	markom	`debug (3, "WARNING: unmatched VAPI (%02x) and uart (%02x) modes.\n",`
472	1367	nogj	`uart->vapi.lcr & ~UART_LCR_SBC, uart->regs.lcr & ~UART_LCR_SBC);`
473	806	markom	`/* Set error bits */`
474	1367	nogj	`uart->iregs.rxser \|= (UART_LSR_FRAME \| UART_LSR_RXERR) << 8;`
475			`if (uart->regs.lcr & UART_LCR_PARITY) uart->iregs.rxser \|= UART_LSR_PARITY << 8;`
476	806	markom	`}`
477	1367	nogj	`uart->istat.rxser_full = 1;`
478	806	markom	`received = 1;`
479			`break;`
480			`case 0x01:`
481	1367	nogj	`uart->vapi.dll = (data >> 0) & 0xff;`
482			`uart->vapi.dlh = (data >> 8) & 0xff;`
483	806	markom	`break;`
484			`case 0x02:`
485	1367	nogj	`uart->vapi.lcr = (data >> 8) & 0xff;`
486	806	markom	`break;`
487			`case 0x03:`
488	1367	nogj	`uart->vapi.skew = (signed short)(data & 0xffff);`
489	806	markom	`break;`
490			`case 0x04:`
491	1367	nogj	`uart->vapi.next_break_cnt = data & 0xffff;`
492			`uart->vapi.next_break = (data >> 16) & 1;`
493	806	markom	`break;`
494			`default:`
495	1350	nogj	`debug (0, "WARNING: Invalid vapi command %02lx\n", data >> 24);`
496	806	markom	`break;`
497			`}`
498			`} else break;`
499			`}`
500			`}`

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