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[/] [or1k/] [tags/] [nog_patch_39/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1354

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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "sim-config.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "labels.h"
#include "execute.h"
#include "sprs.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern uorreg_t reg[];
extern char *disassembled;
 
/* This is an abstract+physical memory array rather than only physical
   memory array */
static uint32_t *simmem32;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t),
                         void (writefunc)(oraddr_t, uint32_t))
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case in overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t),
                         void (writefunc)(oraddr_t, uint32_t))
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  IFF (config.mc.enabled) {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
        return cur_area = ptmp;
  } else {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))
        return cur_area = ptmp;
  }
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr) << 24;
      temp |= cur_area->readfunc(memaddr + 1) << 16;
      temp |= cur_area->readfunc(memaddr + 2) << 8;
      temp |= cur_area->readfunc(memaddr + 3);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr) << 16;
      temp |= cur_area->readfunc(memaddr + 2);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr) << 8;
      temp |= cur_area->readfunc(memaddr + 1);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  }
 
  if (!pending.valid && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
  cur_vadd = pc;
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  // We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done
  // in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned short)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF);
      cur_area->writefunc(memaddr + 1, value & 0xFF);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr) {
  return simmem32[(cur_area->misc + (addr & cur_area->size_mask)) >> 2];
}
 
void simmem_write_word(oraddr_t addr, uint32_t value) {
  simmem32[(cur_area->misc + (addr & cur_area->size_mask)) >> 2] = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  uint32_t memory_needed = 0;
 
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word);
      cur_area->misc = memory_needed;
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
      memory_needed += cur_area->size;
    }
    PRINTF ("\n");
  } else {
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word);
    cur_area->misc = memory_needed;
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
    memory_needed += cur_area->size;
  }
 
  simmem32 = (uint32_t *) malloc (sizeof (uint32_t) * ((memory_needed + 3) / 4));
  if (!simmem32) {
    fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
    exit (-1);
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	7	jrydberg	`#include "sim-config.h"`
37	6	lampret
38	1350	nogj	`#include "arch.h"`
39	2	cvs	`#include "parse.h"`
40			`#include "abstract.h"`
41	261	markom	`#include "labels.h"`
42	2	cvs	`#include "execute.h"`
43	32	lampret	`#include "sprs.h"`
44			`#include "except.h"`
45	123	markom	`#include "debug_unit.h"`
46	134	markom	`#include "opcode/or32.h"`
47	547	markom	`#include "support/profile.h"`
48	1308	phoenix	`#include "dmmu.h"`
49			`#include "dcache_model.h"`
50			`#include "icache_model.h"`
51			`#include "debug.h"`
52	1344	nogj	`#include "stats.h"`
53	2	cvs
54	1354	phoenix	`extern uorreg_t reg[];`
55	138	markom	`extern char *disassembled;`
56	2	cvs
57	28	lampret	`/* This is an abstract+physical memory array rather than only physical`
58			`memory array */`
59	1350	nogj	`static uint32_t *simmem32;`
60	2	cvs
61	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
62			`peripheral devices. */`
63			`struct dev_memarea *dev_list;`
64
65	221	markom	`/* Temporary variable to increase speed. */`
66			`struct dev_memarea *cur_area;`
67
68	970	simons	`/* Pointer to memory controller device descriptor. */`
69			`struct dev_memarea mc_area = (struct dev_memarea )0;`
70
71	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
72			`int data_ci, insn_ci;`
73
74	525	simons	`/* Virtual address of current access. */`
75	1350	nogj	`oraddr_t cur_vadd;`
76	525	simons
77	261	markom	`/* Calculates bit mask to fit the data */`
78	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
79	261	markom	`int i = 0;`
80			`data--;`
81	382	markom	`while (data >> i)`
82	261	markom	`data \|= 1 << i++;`
83			`return data;`
84			`}`
85
86			`/* Register read and write function for a memory area.`
87			`addr is inside the area, if addr & addr_mask == addr_compare`
88			`(used also by peripheral devices like 16450 UART etc.) */`
89	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
90			`uint32_t size, unsigned granularity, unsigned mc_dev,`
91			`uint32_t (readfunc)(oraddr_t),`
92			`void (writefunc)(oraddr_t, uint32_t))`
93	30	lampret	`{`
94	239	markom	`struct dev_memarea **pptmp;`
95	1350	nogj	`unsigned int size_mask = bit_mask (size);`
96	261	markom	`int found_error = 0;`
97			`addr_compare &= addr_mask;`
98	221	markom
99	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
100			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
101			`granularity);`
102	239	markom	`/* Go to the end of the list. */`
103	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
104			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
105			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
106	262	markom	`if (!found_error) {`
107	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
108	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
109			`", size %08"PRIx32", gran %iB\n",`
110	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
111			`granularity);`
112	262	markom	`}`
113	261	markom	`found_error = 1;`
114	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
115			`", size %08"PRIx32", gran %iB\n",`
116	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
117			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
118			`(pptmp)->size, (pptmp)->granularity);`
119	261	markom	`}`
120
121			`if (found_error)`
122			`exit (-1);`
123	537	markom
124	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
125	970	simons
126			`if (mc_dev)`
127			`mc_area = *pptmp;`
128
129	261	markom	`(*pptmp)->addr_mask = addr_mask;`
130			`(*pptmp)->addr_compare = addr_compare;`
131	239	markom	`(*pptmp)->size = size;`
132	261	markom	`(*pptmp)->size_mask = size_mask;`
133	239	markom	`(*pptmp)->granularity = granularity;`
134			`(*pptmp)->readfunc = readfunc;`
135			`(*pptmp)->writefunc = writefunc;`
136	479	markom	`(*pptmp)->log = 0;`
137	882	simons	`(*pptmp)->delayr = 2;`
138			`(*pptmp)->delayw = 2;`
139	239	markom	`(*pptmp)->next = NULL;`
140	261	markom	`}`
141	221	markom
142	261	markom	`/* Register read and write function for a memory area.`
143			`Memory areas should be aligned. Memory area is rounded up to`
144			`fit the nearest 2^n aligment.`
145	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
146			`If mc_dev is 1, this means that this device will be checked first for match`
147			`and will be accessed in case in overlaping memory spaces.`
148			`Only one device can have this set to 1 (used for memory controller) */`
149	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
150			`unsigned mc_dev,`
151			`uint32_t (readfunc)(oraddr_t),`
152			`void (writefunc)(oraddr_t, uint32_t))`
153	261	markom	`{`
154	1350	nogj	`unsigned int size_mask = bit_mask (size);`
155			`unsigned int addr_mask = ~size_mask;`
156	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
157	970	simons	`size_mask + 1, granularity, mc_dev,`
158	261	markom	`readfunc, writefunc);`
159	30	lampret	`}`
160
161	261	markom
162	30	lampret	`/* Check if access is to registered area of memory. */`
163	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
164	30	lampret	`{`
165	239	markom	`struct dev_memarea *ptmp;`
166	221	markom
167	970	simons	`/* Check memory controller space first */`
168			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
169			`return cur_area = mc_area;`
170
171			`/* Check cached value */`
172	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
173			`return cur_area;`
174
175			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
176			`IFF (config.mc.enabled) {`
177			`/* Check list of registered devices. */`
178			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
179			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
180			`return cur_area = ptmp;`
181			`} else {`
182			`/* Check list of registered devices. */`
183			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
184			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))`
185			`return cur_area = ptmp;`
186			`}`
187	239	markom	`return cur_area = NULL;`
188	30	lampret	`}`
189
190	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
191	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
192	882	simons	`{`
193			`if (verify_memoryarea(memaddr)) {`
194			`cur_area->delayr = delayr;`
195			`cur_area->delayw = delayw;`
196			`}`
197			`}`
198
199	1319	phoenix	`/* for cpu accesses`
200			`*`
201			`* STATISTICS: check cpu/common/parse.c`
202			`*/`
203	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
204	560	markom	`{`
205	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
206			`}`
207	560	markom
208	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
209	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
210	1319	phoenix	`{`
211			`return(evalsim_mem32_atomic(memaddr, 0));`
212			`}`
213
214	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
215	1319	phoenix	`{`
216	1350	nogj	`uint32_t temp = 0;`
217	1319	phoenix
218	560	markom	`if (verify_memoryarea(memaddr)) {`
219			`switch(cur_area->granularity) {`
220			`case 4:`
221			`temp = cur_area->readfunc(memaddr);`
222			`break;`
223			`case 1:`
224			`temp = cur_area->readfunc(memaddr) << 24;`
225			`temp \|= cur_area->readfunc(memaddr + 1) << 16;`
226			`temp \|= cur_area->readfunc(memaddr + 2) << 8;`
227			`temp \|= cur_area->readfunc(memaddr + 3);`
228			`break;`
229			`case 2:`
230			`temp = cur_area->readfunc(memaddr) << 16;`
231			`temp \|= cur_area->readfunc(memaddr + 2);`
232			`break;`
233	1319	phoenix	`default:`
234			`/* if you add new memory granularity be sure to check the formula`
235			`* below for the read delay and fix it if necessery`
236			`*/`
237			`PRINTF("unknown/unhandled memory granularuty\n");`
238			`exit(-1);`
239	560	markom	`}`
240	1319	phoenix	`if (cpu_access)`
241			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
242	560	markom	`}`
243			`return temp;`
244			`}`
245
246	1319	phoenix	`/* for cpu accesses */`
247	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
248	560	markom	`{`
249	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
250			`}`
251	560	markom
252	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
253	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
254	1319	phoenix	`{`
255			`return(evalsim_mem16_atomic(memaddr, 0));`
256			`}`
257
258	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
259	1319	phoenix	`{`
260	1350	nogj	`uint32_t temp = 0;`
261	1319	phoenix
262	560	markom	`if (verify_memoryarea(memaddr)) {`
263			`switch(cur_area->granularity) {`
264			`case 1:`
265			`temp = cur_area->readfunc(memaddr) << 8;`
266			`temp \|= cur_area->readfunc(memaddr + 1);`
267	1319	phoenix	`if (cpu_access)`
268			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
269	560	markom	`break;`
270			`case 2:`
271			`temp = cur_area->readfunc(memaddr);`
272	1319	phoenix	`if (cpu_access)`
273			`runtime.sim.mem_cycles += cur_area->delayr;`
274	560	markom	`break;`
275			`case 4:`
276	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
277	560	markom	`if (memaddr & 2)`
278			`temp &= 0xffff;`
279			`else`
280			`temp >>= 16;`
281			`break;`
282	1319	phoenix	`default:`
283			`/* if you add new memory granularity be sure to check the formula`
284			`* below for the read delay and fix it if necessery`
285			`*/`
286			`PRINTF("unknown/unhandled memory granularuty\n");`
287			`exit(-1);`
288	560	markom	`}`
289			`}`
290			`return temp;`
291			`}`
292
293	1319	phoenix	`/* for cpu accesses */`
294	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
295	560	markom	`{`
296	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
297			`}`
298	560	markom
299	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
300	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
301	1319	phoenix	`{`
302			`return(evalsim_mem8_atomic(memaddr, 0));`
303			`}`
304
305	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
306	1319	phoenix	`{`
307	1350	nogj	`uint32_t temp = 0;`
308	1319	phoenix
309	560	markom	`if (verify_memoryarea(memaddr)) {`
310			`switch(cur_area->granularity) {`
311			`case 1:`
312			`temp = cur_area->readfunc(memaddr);`
313	1319	phoenix	`if (cpu_access)`
314			`runtime.sim.mem_cycles += cur_area->delayr;`
315	560	markom	`break;`
316			`case 2:`
317	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
318	560	markom	`if (memaddr & 1)`
319			`temp &= 0xff;`
320			`else`
321			`temp >>= 8;`
322			`break;`
323			`case 4:`
324	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
325	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
326			`temp &= 0xff;`
327			`break;`
328	1319	phoenix	`default:`
329			`/* if you add new memory granularity be sure to check the formula`
330			`* below for the read delay and fix it if necessery`
331			`*/`
332			`PRINTF("unknown/unhandled memory granularuty\n");`
333			`exit(-1);`
334	560	markom	`}`
335			`}`
336			`return temp;`
337			`}`
338
339	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
340			`*`
341	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
342	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
343			`* hence the use of eval_mem32_void()`
344			`*`
345			`* STATISTICS OK.`
346			`*/`
347	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
348	349	simons	`{`
349	1350	nogj	`uint32_t temp;`
350	349	simons
351	525	simons	`cur_vadd = memaddr;`
352	550	markom	`if (config.debug.enabled)`
353	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
354	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
355	611	simons	`if (!cur_area) {`
356	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
357			`memaddr);`
358	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
359			`temp = 0;`
360			`}`
361
362	599	simons	`if (!pending.valid && cur_area->log)`
363	1350	nogj	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
364	550	markom	`if (config.debug.enabled)`
365	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
366			`return temp;`
367	537	markom	`}`
368	349	simons
369	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
370			`*`
371			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
372			`*/`
373	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
374	2	cvs	`{`
375	1350	nogj	`uint32_t temp;`
376	123	markom
377	547	markom	`if (config.sim.mprofile)`
378			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
379
380	538	markom	`if (memaddr & 3) {`
381			`except_handle (EXCEPT_ALIGN, memaddr);`
382			`return 0;`
383			`}`
384	557	markom
385	631	simons	`if (config.debug.enabled)`
386			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
387
388	574	markom	`cur_vadd = memaddr;`
389	631	simons
390			`memaddr = dmmu_translate(memaddr, 0);`
391	574	markom	`if (pending.valid)`
392			`return 0;`
393
394	992	simons	`if (config.dc.enabled)`
395			`temp = dc_simulate_read(memaddr, 4);`
396			`else {`
397			`temp = evalsim_mem32(memaddr);`
398			`if (!cur_area) {`
399	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
400			`memaddr);`
401	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
402			`temp = 0;`
403			`}`
404	611	simons	`}`
405
406	550	markom	`if (config.debug.enabled)`
407	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
408	239	markom	`return temp;`
409	66	lampret	`}`
410
411	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
412			`*`
413			`* STATISTICS OK`
414			`*/`
415	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
416			`int through_dc)`
417	1240	phoenix	`{`
418	1350	nogj	`uint32_t temp;`
419	1240	phoenix
420			`if (memaddr & 3) {`
421			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
422			`return 0;`
423			`}`
424
425			`cur_vadd = memaddr;`
426
427			`if (through_mmu)`
428			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
429
430			`if (through_dc)`
431			`temp = dc_simulate_read(memaddr, 4);`
432			`else {`
433	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
434	1240	phoenix	`if (!cur_area) {`
435	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
436			`") in eval_direct32()\n", memaddr);`
437	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
438			`temp = 0;`
439			`}`
440			`}`
441
442			`return temp;`
443			`}`
444
445
446	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
447			`*`
448			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
449			`*/`
450	1350	nogj	`uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)`
451	349	simons	`{`
452	1350	nogj	`uint32_t temp;`
453	349	simons
454	547	markom	`if (config.sim.mprofile)`
455			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
456	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
457	525	simons	`cur_vadd = pc;`
458	1244	hpanther
459			`// I think this does not belong into eval_insn() 2004-01-30 HP`
460			`// if (config.debug.enabled)`
461			`// breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
462
463			`// We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done`
464			`// in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP`
465
466	631	simons	`if (config.ic.enabled)`
467			`temp = ic_simulate_fetch(memaddr);`
468	992	simons	`else {`
469	631	simons	`temp = evalsim_mem32(memaddr);`
470	992	simons	`if (!cur_area) {`
471	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
472			`memaddr);`
473	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
474			`temp = 0;`
475			`}`
476	611	simons	`}`
477
478	1244	hpanther	`// I think this does not belong into eval_insn() 2004-01-30 HP`
479			`// if (config.debug.enabled)`
480			`// breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
481	349	simons	`return temp;`
482			`}`
483
484	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
485			`*`
486			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
487			`*/`
488	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
489	2	cvs	`{`
490	1350	nogj	`uint16_t temp;`
491	547	markom
492			`if (config.sim.mprofile)`
493			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
494
495	538	markom	`if (memaddr & 1) {`
496			`except_handle (EXCEPT_ALIGN, memaddr);`
497			`return 0;`
498			`}`
499	574	markom
500	631	simons	`if (config.debug.enabled)`

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