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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1362

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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "execute.h"
#include "sprs.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->chip_select = -1;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  IFF (config.mc.enabled) {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
        return cur_area = ptmp;
  } else {
    /* Check list of registered devices. */
    for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
      if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))
        return cur_area = ptmp;
  }
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  }
 
  if (!pending.valid && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
  cur_vadd = pc;
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  // We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done
  // in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  // I think this does not belong into eval_insn() 2004-01-30 HP
//  if (config.debug.enabled)
//    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned short)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (pending.valid)
    return 0;
 
  if (config.dc.enabled)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (pending.valid) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	2	cvs	`#include "execute.h"`
43	32	lampret	`#include "sprs.h"`
44			`#include "except.h"`
45	123	markom	`#include "debug_unit.h"`
46	134	markom	`#include "opcode/or32.h"`
47	547	markom	`#include "support/profile.h"`
48	1308	phoenix	`#include "dmmu.h"`
49			`#include "dcache_model.h"`
50			`#include "icache_model.h"`
51			`#include "debug.h"`
52	1344	nogj	`#include "stats.h"`
53	2	cvs
54	138	markom	`extern char *disassembled;`
55	2	cvs
56	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
57			`peripheral devices. */`
58			`struct dev_memarea *dev_list;`
59
60	221	markom	`/* Temporary variable to increase speed. */`
61			`struct dev_memarea *cur_area;`
62
63	970	simons	`/* Pointer to memory controller device descriptor. */`
64			`struct dev_memarea mc_area = (struct dev_memarea )0;`
65
66	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
67			`int data_ci, insn_ci;`
68
69	525	simons	`/* Virtual address of current access. */`
70	1350	nogj	`oraddr_t cur_vadd;`
71	525	simons
72	261	markom	`/* Calculates bit mask to fit the data */`
73	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
74	261	markom	`int i = 0;`
75			`data--;`
76	382	markom	`while (data >> i)`
77	261	markom	`data \|= 1 << i++;`
78			`return data;`
79			`}`
80
81			`/* Register read and write function for a memory area.`
82			`addr is inside the area, if addr & addr_mask == addr_compare`
83			`(used also by peripheral devices like 16450 UART etc.) */`
84	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
85			`uint32_t size, unsigned granularity, unsigned mc_dev,`
86	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
87			`void (writefunc)(oraddr_t, uint32_t, void *),`
88			`void *dat)`
89	30	lampret	`{`
90	239	markom	`struct dev_memarea **pptmp;`
91	1350	nogj	`unsigned int size_mask = bit_mask (size);`
92	261	markom	`int found_error = 0;`
93			`addr_compare &= addr_mask;`
94	221	markom
95	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
96			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
97			`granularity);`
98	239	markom	`/* Go to the end of the list. */`
99	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
100			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
101			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
102	262	markom	`if (!found_error) {`
103	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
104	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
105			`", size %08"PRIx32", gran %iB\n",`
106	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
107			`granularity);`
108	262	markom	`}`
109	261	markom	`found_error = 1;`
110	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
111			`", size %08"PRIx32", gran %iB\n",`
112	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
113			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
114			`(pptmp)->size, (pptmp)->granularity);`
115	261	markom	`}`
116
117			`if (found_error)`
118			`exit (-1);`
119	537	markom
120	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
121	970	simons
122			`if (mc_dev)`
123			`mc_area = *pptmp;`
124
125	261	markom	`(*pptmp)->addr_mask = addr_mask;`
126			`(*pptmp)->addr_compare = addr_compare;`
127	239	markom	`(*pptmp)->size = size;`
128	261	markom	`(*pptmp)->size_mask = size_mask;`
129	239	markom	`(*pptmp)->granularity = granularity;`
130			`(*pptmp)->readfunc = readfunc;`
131			`(*pptmp)->writefunc = writefunc;`
132	479	markom	`(*pptmp)->log = 0;`
133	882	simons	`(*pptmp)->delayr = 2;`
134			`(*pptmp)->delayw = 2;`
135	1359	nogj	`(*pptmp)->priv_dat = dat;`
136	1362	nogj	`(*pptmp)->chip_select = -1;`
137	239	markom	`(*pptmp)->next = NULL;`
138	261	markom	`}`
139	221	markom
140	261	markom	`/* Register read and write function for a memory area.`
141			`Memory areas should be aligned. Memory area is rounded up to`
142			`fit the nearest 2^n aligment.`
143	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
144			`If mc_dev is 1, this means that this device will be checked first for match`
145	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
146	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
147	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
148			`unsigned mc_dev,`
149	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
150			`void (writefunc)(oraddr_t, uint32_t, void *),`
151			`void *dat)`
152	261	markom	`{`
153	1350	nogj	`unsigned int size_mask = bit_mask (size);`
154			`unsigned int addr_mask = ~size_mask;`
155	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
156	970	simons	`size_mask + 1, granularity, mc_dev,`
157	1359	nogj	`readfunc, writefunc, dat);`
158	30	lampret	`}`
159
160	261	markom
161	30	lampret	`/* Check if access is to registered area of memory. */`
162	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
163	30	lampret	`{`
164	239	markom	`struct dev_memarea *ptmp;`
165	221	markom
166	970	simons	`/* Check memory controller space first */`
167			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
168			`return cur_area = mc_area;`
169
170			`/* Check cached value */`
171	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
172			`return cur_area;`
173
174			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
175			`IFF (config.mc.enabled) {`
176			`/* Check list of registered devices. */`
177			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
178			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
179			`return cur_area = ptmp;`
180			`} else {`
181			`/* Check list of registered devices. */`
182			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
183			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask))`
184			`return cur_area = ptmp;`
185			`}`
186	239	markom	`return cur_area = NULL;`
187	30	lampret	`}`
188
189	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
190	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
191	882	simons	`{`
192			`if (verify_memoryarea(memaddr)) {`
193			`cur_area->delayr = delayr;`
194			`cur_area->delayw = delayw;`
195			`}`
196			`}`
197
198	1319	phoenix	`/* for cpu accesses`
199			`*`
200			`* STATISTICS: check cpu/common/parse.c`
201			`*/`
202	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
203	560	markom	`{`
204	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
205			`}`
206	560	markom
207	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
208	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
209	1319	phoenix	`{`
210			`return(evalsim_mem32_atomic(memaddr, 0));`
211			`}`
212
213	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
214	1319	phoenix	`{`
215	1350	nogj	`uint32_t temp = 0;`
216	1319	phoenix
217	560	markom	`if (verify_memoryarea(memaddr)) {`
218			`switch(cur_area->granularity) {`
219			`case 4:`
220	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
221	560	markom	`break;`
222			`case 1:`
223	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
224			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
225			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
226			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
227	560	markom	`break;`
228			`case 2:`
229	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
230			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
231	560	markom	`break;`
232	1319	phoenix	`default:`
233			`/* if you add new memory granularity be sure to check the formula`
234			`* below for the read delay and fix it if necessery`
235			`*/`
236			`PRINTF("unknown/unhandled memory granularuty\n");`
237			`exit(-1);`
238	560	markom	`}`
239	1319	phoenix	`if (cpu_access)`
240			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
241	560	markom	`}`
242			`return temp;`
243			`}`
244
245	1319	phoenix	`/* for cpu accesses */`
246	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
247	560	markom	`{`
248	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
249			`}`
250	560	markom
251	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
252	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
253	1319	phoenix	`{`
254			`return(evalsim_mem16_atomic(memaddr, 0));`
255			`}`
256
257	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
258	1319	phoenix	`{`
259	1350	nogj	`uint32_t temp = 0;`
260	1319	phoenix
261	560	markom	`if (verify_memoryarea(memaddr)) {`
262			`switch(cur_area->granularity) {`
263			`case 1:`
264	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
265			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
266	1319	phoenix	`if (cpu_access)`
267			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
268	560	markom	`break;`
269			`case 2:`
270	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
271	1319	phoenix	`if (cpu_access)`
272			`runtime.sim.mem_cycles += cur_area->delayr;`
273	560	markom	`break;`
274			`case 4:`
275	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
276	560	markom	`if (memaddr & 2)`
277			`temp &= 0xffff;`
278			`else`
279			`temp >>= 16;`
280			`break;`
281	1319	phoenix	`default:`
282			`/* if you add new memory granularity be sure to check the formula`
283			`* below for the read delay and fix it if necessery`
284			`*/`
285			`PRINTF("unknown/unhandled memory granularuty\n");`
286			`exit(-1);`
287	560	markom	`}`
288			`}`
289			`return temp;`
290			`}`
291
292	1319	phoenix	`/* for cpu accesses */`
293	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
294	560	markom	`{`
295	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
296			`}`
297	560	markom
298	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
299	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
300	1319	phoenix	`{`
301			`return(evalsim_mem8_atomic(memaddr, 0));`
302			`}`
303
304	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
305	1319	phoenix	`{`
306	1350	nogj	`uint32_t temp = 0;`
307	1319	phoenix
308	560	markom	`if (verify_memoryarea(memaddr)) {`
309			`switch(cur_area->granularity) {`
310			`case 1:`
311	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
312	1319	phoenix	`if (cpu_access)`
313			`runtime.sim.mem_cycles += cur_area->delayr;`
314	560	markom	`break;`
315			`case 2:`
316	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
317	560	markom	`if (memaddr & 1)`
318			`temp &= 0xff;`
319			`else`
320			`temp >>= 8;`
321			`break;`
322			`case 4:`
323	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
324	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
325			`temp &= 0xff;`
326			`break;`
327	1319	phoenix	`default:`
328			`/* if you add new memory granularity be sure to check the formula`
329			`* below for the read delay and fix it if necessery`
330			`*/`
331			`PRINTF("unknown/unhandled memory granularuty\n");`
332			`exit(-1);`
333	560	markom	`}`
334			`}`
335			`return temp;`
336			`}`
337
338	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
339			`*`
340	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
341	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
342			`* hence the use of eval_mem32_void()`
343			`*`
344			`* STATISTICS OK.`
345			`*/`
346	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
347	349	simons	`{`
348	1350	nogj	`uint32_t temp;`
349	349	simons
350	525	simons	`cur_vadd = memaddr;`
351	550	markom	`if (config.debug.enabled)`
352	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
353	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
354	611	simons	`if (!cur_area) {`
355	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
356			`memaddr);`
357	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
358			`temp = 0;`
359			`}`
360
361	599	simons	`if (!pending.valid && cur_area->log)`
362	1350	nogj	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
363	550	markom	`if (config.debug.enabled)`
364	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
365			`return temp;`
366	537	markom	`}`
367	349	simons
368	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
369			`*`
370			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
371			`*/`
372	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
373	2	cvs	`{`
374	1350	nogj	`uint32_t temp;`
375	123	markom
376	547	markom	`if (config.sim.mprofile)`
377			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
378
379	538	markom	`if (memaddr & 3) {`
380			`except_handle (EXCEPT_ALIGN, memaddr);`
381			`return 0;`
382			`}`
383	557	markom
384	631	simons	`if (config.debug.enabled)`
385			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
386
387	574	markom	`cur_vadd = memaddr;`
388	631	simons
389			`memaddr = dmmu_translate(memaddr, 0);`
390	574	markom	`if (pending.valid)`
391			`return 0;`
392
393	992	simons	`if (config.dc.enabled)`
394			`temp = dc_simulate_read(memaddr, 4);`
395			`else {`
396			`temp = evalsim_mem32(memaddr);`
397			`if (!cur_area) {`
398	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
399			`memaddr);`
400	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
401			`temp = 0;`
402			`}`
403	611	simons	`}`
404
405	550	markom	`if (config.debug.enabled)`
406	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
407	239	markom	`return temp;`
408	66	lampret	`}`
409
410	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
411			`*`
412			`* STATISTICS OK`
413			`*/`
414	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
415			`int through_dc)`
416	1240	phoenix	`{`
417	1350	nogj	`uint32_t temp;`
418	1240	phoenix
419			`if (memaddr & 3) {`
420			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
421			`return 0;`
422			`}`
423
424			`cur_vadd = memaddr;`
425
426			`if (through_mmu)`
427			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
428
429			`if (through_dc)`
430			`temp = dc_simulate_read(memaddr, 4);`
431			`else {`
432	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
433	1240	phoenix	`if (!cur_area) {`
434	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
435			`") in eval_direct32()\n", memaddr);`
436	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
437			`temp = 0;`
438			`}`
439			`}`
440
441			`return temp;`
442			`}`
443
444
445	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
446			`*`
447			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
448			`*/`
449	1350	nogj	`uint32_t eval_insn(oraddr_t memaddr,int* breakpoint)`
450	349	simons	`{`
451	1350	nogj	`uint32_t temp;`
452	349	simons
453	547	markom	`if (config.sim.mprofile)`
454			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
455	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
456	525	simons	`cur_vadd = pc;`
457	1244	hpanther
458			`// I think this does not belong into eval_insn() 2004-01-30 HP`
459			`// if (config.debug.enabled)`
460			`// breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
461
462			`// We could place the CheckDebugUnit(DebugInstructionFetch) here, but it is currently done`
463			`// in decode_execute_wrapper, so I leave it like this. 2004-01-30 HP`
464
465	631	simons	`if (config.ic.enabled)`
466			`temp = ic_simulate_fetch(memaddr);`
467	992	simons	`else {`
468	631	simons	`temp = evalsim_mem32(memaddr);`
469	992	simons	`if (!cur_area) {`
470	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
471			`memaddr);`
472	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
473			`temp = 0;`
474			`}`
475	611	simons	`}`
476
477	1244	hpanther	`// I think this does not belong into eval_insn() 2004-01-30 HP`
478			`// if (config.debug.enabled)`
479			`// breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
480	349	simons	`return temp;`
481			`}`
482
483	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
484			`*`
485			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
486			`*/`
487	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
488	2	cvs	`{`
489	1350	nogj	`uint16_t temp;`
490	547	markom
491			`if (config.sim.mprofile)`
492			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
493
494	538	markom	`if (memaddr & 1) {`
495			`except_handle (EXCEPT_ALIGN, memaddr);`
496			`return 0;`
497			`}`
498	574	markom
499	631	simons	`if (config.debug.enabled)`
500			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`

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