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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1782

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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "execute.h"
#include "sprs.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "support/profile.h"
#include "dmmu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->chip_select = -1;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  } else if (cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
 
  cur_vadd = memaddr;
 
  memaddr = immu_translate(memaddr);
 
  if (except_pending)
    return 0;
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint16_t)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint8_t)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in toplevel.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, (unsigned long)value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	2	cvs	`#include "execute.h"`
43	32	lampret	`#include "sprs.h"`
44			`#include "except.h"`
45	123	markom	`#include "debug_unit.h"`
46	134	markom	`#include "opcode/or32.h"`
47	547	markom	`#include "support/profile.h"`
48	1308	phoenix	`#include "dmmu.h"`
49			`#include "dcache_model.h"`
50			`#include "icache_model.h"`
51			`#include "debug.h"`
52	1344	nogj	`#include "stats.h"`
53	2	cvs
54	138	markom	`extern char *disassembled;`
55	2	cvs
56	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
57			`peripheral devices. */`
58			`struct dev_memarea *dev_list;`
59
60	221	markom	`/* Temporary variable to increase speed. */`
61			`struct dev_memarea *cur_area;`
62
63	970	simons	`/* Pointer to memory controller device descriptor. */`
64			`struct dev_memarea mc_area = (struct dev_memarea )0;`
65
66	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
67			`int data_ci, insn_ci;`
68
69	525	simons	`/* Virtual address of current access. */`
70	1350	nogj	`oraddr_t cur_vadd;`
71	525	simons
72	261	markom	`/* Calculates bit mask to fit the data */`
73	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
74	261	markom	`int i = 0;`
75			`data--;`
76	382	markom	`while (data >> i)`
77	261	markom	`data \|= 1 << i++;`
78			`return data;`
79			`}`
80
81			`/* Register read and write function for a memory area.`
82			`addr is inside the area, if addr & addr_mask == addr_compare`
83			`(used also by peripheral devices like 16450 UART etc.) */`
84	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
85			`uint32_t size, unsigned granularity, unsigned mc_dev,`
86	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
87			`void (writefunc)(oraddr_t, uint32_t, void *),`
88			`void *dat)`
89	30	lampret	`{`
90	239	markom	`struct dev_memarea **pptmp;`
91	1350	nogj	`unsigned int size_mask = bit_mask (size);`
92	261	markom	`int found_error = 0;`
93			`addr_compare &= addr_mask;`
94	221	markom
95	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
96			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
97			`granularity);`
98	239	markom	`/* Go to the end of the list. */`
99	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
100			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
101			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
102	262	markom	`if (!found_error) {`
103	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
104	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
105			`", size %08"PRIx32", gran %iB\n",`
106	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
107			`granularity);`
108	262	markom	`}`
109	261	markom	`found_error = 1;`
110	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
111			`", size %08"PRIx32", gran %iB\n",`
112	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
113			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
114			`(pptmp)->size, (pptmp)->granularity);`
115	261	markom	`}`
116
117			`if (found_error)`
118			`exit (-1);`
119	537	markom
120	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
121	970	simons
122			`if (mc_dev)`
123			`mc_area = *pptmp;`
124
125	261	markom	`(*pptmp)->addr_mask = addr_mask;`
126			`(*pptmp)->addr_compare = addr_compare;`
127	239	markom	`(*pptmp)->size = size;`
128	261	markom	`(*pptmp)->size_mask = size_mask;`
129	239	markom	`(*pptmp)->granularity = granularity;`
130			`(*pptmp)->readfunc = readfunc;`
131			`(*pptmp)->writefunc = writefunc;`
132	479	markom	`(*pptmp)->log = 0;`
133	882	simons	`(*pptmp)->delayr = 2;`
134			`(*pptmp)->delayw = 2;`
135	1359	nogj	`(*pptmp)->priv_dat = dat;`
136	1362	nogj	`(*pptmp)->chip_select = -1;`
137	239	markom	`(*pptmp)->next = NULL;`
138	261	markom	`}`
139	221	markom
140	261	markom	`/* Register read and write function for a memory area.`
141			`Memory areas should be aligned. Memory area is rounded up to`
142			`fit the nearest 2^n aligment.`
143	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
144			`If mc_dev is 1, this means that this device will be checked first for match`
145	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
146	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
147	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
148			`unsigned mc_dev,`
149	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
150			`void (writefunc)(oraddr_t, uint32_t, void *),`
151			`void *dat)`
152	261	markom	`{`
153	1350	nogj	`unsigned int size_mask = bit_mask (size);`
154			`unsigned int addr_mask = ~size_mask;`
155	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
156	970	simons	`size_mask + 1, granularity, mc_dev,`
157	1359	nogj	`readfunc, writefunc, dat);`
158	30	lampret	`}`
159
160	261	markom
161	30	lampret	`/* Check if access is to registered area of memory. */`
162	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
163	30	lampret	`{`
164	239	markom	`struct dev_memarea *ptmp;`
165	221	markom
166	970	simons	`/* Check memory controller space first */`
167			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
168			`return cur_area = mc_area;`
169
170			`/* Check cached value */`
171	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
172			`return cur_area;`
173
174			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
175	1375	nogj	`/* Check list of registered devices. */`
176			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
177			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
178			`return cur_area = ptmp;`
179	239	markom	`return cur_area = NULL;`
180	30	lampret	`}`
181
182	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
183	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
184	882	simons	`{`
185			`if (verify_memoryarea(memaddr)) {`
186			`cur_area->delayr = delayr;`
187			`cur_area->delayw = delayw;`
188			`}`
189			`}`
190
191	1319	phoenix	`/* for cpu accesses`
192			`*`
193			`* STATISTICS: check cpu/common/parse.c`
194			`*/`
195	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
196	560	markom	`{`
197	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
198			`}`
199	560	markom
200	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
201	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
202	1319	phoenix	`{`
203			`return(evalsim_mem32_atomic(memaddr, 0));`
204			`}`
205
206	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
207	1319	phoenix	`{`
208	1350	nogj	`uint32_t temp = 0;`
209	1319	phoenix
210	560	markom	`if (verify_memoryarea(memaddr)) {`
211			`switch(cur_area->granularity) {`
212			`case 4:`
213	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
214	560	markom	`break;`
215			`case 1:`
216	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
217			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
218			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
219			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
220	560	markom	`break;`
221			`case 2:`
222	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
223			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
224	560	markom	`break;`
225	1319	phoenix	`default:`
226			`/* if you add new memory granularity be sure to check the formula`
227			`* below for the read delay and fix it if necessery`
228			`*/`
229			`PRINTF("unknown/unhandled memory granularuty\n");`
230			`exit(-1);`
231	560	markom	`}`
232	1319	phoenix	`if (cpu_access)`
233			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
234	560	markom	`}`
235			`return temp;`
236			`}`
237
238	1319	phoenix	`/* for cpu accesses */`
239	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
240	560	markom	`{`
241	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
242			`}`
243	560	markom
244	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
245	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
246	1319	phoenix	`{`
247			`return(evalsim_mem16_atomic(memaddr, 0));`
248			`}`
249
250	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
251	1319	phoenix	`{`
252	1350	nogj	`uint32_t temp = 0;`
253	1319	phoenix
254	560	markom	`if (verify_memoryarea(memaddr)) {`
255			`switch(cur_area->granularity) {`
256			`case 1:`
257	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
258			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
259	1319	phoenix	`if (cpu_access)`
260			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
261	560	markom	`break;`
262			`case 2:`
263	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
264	1319	phoenix	`if (cpu_access)`
265			`runtime.sim.mem_cycles += cur_area->delayr;`
266	560	markom	`break;`
267			`case 4:`
268	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
269	560	markom	`if (memaddr & 2)`
270			`temp &= 0xffff;`
271			`else`
272			`temp >>= 16;`
273			`break;`
274	1319	phoenix	`default:`
275			`/* if you add new memory granularity be sure to check the formula`
276			`* below for the read delay and fix it if necessery`
277			`*/`
278			`PRINTF("unknown/unhandled memory granularuty\n");`
279			`exit(-1);`
280	560	markom	`}`
281			`}`
282			`return temp;`
283			`}`
284
285	1319	phoenix	`/* for cpu accesses */`
286	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
287	560	markom	`{`
288	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
289			`}`
290	560	markom
291	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
292	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
293	1319	phoenix	`{`
294			`return(evalsim_mem8_atomic(memaddr, 0));`
295			`}`
296
297	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
298	1319	phoenix	`{`
299	1350	nogj	`uint32_t temp = 0;`
300	1319	phoenix
301	560	markom	`if (verify_memoryarea(memaddr)) {`
302			`switch(cur_area->granularity) {`
303			`case 1:`
304	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
305	1319	phoenix	`if (cpu_access)`
306			`runtime.sim.mem_cycles += cur_area->delayr;`
307	560	markom	`break;`
308			`case 2:`
309	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
310	560	markom	`if (memaddr & 1)`
311			`temp &= 0xff;`
312			`else`
313			`temp >>= 8;`
314			`break;`
315			`case 4:`
316	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
317	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
318			`temp &= 0xff;`
319			`break;`
320	1319	phoenix	`default:`
321			`/* if you add new memory granularity be sure to check the formula`
322			`* below for the read delay and fix it if necessery`
323			`*/`
324			`PRINTF("unknown/unhandled memory granularuty\n");`
325			`exit(-1);`
326	560	markom	`}`
327			`}`
328			`return temp;`
329			`}`
330
331	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
332			`*`
333	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
334	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
335			`* hence the use of eval_mem32_void()`
336			`*`
337			`* STATISTICS OK.`
338			`*/`
339	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
340	349	simons	`{`
341	1350	nogj	`uint32_t temp;`
342	349	simons
343	525	simons	`cur_vadd = memaddr;`
344	550	markom	`if (config.debug.enabled)`
345	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
346	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
347	611	simons	`if (!cur_area) {`
348	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
349			`memaddr);`
350	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
351			`temp = 0;`
352	1386	nogj	`} else if (cur_area->log)`
353			`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
354	611	simons
355	550	markom	`if (config.debug.enabled)`
356	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
357			`return temp;`
358	537	markom	`}`
359	349	simons
360	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
361			`*`
362			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
363			`*/`
364	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
365	2	cvs	`{`
366	1350	nogj	`uint32_t temp;`
367	123	markom
368	547	markom	`if (config.sim.mprofile)`
369			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
370
371	538	markom	`if (memaddr & 3) {`
372			`except_handle (EXCEPT_ALIGN, memaddr);`
373			`return 0;`
374			`}`
375	557	markom
376	631	simons	`if (config.debug.enabled)`
377			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
378
379	574	markom	`cur_vadd = memaddr;`
380	631	simons
381			`memaddr = dmmu_translate(memaddr, 0);`
382	1386	nogj	`if (except_pending)`
383	574	markom	`return 0;`
384
385	992	simons	`if (config.dc.enabled)`
386			`temp = dc_simulate_read(memaddr, 4);`
387			`else {`
388			`temp = evalsim_mem32(memaddr);`
389			`if (!cur_area) {`
390	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
391			`memaddr);`
392	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
393			`temp = 0;`
394			`}`
395	611	simons	`}`
396
397	550	markom	`if (config.debug.enabled)`
398	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
399	239	markom	`return temp;`
400	66	lampret	`}`
401
402	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
403			`*`
404			`* STATISTICS OK`
405			`*/`
406	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
407			`int through_dc)`
408	1240	phoenix	`{`
409	1350	nogj	`uint32_t temp;`
410	1240	phoenix
411			`if (memaddr & 3) {`
412			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
413			`return 0;`
414			`}`
415
416			`cur_vadd = memaddr;`
417
418			`if (through_mmu)`
419			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
420
421			`if (through_dc)`
422			`temp = dc_simulate_read(memaddr, 4);`
423			`else {`
424	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
425	1240	phoenix	`if (!cur_area) {`
426	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
427			`") in eval_direct32()\n", memaddr);`
428	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
429			`temp = 0;`
430			`}`
431			`}`
432
433			`return temp;`
434			`}`
435
436
437	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
438			`*`
439			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
440			`*/`
441	1386	nogj	`uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)`
442	349	simons	`{`
443	1350	nogj	`uint32_t temp;`
444	349	simons
445	547	markom	`if (config.sim.mprofile)`
446			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
447	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
448	1244	hpanther
449	1386	nogj	`cur_vadd = memaddr;`
450	1244	hpanther
451	1386	nogj	`memaddr = immu_translate(memaddr);`
452
453			`if (except_pending)`
454			`return 0;`
455
456			`if (config.debug.enabled)`
457			`*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);`
458
459	631	simons	`if (config.ic.enabled)`
460			`temp = ic_simulate_fetch(memaddr);`
461	992	simons	`else {`
462	631	simons	`temp = evalsim_mem32(memaddr);`
463	992	simons	`if (!cur_area) {`
464	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
465			`memaddr);`
466	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
467			`temp = 0;`
468			`}`
469	611	simons	`}`
470
471	1386	nogj	`if (config.debug.enabled)`
472			`*breakpoint += CheckDebugUnit(DebugLoadData,temp);`
473	349	simons	`return temp;`
474			`}`
475
476	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
477			`*`
478			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
479			`*/`
480	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
481	2	cvs	`{`
482	1350	nogj	`uint16_t temp;`
483	547	markom
484			`if (config.sim.mprofile)`
485			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
486
487	538	markom	`if (memaddr & 1) {`
488			`except_handle (EXCEPT_ALIGN, memaddr);`
489			`return 0;`
490			`}`
491	574	markom
492	631	simons	`if (config.debug.enabled)`
493			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
494
495	574	markom	`cur_vadd = memaddr;`
496	631	simons
497			`memaddr = dmmu_translate(memaddr, 0);`
498	1386	nogj	`if (except_pending)`
499	574	markom	`return 0;`
500	66	lampret

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