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/* except.c -- Simulation of OR1K exceptions

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include "abstract.h"

#include "except.h"

#include "sprs.h"

#include "sim-config.h"

static void except_handle_backend(int,unsigned long,unsigned long);

extern int cont_run;

extern struct iqueue_entry iqueue[20];

extern unsigned long pc;

extern unsigned long pcnext;

extern unsigned long pc_phy;

extern struct iqueue_entry iqueue[];

extern int delay_insn;

int cycle_delay = 0;  /* Added by CZ 27/05/01 */

struct _pending pending;

void ClearPendingException()

{

  if(pending.valid && pending.type != EXCEPT_RESET)

    {

      pending.valid = 0;

      pending.type = 0;

      pending.address = 0;

      pending.saved = 0;

    }

}

/* The delayed_pc and delayed_pcnext are fields which hold

   the original value of the PC across breakpoint exceptions

   in the case of a development interface. Due to an implementation

   issues, DIR injected instructions can modify these values

   when in fact they should not. So we save and restore them

   later on. */

static unsigned long delayed_pc = 0;

static unsigned long delayed_pcnext = 0;

static int delayed_pc_valid = 0;

void ClearPreparedPCState()

{

  delayed_pc_valid = 0;

}

/* This routine is never called if the cpu is not stalled...

   i.e. cpu_stalled == 0. _execute_update_pc is called

   directly in that case. This routine exists to sort out

   the difference between a single step break and a full

   software break. */

void PrepareExceptionPC(unsigned long t_pc,unsigned long t_pcnext)

{

  /* If a real exception occurred which has stalled

     the CPU, we are expecting to halt before the end

     of the instruction. Otherwise, if it is a single

     step that has caused the halt, we are expected to

     complete the entire instruction and stop after

     it is finished. */

  if(pending.valid)

    {

      delayed_pc = t_pc;

      delayed_pcnext = t_pcnext;

      delayed_pc_valid = 1;

    }

  else

    _execute_update_pc(t_pc,t_pcnext);

}

void PrepareException()

{

  if(delayed_pc_valid)

    {

      pc = delayed_pc;

      pcnext = delayed_pcnext;

      pc_phy = simulate_ic_mmu_fetch(pc);

      if (verify_memoryarea(pc_phy))

              except_handle(EXCEPT_BUSERR, pc);

      delayed_pc_valid = delayed_pc = delayed_pcnext = 0;

    }

  if(pending.valid)

    except_handle_backend(pending.type,pending.address,pending.saved);

}

/* Handle OR1K exceptions. */

void except_handle(int except, unsigned long ea)

{

  pending.valid = 1;

  pending.type = except;

  pending.address = ea;

  pending.saved = pc;

  if(DebugCheckException(except))

    {

      pending.valid = 0;

      pending.type = 0;

      pending.address = 0;

      pending.saved = 0;

    }

  else

    {

      printf("Exception 0x%x (%s): ", except, EXCEPT_NAME(except));

      printf("Iqueue[0].insn_addr: 0x%x  Eff ADDR: 0x%x\n",  iqueue[0].insn_addr, ea);

      printf("  pc: 0x%x  pcnext: 0x%x\n",  pc, pcnext);

    }

  cycle_delay = 0;  /* An exception stalls the CPU 0 clock cycles */

}

static void except_handle_backend(int except, unsigned long ea, unsigned long pc_saved)

{

  /* Ignore masked exceptions */

  if (! IS_NME(except) && (!(mfspr(SPR_SR) & SPR_SR_EXR))) {

    if (config.sim.verbose)

                  printf("INFO: Exception occured while exception detection was disabled.\n");

                return;

        }

#if ONLY_VIRTUAL_MACHINE

        fprintf(stderr, "WARNING: No exception processing while ONLY_VIRTUAL_MACHINE is defined.\n");

        cont_run = 0;

#else

        if (delay_insn) {

                printf("INFO: Exception during execution of delay slot insn.\n");

                pc -= 4;

        }

#if 0

        if ((pcnext != (pc + 4)) && (except != EXCEPT_ITLBMISS)) {      /* Always execute delay slot insn */

                printf("XXXXXXXXXXXXXX\n");

                fetch();                                                /* before starting with exception */

                decode(&iqueue[0]);                                      /* (itlbmiss is special case) */

                execute();

        }

#endif

        pc_saved = pc & ~0x3;

  if (except == EXCEPT_ILLEGAL)

        mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_ALIGN)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_DTLBMISS)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_DPF)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_BUSERR)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_TRAP)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else if (except == EXCEPT_RANGE)

    mtspr(SPR_EPCR_BASE, pending.saved);

  else

        mtspr(SPR_EPCR_BASE, pc_saved);

        mtspr(SPR_EEAR_BASE, ea);

        mtspr(SPR_ESR_BASE, mfspr(SPR_SR));

        /* Address translation is always disabled when starting exception. */

        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_DME));

        mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IME));

        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_OVE);     /* Disable overflow flag exception. */

        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_SUPV);     /* SUPV mode */

        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR);     /* Disable interrupts. */

  pending.valid = 0;

  pending.type = 0;

  pending.address = 0;

  pending.saved = 0;

        pc = (unsigned long)except;

        /* This has been removed. All exceptions (not just SYSCALL) suffer

           from the same problem. The solution is to continue just like

           the pipeline would, and issue the exception on the next

           clock cycle. We assume now that this function is being called

           ->BEFORE<- the instruction fetch and after the previous update

           which always yields the correct behavior. This has the added

           advantage that a debugger can prevent an exception from

           taking place by resetting the pc. */

#if 0

        /* MM: We do pc update after the execute (in the simulator), so we

           decrease it by 4 so that next instruction points to first exception

           instruction.  Do NOT comment this out. */

        if (except == EXCEPT_SYSCALL)

          pc -= 4;

#endif

        pcnext = pc+4;

        /* Added by CZ 27/05/01 */

        pc_phy = pc;      /* An exception always turns off the MMU, so

                             pc is always pc_phy */

#endif

}