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/* execute.c -- OR1K architecture dependent simulation

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Most of the OR1K simulation is done in here.

   When SIMPLE_EXECUTION is defined below a file insnset.c is included!

*/

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <ctype.h>

#include "config.h"

#include "arch.h"

#include "opcode/or32.h"

#include "branch_predict.h"

#include "abstract.h"

#include "labels.h"

#include "parse.h"

#include "execute.h"

#include "stats.h"

#include "except.h"

#include "sprs.h"

#include "sim-config.h"

#include "debug_unit.h"

/* Whether instructions set overflow flag */

#define SET_OV_FLAG     1

/* Whether arithmethic instructions set flag on zero */

#define ARITH_SET_FLAG  1

/* Specifies, whether we should use generated decode_execute or

   runtime generated. In latter case file 'insnset.c' is included

   at the bottom of this file */

//#define SIMPLE_EXECUTION 1

/* General purpose registers. */

machword reg[MAX_GPRS];

/* Instruction queue */

struct iqueue_entry iqueue[20];

/* Is current insn in execution a delay insn? */

int delay_insn;

/* Benchmark multi issue execution */

int multissue[20];

int supercycles;

int issued_per_cycle = 4;

int hazardwait = 0;

/* Whether break was hit - so we can step over a break */

static int break_just_hit = 0;

/* freemem 'pointer' */

extern unsigned long freemem;

/* Completition queue */

struct iqueue_entry icomplet[20];

/* Program counter (and translated PC) */

unsigned long pc;

unsigned long pc_phy;

/* Previous program counter */

unsigned long pcprev = 0;

/* Temporary program counter */

unsigned long pcnext;

/* Delay instruction effective address register */

unsigned long pcdelay;

/* CCR */

int flag;

/* CCR (for dependency calculation) */

char ccr_flag[10] = "flag";

/* Cycles counts fetch stages */

int cycles;

/* Each cycle has counter of mem_cycles; this value is joined with cycles

   at the end of the cycle; no sim originated memory accesses should be

   performed inbetween. */

int mem_cycles;

/* Instructions executed */

int instructions;

/* Load and store stalls */

int loadcycles, storecycles;

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;

static int sbuf_buf[MAX_SBUF_LEN] = {0};

static int sbuf_prev_cycles = 0;

/* Num cycles waiting for stores to complete */

int sbuf_wait_cyc = 0;

/* Number of total store cycles */

int sbuf_total_cyc = 0;

/* Local data needed for execution.  */

static struct iqueue_entry *cur;

static int next_delay_insn;

static int breakpoint;

static unsigned long *op;

static int num_op;

/* Implementation specific.

   Get an actual value of a specific register. */

unsigned long evalsim_reg32(int regno)

{

  if (regno < MAX_GPRS) {

    return reg[regno];

  } else {

    printf("\nABORT: read out of registers\n");

    cont_run = 0;

    return 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

void setsim_reg32(int regno, unsigned long value)

{

  if (regno == 0)               /* gpr0 is always zero */

    value = 0;

  if (regno < MAX_GPRS) {

    reg[regno] = value;

  } else {

    printf("\nABORT: write out of registers\n");

    cont_run = 0;

  }

}

/* Implementation specific.

   Get an actual value of a specific register. */

inline static unsigned long eval_reg32(int regno)

{

  if (regno < MAX_GPRS) {

    IFF(config.cpu.raw_range) {

      int delta = (cycles - raw_stats.reg[regno]);

      if ((unsigned long)delta < (unsigned long)config.cpu.raw_range)

        raw_stats.range[delta]++;

    }

    return reg[regno];

  } else {

    printf("\nABORT: read out of registers\n");

    cont_run = 0;

    return 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

inline static void set_reg32(int regno, unsigned long value)

{

#if 0   

  if (strcmp(regstr, FRAME_REG) == 0) {

    printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc);

    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regno), value);

  }

  if (strcmp(regstr, STACK_REG) == 0) {

    printf("SP (%s) modified by insn at %x. ", STACK_REG, pc);

    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regmo), value);

  }

#endif

  if (regno < MAX_GPRS) {

    reg[regno] = value;

    IFF(config.cpu.raw_range)

      raw_stats.reg[regno] = cycles;

  } else {

    printf("\nABORT: write out of registers\n");

    cont_run = 0;

  }

}

/* Does srcoperand depend on computation of dstoperand? Return

   non-zero if yes.

 Cycle t                 Cycle t+1

dst: irrelevant         src: immediate                  always 0

dst: reg1 direct        src: reg2 direct                0 if reg1 != reg2

dst: reg1 disp          src: reg2 direct                always 0

dst: reg1 direct        src: reg2 disp                  0 if reg1 != reg2

dst: reg1 disp          src: reg2 disp                  always 1 (store must

                                                        finish before load)

dst: flag               src: flag                       always 1

*/

int depend_operands(prev, next)

     struct iqueue_entry *prev;

     struct iqueue_entry *next;

{

  /* Find destination type. */

  unsigned long type = 0;

  int i = 0;

  if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG

      && or32_opcodes[next->insn_index].flags & OR32_R_FLAG)

    return 1;

  while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))

    if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)

      {

        type = prev->op[i + MAX_OPERANDS];

        break;

      }

    else

      i++;

  /* We search all source operands - if we find confict => return 1 */

  i = 0;

  while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))

    if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))

      {

        if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS)

          if (type & OPTYPE_DIS)

            return 1;

          else if (next->op[i] == prev->op[i]

                   && (next->op[i + MAX_OPERANDS] & OPTYPE_REG))

            return 1;

        if (next->op[i] == prev->op[i]

            && (next->op[i + MAX_OPERANDS] & OPTYPE_REG)

            && (type & OPTYPE_REG))

          return 1;

        i++;

      }

    else

      i++;

  return 0;

}

/* Implementation specific.

   Parses and returns operands. */

static void

eval_operands (unsigned long insn, int insn_index, int* breakpoint)

{

  struct insn_op_struct *opd = op_start[insn_index];

  unsigned long data = 0;

  int dis = 0;

  int no = 0;

  while (1)

    {

      unsigned long tmp = 0, nbits = 0;

      while (1)

        {

          tmp |= ((insn  >> (opd->type & OPTYPE_SHR)) & ((1 << opd->data) - 1)) << nbits;

          nbits += opd->data;

          if (opd->type & OPTYPE_OP)

            break;

          opd++;

        }

      /* Do we have to sign extend? */

      if (opd->type & OPTYPE_SIG)

        {

          int sbit = (opd->type & OPTYPE_SBIT) >> OPTYPE_SBIT_SHR;

          if (tmp & (1 << sbit))

            tmp |= 0xFFFFFFFF << sbit;

        }

      if (opd->type & OPTYPE_DIS) {

        /* We have to read register later.  */

        data += tmp;

        dis = 1;

      } else

        {

          if (dis && (opd->type & OPTYPE_REG))

            op[no] = data + eval_reg32 (tmp);

          else

            op[no] = tmp;

          op[no + MAX_OPERANDS] = opd->type | (dis ? OPTYPE_DIS : 0);

          no++;

          data = 0;

          dis = 0;

        }

      if(opd->type & OPTYPE_LAST) {

        num_op = no;

        return;

      }

      opd++;

    }

  num_op = no;

}

/* Implementation specific.

   Evaluates source operand op_no. */

inline static unsigned long eval_operand32 (int op_no, int *breakpoint)

{

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)

    /* memory accesses are not cached */

    return eval_mem32 (op[op_no], breakpoint);

  else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {

    return eval_reg32 (op[op_no]);

  } else {

    return op[op_no];

  }

}

/* Implementation specific.

   Evaluates source operand op_no. */

static unsigned long eval_operand16 (int op_no, int *breakpoint)

{

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {

    return eval_mem16 (op[op_no], breakpoint);

  }

  else {

    fprintf (stderr, "Invalid operand type.\n");

    exit (1);

  }

}

/* Implementation specific.

   Evaluates source operand op_no. */

static unsigned long eval_operand8 (int op_no, int *breakpoint)

{

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)

    return eval_mem8 (op[op_no], breakpoint);

  else {

    fprintf (stderr, "Invalid operand type.\n");

    exit (1);

  }

}

/* Implementation specific.

   Set destination operand (register direct, register indirect

   (with displacement) with value. */

inline static void set_operand32(int op_no, unsigned long value, int* breakpoint)

{

  /* Mark this as destination operand.  */

  IFF (config.cpu.dependstats) op[op_no + MAX_OPERANDS] |= OPTYPE_DST;

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {

    set_mem32(op[op_no], value, breakpoint);

  } else if (op[op_no + MAX_OPERANDS] & OPTYPE_REG) {

    set_reg32(op[op_no], value);

  } else {

    fprintf (stderr, "Invalid operand type.\n");

    exit (1);

  }

}

/* Implementation specific.

   Set destination operand (register direct, register indirect

   (with displacement) with value. */

void set_operand16(int op_no, unsigned long value, int* breakpoint)

{

  /* Mark this as destination operand.  */

  op[op_no + MAX_OPERANDS] |= OPTYPE_DST;

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {

    set_mem16(op[op_no], value, breakpoint);

  }

  else

    {

      fprintf (stderr, "Invalid operand type.\n");

      exit (1);

    }

}

/* Implementation specific.

   Set destination operand (register direct, register indirect

   (with displacement) with value. */

void set_operand8(int op_no, unsigned long value, int* breakpoint)

{

  /* Mark this as destination operand.  */

  op[op_no + MAX_OPERANDS] |= OPTYPE_DST;

  if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS)

    set_mem8(op[op_no], value, breakpoint);

  else

    {

      fprintf (stderr, "Invalid operand type.\n");

      exit (1);

    }

}

/* Sets a new SPR_SR_OV value, based on next register value */

static inline unsigned long set_ov_flag (unsigned long value)

{

#if SET_OV_FLAG

  value & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0);

#endif

  return value;

}

/* Modified by CZ 26/05/01 for new mode execution */

/* Fetch returns nonzero if instruction should NOT be executed.  */

static inline int fetch()

{

  struct mem_entry *entry;

  debug(5, "fetch()\n");

  /* Update the pc for pending exceptions, or get physical pc */

  if (!pending.valid)

    pc_phy = immu_translate(pc, 0);

  if(pending.valid)

    except_handle_backend(pending.type, pending.address, pending.saved);

  if (CHECK_BREAKPOINTS) {

    /* MM: Check for breakpoint.  This has to be done in fetch cycle,

       because of peripheria.

       MM1709: if we cannot access the memory entry, we could not set the

       breakpoint earlier, so just chech the breakpoint list.  */

    if (has_breakpoint (pc_phy) && !break_just_hit) {

      break_just_hit = 1;

      return 1; /* Breakpoint set. */

    }

    break_just_hit = 0;

  }

  instructions++;

  pc_phy &= ~0x03;

  /* Fetch instruction. */

  iqueue[0].insn_addr = pc;

  iqueue[0].insn = eval_insn (pc_phy, &breakpoint);;

  /* update_pc will be called after execution */

  return 0;

}

/* This code actually updates the PC value.  */

static inline void update_pc ()

{

  pcprev = pc; /* Store value for later */

  pc = pcnext;

  pcnext = delay_insn ? pcdelay : pcnext + 4;

}

static inline void analysis ()

{

  if (config.cpu.dependstats)

    /* Instruction waits in completition buffer until retired. */

    memcpy (&icomplet[0], &iqueue[0], sizeof (struct iqueue_entry));

  if (config.sim.history) {

    int i;

    /* History of execution */

    for (i = HISTEXEC_LEN - 1; i; i--)

      histexec[i] = histexec[i - 1];

    histexec[0] = icomplet[0].insn_addr;        /* add last insn */

  }

}

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static inline sbuf_store (int cyc) {

  int delta = cycles - sbuf_prev_cycles;

  sbuf_total_cyc += cyc;

  sbuf_prev_cycles = cycles;

  //printf (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Store buffer is full, take one out */

  if (sbuf_count >= config.cpu.sbuf_len) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  /* Put newest store in the buffer */

  sbuf_buf[sbuf_head] = cyc;

  sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;

  sbuf_count++;

  //printf ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Store buffer analysis - previous stores should commit, before any load */

static inline sbuf_load () {

  int delta = cycles - sbuf_prev_cycles;

  sbuf_prev_cycles = cycles;

  //printf (">LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Wait for all stores to complete */

  while (sbuf_count > 0) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  //printf ("|LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Execution logger.  */

inline void dump_exe_log()

{

  unsigned long i = iqueue[0].insn_addr;

  if (i == 0xffffffff) return;

  if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {

    if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {

      fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", instructions);

    }

    switch (config.sim.exe_log_type) {

    case EXE_LOG_HARDWARE:

      fprintf (runtime.sim.fexe_log, "\nEXECUTED(): %.8lx:  ", i);

      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));

      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));

      for(i = 0; i < MAX_GPRS; i++) {

        if (i % 4 == 0)

          fprintf(runtime.sim.fexe_log, "\n");

        fprintf (runtime.sim.fexe_log, "GPR%2u: %.8lx  ", i, reg[i]);

      }

      fprintf (runtime.sim.fexe_log, "\n");

      fprintf (runtime.sim.fexe_log, "SR   : %.8lx  ", mfspr(SPR_SR));

      fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx  ", mfspr(SPR_EPCR_BASE));

      fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx  ", mfspr(SPR_EEAR_BASE));

      fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));

      break;

    case EXE_LOG_SIMPLE:

    case EXE_LOG_SOFTWARE:

      {

        int labels = 0;

        if (verify_memoryarea(i)) {

          struct label_entry *entry;

          entry = get_label(i);

          if (entry) {

            fprintf (runtime.sim.fexe_log, "%s: ", entry->name);

            labels++;

          }

        } else {

          fprintf (runtime.sim.fexe_log, "<invalid addr>: ");

          labels++;

        }

        if (labels) fprintf (runtime.sim.fexe_log, "\n");

        if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {

          int i;

          for (i = 0; i < num_op; i++)

            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {

              fprintf (runtime.sim.fexe_log, "EA =%08x ", op[i]);

            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {

              fprintf (runtime.sim.fexe_log, "r%-2i=%08x ", op[i], evalsim_reg32 (op[i]));

            } else

            fprintf (runtime.sim.fexe_log, "             ");

          for (; i < 3; i++)

            fprintf (runtime.sim.fexe_log, "             ");

        }

        fprintf (runtime.sim.fexe_log, "%.8lx ", i);

        if (index >= 0) {

          extern char *disassembled;

          disassemble_index (iqueue[0].insn, iqueue[0].insn_index);

          fprintf (runtime.sim.fexe_log, "%s\n", disassembled);

        } else

          fprintf (runtime.sim.fexe_log, "<invalid>\n");

      }

    }

  }

}

#if 0

void print_time (int cycles, char *output)

{

  int i = 0, c_ps = config.sim.clkcycle_ps;

  while (c_ps % 1000 == 0 && i < 2) {

    c_ps /= 1000;

    i++;

  }

  c_ps *= cycles;

  sprintf (output, "%i%cs", cycles, i == 0 ? 'p' : i == 1 ? 'n': 'u');

}

#endif

void dumpreg()

{

  int i;

  char temp[100];

  dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4, 1, 0);

  generate_time_pretty (temp, cycles);