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/* execute.c -- OR1K architecture dependent simulation

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Most of the OR1K simulation is done in here.

   When SIMPLE_EXECUTION is defined below a file insnset.c is included!

*/

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <ctype.h>

#include "config.h"

#include "arch.h"

#include "opcode/or32.h"

#include "branch_predict.h"

#include "abstract.h"

#include "labels.h"

#include "parse.h"

#include "execute.h"

#include "stats.h"

#include "except.h"

#include "sprs.h"

#include "sim-config.h"

#include "debug_unit.h"

/* General purpose registers. */

machword reg[MAX_GPRS];

/* Instruction queue */

struct iqueue_entry iqueue[20];

/* Is current insn in execution a delay insn? */

int delay_insn;

/* Benchmark multi issue execution */

int multissue[20];

int supercycles;

int issued_per_cycle = 4;

int hazardwait = 0;

/* Whether break was hit - so we can step over a break */

static int break_just_hit = 0;

/* freemem 'pointer' */

extern unsigned long freemem;

/* Completition queue */

struct iqueue_entry icomplet[20];

/* Program counter (and translated PC) */

unsigned long pc;

unsigned long pc_phy;

/* Previous program counter */

unsigned long pcprev = 0;

/* Temporary program counter */

unsigned long pcnext;

/* Delay instruction effective address register */

unsigned long pcdelay;

/* CCR */

int flag;

/* CCR (for dependency calculation) */

char ccr_flag[10] = "flag";

/* Cycles counts fetch stages */

int cycles;

/* Each cycle has counter of mem_cycles; this value is joined with cycles

   at the end of the cycle; no sim originated memory accesses should be

   performed inbetween. */

int mem_cycles;

/* Instructions executed */

int instructions;

/* Load and store stalls */

int loadcycles, storecycles;

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static int sbuf_head = 0, sbuf_tail = 0, sbuf_count = 0;

static int sbuf_buf[MAX_SBUF_LEN] = {0};

static int sbuf_prev_cycles = 0;

/* Num cycles waiting for stores to complete */

int sbuf_wait_cyc = 0;

/* Number of total store cycles */

int sbuf_total_cyc = 0;

/* Whether we are doing statistical analysis */

int do_stats = 0;

/* Local data needed for execution.  */

static int next_delay_insn;

static int breakpoint;

static unsigned long *op;

static int num_op;

/* Implementation specific.

   Get an actual value of a specific register. */

unsigned long evalsim_reg32(int regno)

{

  if (regno < MAX_GPRS) {

    return reg[regno];

  } else {

    printf("\nABORT: read out of registers\n");

    cont_run = 0;

    return 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

void setsim_reg32(int regno, unsigned long value)

{

  if (regno == 0)               /* gpr0 is always zero */

    value = 0;

  if (regno < MAX_GPRS) {

    reg[regno] = value;

  } else {

    printf("\nABORT: write out of registers\n");

    cont_run = 0;

  }

}

/* Implementation specific.

   Get an actual value of a specific register. */

inline static unsigned long eval_reg32(int regno)

{

  if (regno < MAX_GPRS) {

#if RAW_RANGE_STATS

      int delta = (cycles - raw_stats.reg[regno]);

      if ((unsigned long)delta < (unsigned long)MAX_RAW_RANGE)

        raw_stats.range[delta]++;

#endif /* RAW_RANGE */

    return reg[regno];

  } else {

    printf("\nABORT: read out of registers\n");

    cont_run = 0;

    return 0;

  }

}

/* Implementation specific.

   Set a specific register with value. */

inline static void set_reg32(int regno, unsigned long value)

{

#if 0   

  if (strcmp(regstr, FRAME_REG) == 0) {

    printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc);

    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regno), value);

  }

  if (strcmp(regstr, STACK_REG) == 0) {

    printf("SP (%s) modified by insn at %x. ", STACK_REG, pc);

    printf("Old:%.8lx  New:%.8lx\n", eval_reg(regmo), value);

  }

#endif

  if (regno < MAX_GPRS) {

    reg[regno] = value;

#if RAW_RANGE_STATS

    raw_stats.reg[regno] = cycles;

#endif /* RAW_RANGE */

  } else {

    printf("\nABORT: write out of registers\n");

    cont_run = 0;

  }

}

/* Does srcoperand depend on computation of dstoperand? Return

   non-zero if yes.

 Cycle t                 Cycle t+1

dst: irrelevant         src: immediate                  always 0

dst: reg1 direct        src: reg2 direct                0 if reg1 != reg2

dst: reg1 disp          src: reg2 direct                always 0

dst: reg1 direct        src: reg2 disp                  0 if reg1 != reg2

dst: reg1 disp          src: reg2 disp                  always 1 (store must

                                                        finish before load)

dst: flag               src: flag                       always 1

*/

int depend_operands(prev, next)

     struct iqueue_entry *prev;

     struct iqueue_entry *next;

{

  /* Find destination type. */

  unsigned long type = 0;

  int i = 0;

  if (or32_opcodes[prev->insn_index].flags & OR32_W_FLAG

      && or32_opcodes[next->insn_index].flags & OR32_R_FLAG)

    return 1;

  while (!(prev->op[i + MAX_OPERANDS] & OPTYPE_LAST))

    if (prev->op[i + MAX_OPERANDS] & OPTYPE_DST)

      {

        type = prev->op[i + MAX_OPERANDS];

        break;

      }

    else

      i++;

  /* We search all source operands - if we find confict => return 1 */

  i = 0;

  while (!(next->op[i + MAX_OPERANDS] & OPTYPE_LAST))

    if (!(next->op[i + MAX_OPERANDS] & OPTYPE_DST))

      {

        if (next->op[i + MAX_OPERANDS] & OPTYPE_DIS)

          if (type & OPTYPE_DIS)

            return 1;

          else if (next->op[i] == prev->op[i]

                   && (next->op[i + MAX_OPERANDS] & OPTYPE_REG))

            return 1;

        if (next->op[i] == prev->op[i]

            && (next->op[i + MAX_OPERANDS] & OPTYPE_REG)

            && (type & OPTYPE_REG))

          return 1;

        i++;

      }

    else

      i++;

  return 0;

}

/* Sets a new SPR_SR_OV value, based on next register value */

#if SET_OV_FLAG

#define set_ov_flag(value) (((value) & 0x80000000 ? setsprbits (SPR_SR, SPR_SR_OV, 1) : setsprbits (SPR_SR, SPR_SR_OV, 0)), value)

#else

#define set_ov_flag(value) (value)

#endif

/* Modified by CZ 26/05/01 for new mode execution */

/* Fetch returns nonzero if instruction should NOT be executed.  */

static inline int fetch()

{

  struct mem_entry *entry;

  /* Update the pc for pending exceptions, or get physical pc */

  if (!pending.valid)

    pc_phy = immu_translate(pc, 0);

  if(pending.valid)

    except_handle_backend(pending.type, pending.address, pending.saved);

  if (CHECK_BREAKPOINTS) {

    /* MM: Check for breakpoint.  This has to be done in fetch cycle,

       because of peripheria.

       MM1709: if we cannot access the memory entry, we could not set the

       breakpoint earlier, so just chech the breakpoint list.  */

    if (has_breakpoint (pc_phy) && !break_just_hit) {

      break_just_hit = 1;

      return 1; /* Breakpoint set. */

    }

    break_just_hit = 0;

  }

  instructions++;

  pc_phy &= ~0x03;

  /* Fetch instruction. */

  iqueue[0].insn_addr = pc;

  iqueue[0].insn = eval_insn (pc_phy, &breakpoint);

  /* update_pc will be called after execution */

  return 0;

}

/* This code actually updates the PC value.  */

static inline void update_pc ()

{

  delay_insn = next_delay_insn;

  pcprev = pc; /* Store value for later */

  pc = pcnext;

  pcnext = delay_insn ? pcdelay : pcnext + 4;

}

#if SIMPLE_EXECUTION

static inline

#endif

void analysis (struct iqueue_entry *current)

{

  if (config.cpu.dependstats) {

    /* Dynamic, dependency stats. */

    adddstats(icomplet[0].insn_index, current->insn_index, 1, check_depend());

    /* Dynamic, functional units stats. */

    addfstats(icomplet[0].func_unit, current->func_unit, 1, check_depend());

    /* Dynamic, single stats. */

    addsstats(current->insn_index, 1);

  }

  if (config.cpu.superscalar) {

    if ((current->func_unit == it_branch) || (current->func_unit == it_jump))

      storecycles += 0;

    if (current->func_unit == it_store)

      storecycles += 1;

    if (current->func_unit == it_load)

      loadcycles += 1;

#if 0        

    if ((icomplet[0].func_unit == it_load) && check_depend())

      loadcycles++;

#endif

    /* Pseudo multiple issue benchmark */

    if ((multissue[current->func_unit] < 1) || (check_depend())

     || (issued_per_cycle < 1)) {

      int i;

      for (i = 0; i < 20; i++)

        multissue[i] = 2;

      issued_per_cycle = 2;

      supercycles++;

      if (check_depend())

        hazardwait++;

      multissue[it_unknown] = 2;

      multissue[it_shift] = 2;

      multissue[it_compare] = 1;

      multissue[it_branch] = 1;

      multissue[it_jump] = 1;

      multissue[it_extend] = 2;

      multissue[it_nop] = 2;

      multissue[it_move] = 2;

      multissue[it_movimm] = 2;

      multissue[it_arith] = 2;

      multissue[it_store] = 2;

      multissue[it_load] = 2;

    }

    multissue[current->func_unit]--;

    issued_per_cycle--;

  }

  if (config.cpu.dependstats)

    /* Instruction waits in completition buffer until retired. */

    memcpy (&icomplet[0], current, sizeof (struct iqueue_entry));

  if (config.sim.history) {

    int i;

    /* History of execution */

    for (i = HISTEXEC_LEN - 1; i; i--)

      histexec[i] = histexec[i - 1];

    histexec[0] = icomplet[0].insn_addr;        /* add last insn */

  }

  if (config.sim.exe_log) dump_exe_log();

}

/* Store buffer analysis - stores are accumulated and commited when IO is idle */

static inline sbuf_store (int cyc) {

  int delta = cycles - sbuf_prev_cycles;

  sbuf_total_cyc += cyc;

  sbuf_prev_cycles = cycles;

  //printf (">STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Store buffer is full, take one out */

  if (sbuf_count >= config.cpu.sbuf_len) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  /* Put newest store in the buffer */

  sbuf_buf[sbuf_head] = cyc;

  sbuf_head = (sbuf_head + 1) % MAX_SBUF_LEN;

  sbuf_count++;

  //printf ("|STORE %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Store buffer analysis - previous stores should commit, before any load */

static inline sbuf_load () {

  int delta = cycles - sbuf_prev_cycles;

  sbuf_prev_cycles = cycles;

  //printf (">LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

  //printf ("|%i,%i\n", sbuf_total_cyc, sbuf_wait_cyc);

  /* Take stores from buffer, that occured meanwhile */

  while (sbuf_count && delta >= sbuf_buf[sbuf_tail]) {

    delta -= sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  if (sbuf_count)

    sbuf_buf[sbuf_tail] -= delta;

  /* Wait for all stores to complete */

  while (sbuf_count > 0) {

    sbuf_wait_cyc += sbuf_buf[sbuf_tail];

    mem_cycles += sbuf_buf[sbuf_tail];

    sbuf_prev_cycles += sbuf_buf[sbuf_tail];

    sbuf_tail = (sbuf_tail + 1) % MAX_SBUF_LEN;

    sbuf_count--;

  }

  //printf ("|LOAD  %i,%i,%i,%i,%i\n", delta, sbuf_count, sbuf_tail, sbuf_head, sbuf_buf[sbuf_tail], sbuf_buf[sbuf_head]);

}

/* Outputs dissasembled instruction */

void dump_exe_log ()

{

  unsigned long i = iqueue[0].insn_addr;

  if (i == 0xffffffff) return;

  if (config.sim.exe_log_start <= instructions && (config.sim.exe_log_end <= 0 || instructions <= config.sim.exe_log_end)) {

    if (config.sim.exe_log_marker && instructions % config.sim.exe_log_marker == 0) {

      fprintf (runtime.sim.fexe_log, "--------------------- %8i instruction ---------------------\n", instructions);

    }

    switch (config.sim.exe_log_type) {

    case EXE_LOG_HARDWARE:

      fprintf (runtime.sim.fexe_log, "\nEXECUTED(): %.8lx:  ", i);

      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i), evalsim_mem8(i + 1));

      fprintf (runtime.sim.fexe_log, "%.2x%.2x", evalsim_mem8(i + 2), evalsim_mem8(i + 3));

      for(i = 0; i < MAX_GPRS; i++) {

        if (i % 4 == 0)

          fprintf(runtime.sim.fexe_log, "\n");

        fprintf (runtime.sim.fexe_log, "GPR%2u: %.8lx  ", i, reg[i]);

      }

      fprintf (runtime.sim.fexe_log, "\n");

      fprintf (runtime.sim.fexe_log, "SR   : %.8lx  ", mfspr(SPR_SR));

      fprintf (runtime.sim.fexe_log, "EPCR0: %.8lx  ", mfspr(SPR_EPCR_BASE));

      fprintf (runtime.sim.fexe_log, "EEAR0: %.8lx  ", mfspr(SPR_EEAR_BASE));

      fprintf (runtime.sim.fexe_log, "ESR0 : %.8lx\n", mfspr(SPR_ESR_BASE));

      break;

    case EXE_LOG_SIMPLE:

    case EXE_LOG_SOFTWARE:

      {

        extern char *disassembled;

        disassemble_index (iqueue[0].insn, iqueue[0].insn_index);

        {

          struct label_entry *entry;

          entry = get_label(i);

          if (entry)

            fprintf (runtime.sim.fexe_log, "%s:\n", entry->name);

        }

        if (config.sim.exe_log_type == EXE_LOG_SOFTWARE) {

          int i;

          for (i = 0; i < num_op; i++)

            if (op[i + MAX_OPERANDS] & OPTYPE_DIS) {

              fprintf (runtime.sim.fexe_log, "EA =%08x ", op[i]);

            } else if ((op[i + MAX_OPERANDS] & OPTYPE_REG) && op[i]) {

              fprintf (runtime.sim.fexe_log, "r%-2i=%08x ", op[i], evalsim_reg32 (op[i]));

            } else

            fprintf (runtime.sim.fexe_log, "             ");

          for (; i < 3; i++)

            fprintf (runtime.sim.fexe_log, "             ");

        }

        fprintf (runtime.sim.fexe_log, "%.8lx ", i);

        fprintf (runtime.sim.fexe_log, "%s\n", disassembled);

      }

    }

  }

}

/* Dump registers - 'r' or 't' command */

void dumpreg()

{

  int i;

  char temp[100];

  dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4, 1, 0);

  generate_time_pretty (temp, cycles);

  printf(" (executed) [time %s, #%i]\n", temp, instructions);

  if (config.cpu.superscalar)

    printf ("Superscalar CYCLES: %u", supercycles);

  if (config.cpu.hazards)

    printf ("  HAZARDWAIT: %u\n", hazardwait);

  else

    if (config.cpu.superscalar)

      printf ("\n");

  dumpmemory(pc, pc + 4, 1, 0);

  printf(" (next insn) %s", (delay_insn?"(delay insn)":""));

  for(i = 0; i < MAX_GPRS; i++) {

    if (i % 4 == 0)

      printf("\n");

    printf("GPR%.2u: %.8lx  ", i, evalsim_reg32(i));

  }

  printf("flag: %u\n", flag);

}

/* Generated/built in decoding/executing function */

static inline void decode_execute (struct iqueue_entry *current);

/* Wrapper around real decode_execute function -- some statistics here only */

static inline void decode_execute_wrapper (struct iqueue_entry *current)

{

  breakpoint = 0;

  next_delay_insn = 0;

#ifndef HAS_EXECUTION

#error HAS_EXECUTION has to be defined in order to execute programs.

#endif

  if(config.debug.enabled && CheckDebugUnit(DebugInstructionFetch, pc_phy))

    breakpoint = 1;

  decode_execute (current);

#if SET_OV_FLAG

  /* Check for range exception */

  if (testsprbits (SPR_SR, SPR_SR_OVE) && testsprbits (SPR_SR, SPR_SR_OV))

    except_handle (EXCEPT_RANGE, mfspr(SPR_EEAR_BASE));

#endif

  if(breakpoint)

    except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));

}

/* Reset the CPU */

void cpu_reset()

{

  int i;

  cycles = 0;

  instructions = 0;

  supercycles = 0;

  loadcycles = 0;

  storecycles = 0;

  for (i = 0; i < MAX_GPRS; i++)

    set_reg32 (i, 0);

  memset(iqueue, 0, sizeof(iqueue));

  memset(icomplet, 0, sizeof(icomplet));

  sbuf_head = 0;

  sbuf_tail = 0;

  sbuf_count = 0;

  sbuf_prev_cycles = 0;

  /* Cpu configuration */

  mtspr(SPR_UPR, config.cpu.upr);

  setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver);

  setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev);

  mtspr(SPR_SR, config.cpu.sr);

  pcnext = 0x0; /* MM1409: All programs should start at reset vector entry!  */

  printf ("Starting at 0x%08x\n", pcnext);

  pc = pcnext;

  pc_phy = pc;

  pcnext += 4;

  debug(1, "reset ...\n");

  /* MM1409: All programs should set their stack pointer!  */

  except_handle(EXCEPT_RESET, 0);

}

/* Simulates one CPU clock cycle */

inline int cpu_clock ()

{

  if(fetch()) {

    printf ("Breakpoint hit.\n");

    cont_run = 0; /* memory breakpoint encountered */

    return 1;

  }

  decode_execute_wrapper (&iqueue[0]);

  update_pc();

  return 0;

}

/* If decoding cannot be found, call this function */

void l_invalid () {

  /* It would be hard to handle this case for statistics; we skip it

     since it should not occur anyway:

  IFF (config.cpu.dependstats) current->func_unit = it_unknown; */

  except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);

}

#if !SIMPLE_EXECUTION

/* Include decode_execute function */

#include "execgen.c"

#else /* SIMPLE_EXECUTION */

#define INSTRUCTION(name) void name ()

#include "insnset.c"

/* Implementation specific.

   Parses and returns operands. */

static void

eval_operands (unsigned long insn, int insn_index, int* breakpoint)

{

  struct insn_op_struct *opd = op_start[insn_index];

  unsigned long data = 0;

  int dis = 0;

  int no = 0;