OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [cpu/] [or32/] [insnset.c] - Blame information for rev 1782

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 706 markom 
/* execute.c -- Instruction specific functions.
2 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3 
                 2000-2002 Marko Mlinar, markom@opencores.org
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
INSTRUCTION (l_add) {
22 1350 nogj 
  orreg_t temp1, temp2, temp3;
23 
  int8_t temp4;
24 706 markom 
 
25 1350 nogj 
  temp2 = (orreg_t)PARAM2;
26 
  temp3 = (orreg_t)PARAM1;
27 1170 csanchez 
  temp1 = temp2 + temp3;
28 1342 nogj 
  SET_PARAM0(temp1);
29 706 markom 
  set_ov_flag (temp1);
30 
  if (ARITH_SET_FLAG) {
31 
    flag = temp1 == 0;
32 
    setsprbits(SPR_SR, SPR_SR_F, flag);
33 
  }
34 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
35 1170 csanchez 
          setsprbits(SPR_SR, SPR_SR_CY, 1);
36 
  else
37 
          setsprbits(SPR_SR, SPR_SR_CY, 0);
38 706 markom 
 
39 
  temp4 = temp1;
40 
  if (temp4 == temp1)
41 1244 hpanther 
    or1k_mstats.byteadd++;
42 706 markom 
}
43 1170 csanchez 
INSTRUCTION (l_addc) {
44 1350 nogj 
  orreg_t temp1, temp2, temp3;
45 
  int8_t temp4;
46 1170 csanchez 
 
47 1350 nogj 
  temp2 = (orreg_t)PARAM2;
48 
  temp3 = (orreg_t)PARAM1;
49 1170 csanchez 
  temp1 = temp2 + temp3 + getsprbits(SPR_SR, SPR_SR_CY);
50 1342 nogj 
  SET_PARAM0(temp1);
51 1170 csanchez 
  set_ov_flag (temp1);
52 
  if (ARITH_SET_FLAG) {
53 
    flag = temp1 == 0;
54 
    setsprbits(SPR_SR, SPR_SR_F, flag);
55 
  }
56 1350 nogj 
  if ((uorreg_t) temp1 < (uorreg_t) temp2)
57 1170 csanchez 
        setsprbits(SPR_SR, SPR_SR_CY, 1);
58 
  else
59 
        setsprbits(SPR_SR, SPR_SR_CY, 0);
60 
 
61 
  temp4 = temp1;
62 
  if (temp4 == temp1)
63 1244 hpanther 
    or1k_mstats.byteadd++;
64 1170 csanchez 
}
65 706 markom 
INSTRUCTION (l_sw) {
66 
  int old_cyc = 0;
67 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
68 1342 nogj 
  set_mem32(PARAM0, PARAM1, &breakpoint);
69 706 markom 
  if (config.cpu.sbuf_len) {
70 884 markom 
    int t = runtime.sim.mem_cycles;
71 
    runtime.sim.mem_cycles = old_cyc;
72 706 markom 
    sbuf_store (t - old_cyc);
73 
  }
74 
}
75 
INSTRUCTION (l_sb) {
76 
  int old_cyc = 0;
77 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
78 1342 nogj 
  set_mem8(PARAM0, PARAM1, &breakpoint);
79 706 markom 
  if (config.cpu.sbuf_len) {
80 884 markom 
    int t = runtime.sim.mem_cycles;
81 
    runtime.sim.mem_cycles = old_cyc;
82 706 markom 
    sbuf_store (t- old_cyc);
83 
  }
84 
}
85 
INSTRUCTION (l_sh) {
86 
  int old_cyc = 0;
87 1375 nogj 
  if (config.cpu.sbuf_len) old_cyc = runtime.sim.mem_cycles;
88 1342 nogj 
  set_mem16(PARAM0, PARAM1, &breakpoint);
89 706 markom 
  if (config.cpu.sbuf_len) {
90 884 markom 
    int t = runtime.sim.mem_cycles;
91 
    runtime.sim.mem_cycles = old_cyc;
92 706 markom 
    sbuf_store (t - old_cyc);
93 
  }
94 
}
95 
INSTRUCTION (l_lwz) {
96 1350 nogj 
  uint32_t val;
97 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
98 1342 nogj 
  val = eval_mem32(PARAM1, &breakpoint);
99 706 markom 
  /* If eval operand produced exception don't set anything */
100 1386 nogj 
  if (!except_pending)
101 1342 nogj 
    SET_PARAM0(val);
102 706 markom 
}
103 
INSTRUCTION (l_lbs) {
104 1350 nogj 
  int8_t val;
105 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
106 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
107 706 markom 
  /* If eval opreand produced exception don't set anything */
108 1386 nogj 
  if (!except_pending)
109 1342 nogj 
    SET_PARAM0(val);
110 706 markom 
}
111 
INSTRUCTION (l_lbz) {
112 1350 nogj 
  uint8_t val;
113 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
114 1342 nogj 
  val = eval_mem8(PARAM1, &breakpoint);
115 706 markom 
  /* If eval opreand produced exception don't set anything */
116 1386 nogj 
  if (!except_pending)
117 1342 nogj 
    SET_PARAM0(val);
118 706 markom 
}
119 
INSTRUCTION (l_lhs) {
120 1350 nogj 
  int16_t val;
121 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
122 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
123 706 markom 
  /* If eval opreand produced exception don't set anything */
124 1386 nogj 
  if (!except_pending)
125 1342 nogj 
    SET_PARAM0(val);
126 706 markom 
}
127 
INSTRUCTION (l_lhz) {
128 1350 nogj 
  uint16_t val;
129 706 markom 
  if (config.cpu.sbuf_len) sbuf_load ();
130 1342 nogj 
  val = eval_mem16(PARAM1, &breakpoint);
131 706 markom 
  /* If eval opreand produced exception don't set anything */
132 1386 nogj 
  if (!except_pending)
133 1342 nogj 
    SET_PARAM0(val);
134 706 markom 
}
135 
INSTRUCTION (l_movhi) {
136 1342 nogj 
  SET_PARAM0(PARAM1 << 16);
137 706 markom 
}
138 
INSTRUCTION (l_and) {
139 1350 nogj 
  uorreg_t temp1;
140 1342 nogj 
  temp1 = PARAM1 & PARAM2;
141 
  set_ov_flag (temp1);
142 
  SET_PARAM0(temp1);
143 706 markom 
  if (ARITH_SET_FLAG) {
144 
    flag = temp1 == 0;
145 
    setsprbits(SPR_SR, SPR_SR_F, flag);
146 
  }
147 
}
148 
INSTRUCTION (l_or) {
149 1350 nogj 
  uorreg_t temp1;
150 1342 nogj 
  temp1 = PARAM1 | PARAM2;
151 
  set_ov_flag (temp1);
152 
  SET_PARAM0(temp1);
153 706 markom 
}
154 
INSTRUCTION (l_xor) {
155 1350 nogj 
  uorreg_t temp1;
156 1342 nogj 
  temp1 = PARAM1 ^ PARAM2;
157 
  set_ov_flag (temp1);
158 
  SET_PARAM0(temp1);
159 706 markom 
}
160 
INSTRUCTION (l_sub) {
161 1350 nogj 
  orreg_t temp1;
162 
  temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
163 1342 nogj 
  set_ov_flag (temp1);
164 
  SET_PARAM0(temp1);
165 706 markom 
}
166 
/*int mcount = 0;*/
167 
INSTRUCTION (l_mul) {
168 1350 nogj 
  orreg_t temp1;
169 706 markom 
 
170 1350 nogj 
  temp1 = (orreg_t)PARAM1 * (orreg_t)PARAM2;
171 1342 nogj 
  set_ov_flag (temp1);
172 
  SET_PARAM0(temp1);
173 706 markom 
  /*if (!(mcount++ & 1023)) {
174 997 markom 
    PRINTF ("[%i]\n",mcount);
175 706 markom 
    }*/
176 
}
177 
INSTRUCTION (l_div) {
178 1350 nogj 
  orreg_t temp3, temp2, temp1;
179 706 markom 
 
180 1342 nogj 
  temp3 = PARAM2;
181 
  temp2 = PARAM1;
182 706 markom 
  if (temp3)
183 
    temp1 = temp2 / temp3;
184 
  else {
185 
    except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
186 
    return;
187 
  }
188 1342 nogj 
  set_ov_flag (temp1);
189 
  SET_PARAM0(temp1);
190 706 markom 
}
191 
INSTRUCTION (l_divu) {
192 1350 nogj 
  uorreg_t temp3, temp2, temp1;
193 706 markom 
 
194 1342 nogj 
  temp3 = PARAM2;
195 
  temp2 = PARAM1;
196 
  if (temp3)
197 
    temp1 = temp2 / temp3;
198 
  else {
199 
    except_handle(EXCEPT_ILLEGAL, iqueue[0].insn_addr);
200 
    return;
201 
  }
202 
  set_ov_flag (temp1);
203 
  SET_PARAM0(temp1);
204 884 markom 
  /* runtime.sim.cycles += 16; */
205 706 markom 
}
206 
INSTRUCTION (l_sll) {
207 1350 nogj 
  uorreg_t temp1;
208 1342 nogj 
 
209 
  temp1 = PARAM1 << PARAM2;
210 
  set_ov_flag (temp1);
211 
  SET_PARAM0(temp1);
212 884 markom 
  /* runtime.sim.cycles += 2; */
213 706 markom 
}
214 
INSTRUCTION (l_sra) {
215 1350 nogj 
  orreg_t temp1;
216 706 markom 
 
217 1350 nogj 
  temp1 = (orreg_t)PARAM1 >> PARAM2;
218 1342 nogj 
  set_ov_flag (temp1);
219 
  SET_PARAM0(temp1);
220 884 markom 
  /* runtime.sim.cycles += 2; */
221 706 markom 
}
222 
INSTRUCTION (l_srl) {
223 1350 nogj 
  uorreg_t temp1;
224 1342 nogj 
  temp1 = PARAM1 >> PARAM2;
225 
  set_ov_flag (temp1);
226 
  SET_PARAM0(temp1);
227 884 markom 
  /* runtime.sim.cycles += 2; */
228 706 markom 
}
229 
INSTRUCTION (l_bf) {
230 
  if (config.bpb.enabled) {
231 1342 nogj 
    int fwd = (PARAM0 >= pc) ? 1 : 0;
232 1244 hpanther 
    or1k_mstats.bf[flag][fwd]++;
233 713 markom 
    bpb_update(current->insn_addr, flag);
234 706 markom 
  }
235 
  if (flag) {
236 1350 nogj 
    pcdelay = pc + (orreg_t)PARAM0 * 4;
237 706 markom 
    btic_update(pcnext);
238 
    next_delay_insn = 1;
239 
  } else {
240 
    btic_update(pc);
241 
  }
242 
}
243 
INSTRUCTION (l_bnf) {
244 
  if (config.bpb.enabled) {
245 1342 nogj 
    int fwd = (PARAM0 >= pc) ? 1 : 0;
246 1244 hpanther 
    or1k_mstats.bnf[!flag][fwd]++;
247 713 markom 
    bpb_update(current->insn_addr, flag == 0);
248 706 markom 
  }
249 
  if (flag == 0) {
250 1350 nogj 
    pcdelay = pc + (orreg_t)PARAM0 * 4;
251 706 markom 
    btic_update(pcnext);
252 
    next_delay_insn = 1;
253 
  } else {
254 
    btic_update(pc);
255 
  }
256 
}
257 
INSTRUCTION (l_j) {
258 1350 nogj 
  pcdelay = pc + (orreg_t)PARAM0 * 4;
259 706 markom 
  next_delay_insn = 1;
260 
}
261 
INSTRUCTION (l_jal) {
262 1350 nogj 
  pcdelay = pc + (orreg_t)PARAM0 * 4;
263 706 markom 
 
264 1350 nogj 
  set_reg(LINK_REGNO, pc + 8);
265 706 markom 
  next_delay_insn = 1;
266 
  if (config.sim.profile) {
267 
    struct label_entry *tmp;
268 
    if (verify_memoryarea(pcdelay) && (tmp = get_label (pcdelay)))
269 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" %s\n",
270 1343 nogj 
               runtime.sim.cycles, pc + 8, pcdelay, tmp->name);
271 706 markom 
    else
272 1350 nogj 
      fprintf (runtime.sim.fprof, "+%08llX %"PRIxADDR" %"PRIxADDR" @%"PRIxADDR"\n",
273 1343 nogj 
               runtime.sim.cycles, pc + 8, pcdelay, pcdelay);
274 706 markom 
  }
275 
}
276 
INSTRUCTION (l_jalr) {
277 1342 nogj 
  pcdelay = PARAM0;
278 1350 nogj 
  set_reg(LINK_REGNO, pc + 8);
279 706 markom 
  next_delay_insn = 1;
280 
}
281 
INSTRUCTION (l_jr) {
282 1342 nogj 
  pcdelay = PARAM0;
283 706 markom 
  next_delay_insn = 1;
284 
  if (config.sim.profile)
285 1350 nogj 
    fprintf (runtime.sim.fprof, "-%08llX %"PRIxADDR"\n", runtime.sim.cycles,
286 
             pcdelay);
287 706 markom 
}
288 
INSTRUCTION (l_rfe) {
289 
  pcnext = mfspr(SPR_EPCR_BASE);
290 
  mtspr(SPR_SR, mfspr(SPR_ESR_BASE));
291 
}
292 
INSTRUCTION (l_nop) {
293 1350 nogj 
  oraddr_t stackaddr;
294 
  uint32_t k = PARAM0;
295 706 markom 
  switch (k) {
296 
    case NOP_NOP:
297 
      break;
298 
    case NOP_EXIT:
299 1350 nogj 
      PRINTF("exit(%"PRIdREG")\n", evalsim_reg (3));
300 1343 nogj 
      fprintf(stderr, "@reset : cycles %lld, insn #%lld\n",
301 
              runtime.sim.reset_cycles, runtime.cpu.reset_instructions);
302 
      fprintf(stderr, "@exit  : cycles %lld, insn #%lld\n", runtime.sim.cycles,
303 
              runtime.cpu.instructions);
304 
      fprintf(stderr, " diff  : cycles %lld, insn #%lld\n",
305 
              runtime.sim.cycles - runtime.sim.reset_cycles,
306 
              runtime.cpu.instructions - runtime.cpu.reset_instructions);
307 706 markom 
      if (config.debug.gdb_enabled)
308 
        set_stall_state (1);
309 
      else
310 884 markom 
        runtime.sim.cont_run = 0;
311 706 markom 
      break;
312 1319 phoenix 
    case NOP_CNT_RESET:
313 
      PRINTF("****************** counters reset ******************\n");
314 
      PRINTF("cycles %lld, insn #%lld\n", runtime.sim.cycles, runtime.cpu.instructions);
315 
      PRINTF("****************** counters reset ******************\n");
316 
      runtime.sim.reset_cycles = runtime.sim.cycles;
317 
      runtime.cpu.reset_instructions = runtime.cpu.instructions;
318 
      break;
319 706 markom 
    case NOP_PRINTF:
320 1350 nogj 
      stackaddr = evalsim_reg(4);
321 
      simprintf(stackaddr, evalsim_reg(3));
322 706 markom 
      debug(5, "simprintf %x\n", stackaddr);
323 
      break;
324 
    case NOP_REPORT:
325 1350 nogj 
      PRINTF("report(0x%"PRIdREG");\n", evalsim_reg(3));
326 706 markom 
    default:
327 
      if (k >= NOP_REPORT_FIRST && k <= NOP_REPORT_LAST)
328 1350 nogj 
      PRINTF("report %i (0x%"PRIxREG");\n", k - NOP_REPORT_FIRST,
329 
             evalsim_reg(3));
330 706 markom 
      break;
331 
  }
332 
}
333 
INSTRUCTION (l_sfeq) {
334 1342 nogj 
  flag = PARAM0 == PARAM1;
335 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
336 
}
337 
INSTRUCTION (l_sfne) {
338 1342 nogj 
  flag = PARAM0 != PARAM1;
339 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
340 
}
341 
INSTRUCTION (l_sfgts) {
342 1350 nogj 
  flag = (orreg_t)PARAM0 > (orreg_t)PARAM1;
343 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
344 
}
345 
INSTRUCTION (l_sfges) {
346 1350 nogj 
  flag = (orreg_t)PARAM0 >= (orreg_t)PARAM1;
347 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
348 
}
349 
INSTRUCTION (l_sflts) {
350 1350 nogj 
  flag = (orreg_t)PARAM0 < (orreg_t)PARAM1;
351 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
352 
}
353 
INSTRUCTION (l_sfles) {
354 1350 nogj 
  flag = (orreg_t)PARAM0 <= (orreg_t)PARAM1;
355 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
356 
}
357 
INSTRUCTION (l_sfgtu) {
358 1350 nogj 
  flag = PARAM0 > PARAM1;
359 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
360 
}
361 
INSTRUCTION (l_sfgeu) {
362 1350 nogj 
  flag = PARAM0 >= PARAM1;
363 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
364 
}
365 
INSTRUCTION (l_sfltu) {
366 1350 nogj 
  flag = PARAM0 < PARAM1;
367 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
368 
}
369 
INSTRUCTION (l_sfleu) {
370 1350 nogj 
  flag = PARAM0 <= PARAM1;
371 706 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
372 
}
373 
INSTRUCTION (l_extbs) {
374 1350 nogj 
  int8_t x;
375 1342 nogj 
  x = PARAM1;
376 1350 nogj 
  SET_PARAM0((orreg_t)x);
377 706 markom 
}
378 
INSTRUCTION (l_extbz) {
379 1350 nogj 
  uint8_t x;
380 1342 nogj 
  x = PARAM1;
381 1350 nogj 
  SET_PARAM0((uorreg_t)x);
382 706 markom 
}
383 
INSTRUCTION (l_exths) {
384 1350 nogj 
  int16_t x;
385 1342 nogj 
  x = PARAM1;
386 1350 nogj 
  SET_PARAM0((orreg_t)x);
387 706 markom 
}
388 
INSTRUCTION (l_exthz) {
389 1350 nogj 
  uint16_t x;
390 1342 nogj 
  x = PARAM1;
391 1350 nogj 
  SET_PARAM0((uorreg_t)x);
392 706 markom 
}
393 
INSTRUCTION (l_extws) {
394 1350 nogj 
  int32_t x;
395 1342 nogj 
  x = PARAM1;
396 1350 nogj 
  SET_PARAM0((orreg_t)x);
397 706 markom 
}
398 
INSTRUCTION (l_extwz) {
399 1350 nogj 
  uint32_t x;
400 1342 nogj 
  x = PARAM1;
401 1350 nogj 
  SET_PARAM0((uorreg_t)x);
402 706 markom 
}
403 
INSTRUCTION (l_mtspr) {
404 1350 nogj 
  uint16_t regno = PARAM0 + PARAM2;
405 
  uorreg_t value = PARAM1;
406 706 markom 
 
407 
  if (runtime.sim.fspr_log) {
408 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Write to SPR  : [%08"PRIx16"] <- [%08"PRIx32"]\n", regno, value);
409 706 markom 
  }
410 
 
411 
  if (mfspr(SPR_SR) & SPR_SR_SM)
412 
    mtspr(regno, value);
413 
  else {
414 997 markom 
    PRINTF("WARNING: trying to write SPR while SR[SUPV] is cleared.\n");
415 884 markom 
    runtime.sim.cont_run = 0;
416 706 markom 
  }
417 
}
418 
INSTRUCTION (l_mfspr) {
419 1350 nogj 
  uint16_t regno = PARAM1 + PARAM2;
420 
  uorreg_t value = mfspr(regno);
421 706 markom 
 
422 
  if (runtime.sim.fspr_log) {
423 1350 nogj 
    fprintf(runtime.sim.fspr_log, "Read from SPR : [%08"PRIx16"] -> [%08"PRIx32"]\n", regno, value);
424 706 markom 
  }
425 
 
426 
  if (mfspr(SPR_SR) & SPR_SR_SM)
427 1342 nogj 
    SET_PARAM0(value);
428 706 markom 
  else {
429 1342 nogj 
    SET_PARAM0(0);
430 997 markom 
    PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n");
431 884 markom 
    runtime.sim.cont_run = 0;
432 706 markom 
  }
433 
}
434 
INSTRUCTION (l_sys) {
435 
  except_handle(EXCEPT_SYSCALL, mfspr(SPR_EEAR_BASE));
436 
}
437 
INSTRUCTION (l_trap) {
438 
  /* TODO: some SR related code here! */
439 
  except_handle(EXCEPT_TRAP, mfspr(SPR_EEAR_BASE));
440 
}
441 
INSTRUCTION (l_mac) {
442 
  sprword lo, hi;
443 
  LONGEST l;
444 1350 nogj 
  orreg_t x, y;
445 
 
446 706 markom 
  lo = mfspr (SPR_MACLO);
447 
  hi = mfspr (SPR_MACHI);
448 1342 nogj 
  x = PARAM0;
449 
  y = PARAM1;
450 1350 nogj 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
451 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
452 
  l += (LONGEST) x * (LONGEST) y;
453 
 
454 
  /* This implementation is very fast - it needs only one cycle for mac.  */
455 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
456 
  hi = ((LONGEST)l) >> 32;
457 
  mtspr (SPR_MACLO, lo);
458 
  mtspr (SPR_MACHI, hi);
459 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
460 706 markom 
}
461 
INSTRUCTION (l_msb) {
462 
  sprword lo, hi;
463 
  LONGEST l;
464 1350 nogj 
  orreg_t x, y;
465 
 
466 706 markom 
  lo = mfspr (SPR_MACLO);
467 
  hi = mfspr (SPR_MACHI);
468 1342 nogj 
  x = PARAM0;
469 
  y = PARAM1;
470 1350 nogj 
 
471 
  PRINTF ("[%"PRIxREG",%"PRIxREG"]\t", x, y);
472 
 
473 706 markom 
  l = (ULONGEST)lo | ((LONGEST)hi << 32);
474 1342 nogj 
  l -= x * y;
475 706 markom 
 
476 
  /* This implementation is very fast - it needs only one cycle for msb.  */
477 
  lo = ((ULONGEST)l) & 0xFFFFFFFF;
478 
  hi = ((LONGEST)l) >> 32;
479 
  mtspr (SPR_MACLO, lo);
480 
  mtspr (SPR_MACHI, hi);
481 1308 phoenix 
  PRINTF ("(%08lx,%08lx)\n", hi, lo);
482 706 markom 
}
483 
INSTRUCTION (l_macrc) {
484 
  sprword lo, hi;
485 
  LONGEST l;
486 
  /* No need for synchronization here -- all MAC instructions are 1 cycle long.  */
487 
  lo =  mfspr (SPR_MACLO);
488 
  hi =  mfspr (SPR_MACHI);
489 
  l = (ULONGEST) lo | ((LONGEST)hi << 32);
490 
  l >>= 28;
491 997 markom 
  //PRINTF ("<%08x>\n", (unsigned long)l);
492 1350 nogj 
  SET_PARAM0((orreg_t)l);
493 706 markom 
  mtspr (SPR_MACLO, 0);
494 
  mtspr (SPR_MACHI, 0);
495 
}
496 
INSTRUCTION (l_cmov) {
497 1342 nogj 
  SET_PARAM0(flag ? PARAM1 : PARAM2);
498 706 markom 
}
499 1338 andreje 
INSTRUCTION (l_ff1) {
500 1342 nogj 
  SET_PARAM0(ffs(PARAM1));
501 1338 andreje 
}
502 720 markom 
/******* Floating point instructions *******/
503 
/* Single precision */
504 
INSTRUCTION (lf_add_s) {
505 1350 nogj 
  SET_PARAM0((float)PARAM1 + (float)PARAM2);
506 720 markom 
}
507 
INSTRUCTION (lf_div_s) {
508 1350 nogj 
  SET_PARAM0((float)PARAM1 / (float)PARAM2);
509 720 markom 
}
510 1303 phoenix 
INSTRUCTION (lf_ftoi_s) {
511 
//  set_operand32(0, freg[get_operand(1)], &breakpoint);
512 720 markom 
}
513 
INSTRUCTION (lf_itof_s) {
514 1303 phoenix 
//  freg[get_operand(0)] = eval_operand32(1, &breakpoint);
515 
}
516 720 markom 
INSTRUCTION (lf_madd_s) {
517 1350 nogj 
  SET_PARAM0((float)PARAM0 + (float)PARAM1 * (float)PARAM2);
518 720 markom 
}
519 
INSTRUCTION (lf_mul_s) {
520 1350 nogj 
  SET_PARAM0((float)PARAM1 * (float)PARAM2);
521 720 markom 
}
522 
INSTRUCTION (lf_rem_s) {
523 1342 nogj 
  float temp = (float)PARAM1 / (float)PARAM2;
524 1350 nogj 
  SET_PARAM0(temp - (uint32_t)temp);
525 720 markom 
}
526 
INSTRUCTION (lf_sfeq_s) {
527 1342 nogj 
  flag = (float)PARAM0 == (float)PARAM1;
528 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
529 
}
530 
INSTRUCTION (lf_sfge_s) {
531 1342 nogj 
  flag = (float)PARAM0 >= (float)PARAM1;
532 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
533 
}
534 
INSTRUCTION (lf_sfgt_s) {
535 1342 nogj 
  flag = (float)PARAM0 > (float)PARAM1;
536 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
537 
}
538 
INSTRUCTION (lf_sfle_s) {
539 1342 nogj 
  flag = (float)PARAM0 <= (float)PARAM1;
540 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
541 
}
542 
INSTRUCTION (lf_sflt_s) {
543 1342 nogj 
  flag = (float)PARAM0 < (float)PARAM1;
544 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
545 
}
546 
INSTRUCTION (lf_sfne_s) {
547 1342 nogj 
  flag = (float)PARAM0 != (float)PARAM1;
548 720 markom 
  setsprbits(SPR_SR, SPR_SR_F, flag);
549 
}
550 
INSTRUCTION (lf_sub_s) {
551 1350 nogj 
  SET_PARAM0((float)PARAM1 - (float)PARAM2);
552 720 markom 
}
553 
 
554 
/******* Custom instructions *******/
555 706 markom 
INSTRUCTION (l_cust1) {
556 713 markom 
  /*int destr = current->insn >> 21;
557 
    int src1r = current->insn >> 15;
558 
    int src2r = current->insn >> 9;*/
559 706 markom 
}
560 
INSTRUCTION (l_cust2) {
561 
}
562 
INSTRUCTION (l_cust3) {
563 
}
564 
INSTRUCTION (l_cust4) {
565 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.