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markom |
/* debug_unit.c -- Simulation of Or1k debug unit
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Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/*
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This is an architectural level simulation of the Or1k debug
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unit as described in OpenRISC 1000 System Architecture Manual,
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v. 0.1 on 22 April, 2001. This unit is described in Section 13.
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Every attempt has been made to be as accurate as possible with
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respect to the registers and the behavior. There are no known
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limitations at this time.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "debug_unit.h"
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#include "sim-config.h"
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#include "except.h"
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#include "arch.h"
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#include "abstract.h"
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#include "parse.h"
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#include "trace.h"
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#include "sprs.h"
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#include "../gdb.h"
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#include "../cpu/or1k/except.h"
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#include "opcode/or32.h"
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DebugUnit debug_unit;
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DevelopmentInterface development;
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typedef enum {
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false = 0,
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true = 1,
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} Boolean;
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static void ExecuteInducedInstruction(unsigned long);
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/* External STALL signal to debug interface */
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int cpu_stalled = false;
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int in_reset = false;
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/* An induced instruction has been written to the DIR register */
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static Boolean induced = false;
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static unsigned long induced_insn;
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/* A flag to indicate that we must perform an ic mmu cycle */
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static Boolean lookup_physical_address = false;
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/* Variables for implementing ExecuteInducedInstruction */
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extern unsigned long pc;
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extern unsigned long pcnext;
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extern unsigned long pcdelay;
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extern unsigned long pc_phy;
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extern int delay_insn;
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static void GetIQueueEntry(struct iqueue_entry*);
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static int CalculateWatchpoints(void);
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static int watchpoint[10];
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/* This function returns true if an induced instruction has
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been inserted into the instruction stream. It will remove
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that instruction and return the result. This function is
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called from the fetch() routine. */
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int OverrideFetch(unsigned long* insn)
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{
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int valid = induced;
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induced = false;
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if(valid)
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*insn = induced_insn;
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return valid;
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}
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void InduceImmediateInstruction(unsigned long insn)
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{
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induced = true;
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induced_insn = insn;
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if(in_reset)
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return;
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if(cpu_stalled)
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{
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ExecuteInducedInstruction(insn);
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induced_insn = 0;
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induced = false;
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}
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}
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void SetCPUStallState(int state)
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{
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if(debug_unit.DMR1.DXFW) /* If debugger disabled */
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state = false;
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if(state == cpu_stalled)
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return;
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if(state && induced)
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{
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ExecuteInducedInstruction(induced_insn);
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induced_insn = 0;
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induced = false;
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}
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cpu_stalled = state;
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}
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void ResetDebugUnit()
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{
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memset(&debug_unit,'\0',sizeof(DebugUnit));
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cpu_stalled = 0;
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}
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#ifdef DEBUGMOD_OFF
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#define CheckDebugUnit(x,y) 0
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#else
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inline int CheckDebugUnit(DebugUnitAction action,unsigned long udata)
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{
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int i;
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DCR_CT_Settings condition = DCR_CT_Disabled;
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long data = (long)udata;
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int match;
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269 |
markom |
if(DEBUG_ENABLED || in_reset)
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221 |
markom |
return 0;
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/* If we're single stepping, always stop */
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if(debug_unit.DMR1.ST && action == DebugInstructionFetch)
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return 1;
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switch(action)
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{
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case DebugInstructionFetch: condition = DCR_CT_InsnAddress; break;
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case DebugLoadAddress: condition = DCR_CT_LoadAddress; break;
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case DebugStoreAddress: condition = DCR_CT_StoreAddress; break;
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case DebugLoadData: condition = DCR_CT_LoadData; break;
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case DebugStoreData: condition = DCR_CT_StoreData; break;
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}
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for(i=0;i<8;i++)
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{
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if(debug_unit.DCR[i].DP == DCR_DP_Absent)
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continue;
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if(debug_unit.DCR[i].CT == condition)
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{
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if(debug_unit.DCR[i].SC == DCR_SC_Signed)
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{
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switch(debug_unit.DCR[i].CC)
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{
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case DCR_CC_Equal: match = data == (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = data < (int)debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = data <= (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = data > (int)debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = data >= (int)debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = data != (int)debug_unit.DVR[i]; break;
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default: match = 0; break;
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}
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}
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else
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{
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switch(debug_unit.DCR[i].CC)
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{
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case DCR_CC_Equal: match = udata == debug_unit.DVR[i]; break;
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case DCR_CC_LessThan: match = udata < debug_unit.DVR[i]; break;
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case DCR_CC_LessEqual: match = udata <= debug_unit.DVR[i]; break;
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case DCR_CC_GreaterThan: match = udata > debug_unit.DVR[i]; break;
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case DCR_CC_GreaterEqual: match = udata >= debug_unit.DVR[i]; break;
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case DCR_CC_NotEqual: match = udata != debug_unit.DVR[i]; break;
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default: match = 0; break;
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}
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}
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}
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match <<= i;
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debug_unit.DCR_hit &= ~match; /* Clear DCR compare if it has changed */
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debug_unit.DCR_hit |= match; /* Save the state of each DCR compare */
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}
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return CalculateWatchpoints();
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}
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#endif
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static int CalculateWatchpoints()
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{
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int spec[11];
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int breakpoint = 0;
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int i,bit;
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spec[0] = debug_unit.DMR1.CW0;
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spec[1] = debug_unit.DMR1.CW1;
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spec[2] = debug_unit.DMR1.CW2;
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spec[3] = debug_unit.DMR1.CW3;
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spec[4] = debug_unit.DMR1.CW4;
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spec[5] = debug_unit.DMR1.CW5;
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spec[6] = debug_unit.DMR1.CW6;
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spec[7] = debug_unit.DMR1.CW7;
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spec[8] = debug_unit.DMR1.CW8;
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spec[9] = debug_unit.DMR1.CW9;
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spec[10] = debug_unit.DMR1.CW10;
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for(i=0,bit=1;i<11;i++,bit<<=1)
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{
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int chain1,chain2;
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int match = 0;
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switch(i)
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{
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case 0:
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chain1 = chain2 = debug_unit.DCR_hit & 0x01;
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break;
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case 8:
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chain1 = debug_unit.DWCR[0].COUNT == debug_unit.DWCR[0].MATCH;
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chain2 = debug_unit.watchpoint & (1 << 7);
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break;
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case 9:
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chain1 = debug_unit.DWCR[1].COUNT == debug_unit.DWCR[1].MATCH;
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chain2 = debug_unit.watchpoint & (1 << 8);
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break;
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case 10:
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chain1 = debug_unit.DCR_hit & 0x100; /* External hit */
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chain2 = debug_unit.watchpoint & (1 << 9);
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break;
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| 242 |
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default:
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chain1 = debug_unit.DCR_hit & bit;
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| 244 |
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chain2 = debug_unit.watchpoint & (bit >> 1);
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| 245 |
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break;
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| 246 |
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}
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| 247 |
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| 248 |
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switch(spec[i])
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{
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| 250 |
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case 0: match = chain1; break;
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| 251 |
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case 1: match = chain1 && chain2; break;
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| 252 |
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case 2: match = chain1 || chain2; break;
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| 253 |
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default:
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| 254 |
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break;
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| 255 |
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}
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| 256 |
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| 257 |
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if(match & !(debug_unit.watchpoint & bit))
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| 258 |
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{
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| 259 |
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int counter = (debug_unit.DMR2.AWPC & bit) ? 1 : 0;
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| 260 |
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int enabled = counter ? debug_unit.DMR2.WCE1 : debug_unit.DMR2.WCE0;
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| 261 |
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| 262 |
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if(enabled)
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| 263 |
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debug_unit.DWCR[counter].COUNT++;
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| 264 |
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| 265 |
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if(debug_unit.DMR2.WGB & bit)
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| 266 |
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breakpoint = 1;
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| 267 |
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}
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| 268 |
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| 269 |
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debug_unit.watchpoint &= ~bit;
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| 270 |
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debug_unit.watchpoint |= bit;
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| 271 |
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}
|
| 272 |
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| 273 |
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return breakpoint;
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| 274 |
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}
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| 275 |
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| 276 |
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static void GetIQueueEntry(struct iqueue_entry* iq_entry)
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| 277 |
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{
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| 278 |
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iq_entry->insn = induced_insn;
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| 279 |
|
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iq_entry->insn_index = insn_decode(induced_insn);
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| 280 |
|
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iq_entry->insn_addr = pc_phy;
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| 281 |
|
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iq_entry->op[0] = 0;
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| 282 |
|
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iq_entry->op[MAX_OPERANDS] = OPTYPE_LAST;
|
| 283 |
|
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}
|
| 284 |
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|
| 285 |
|
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static void ExecuteInducedInstruction(unsigned long insn)
|
| 286 |
|
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{
|
| 287 |
|
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struct iqueue_entry iq_entry;
|
| 288 |
|
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unsigned long pc_saved = pc;
|
| 289 |
|
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unsigned long pcnext_saved = pcnext;
|
| 290 |
|
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unsigned long pcdelay_saved = pcdelay;
|
| 291 |
|
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unsigned long pc_phy_saved = pc_phy;
|
| 292 |
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|
| 293 |
|
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GetIQueueEntry(&iq_entry);
|
| 294 |
|
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decode_execute(&iq_entry);
|
| 295 |
|
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|
| 296 |
|
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pc = pc_saved;
|
| 297 |
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pcnext = pcnext_saved;
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| 298 |
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pcdelay = pcdelay_saved;
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| 299 |
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pc_phy = pc_phy_saved;
|
| 300 |
|
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}
|
| 301 |
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|
| 302 |
|
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static DebugScanChainIDs current_scan_chain = JTAG_CHAIN_GLOBAL;
|
| 303 |
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|
| 304 |
|
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int DebugGetRegister(unsigned int address,int32_t* data)
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| 305 |
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{
|
| 306 |
|
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int err;
|
| 307 |
|
|
#ifdef DEBUG_JTAG
|
| 308 |
|
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printf("Debug get register %x\n",address);
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| 309 |
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fflush(stdout);
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| 310 |
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#endif
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| 311 |
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switch(current_scan_chain)
|
| 312 |
|
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{
|
| 313 |
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case JTAG_CHAIN_DEBUG_UNIT:
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| 314 |
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err = GetDebugUnitRegister(address,data);
|
| 315 |
|
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break;
|
| 316 |
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case JTAG_CHAIN_TRACE:
|
| 317 |
|
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*data = 0; /* Scan chain not yet implemented */
|
| 318 |
|
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err = 0;
|
| 319 |
|
|
break;
|
| 320 |
|
|
case JTAG_CHAIN_DEVELOPMENT:
|
| 321 |
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err = GetDevelopmentInterfaceRegister(address,data);
|
| 322 |
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break;
|
| 323 |
|
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case JTAG_CHAIN_WISHBONE:
|
| 324 |
|
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err = GetWishboneMemory(address,data);
|
| 325 |
|
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break;
|
| 326 |
|
|
}
|
| 327 |
|
|
#ifdef DEBUG_JTAG
|
| 328 |
|
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printf("!get reg %x\n", *data);
|
| 329 |
|
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fflush(stdout);
|
| 330 |
|
|
#endif
|
| 331 |
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return err;
|
| 332 |
|
|
}
|
| 333 |
|
|
|
| 334 |
|
|
int DebugSetRegister(unsigned int address,int32_t data)
|
| 335 |
|
|
{
|
| 336 |
|
|
int err;
|
| 337 |
|
|
#ifdef DEBUG_JTAG
|
| 338 |
|
|
printf("Debug set register %x <- %x\n",address, data);
|
| 339 |
|
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fflush(stdout);
|
| 340 |
|
|
#endif
|
| 341 |
|
|
switch(current_scan_chain)
|
| 342 |
|
|
{
|
| 343 |
|
|
case JTAG_CHAIN_DEBUG_UNIT:
|
| 344 |
|
|
err = SetDebugUnitRegister(address,data);
|
| 345 |
|
|
break;
|
| 346 |
|
|
case JTAG_CHAIN_TRACE:
|
| 347 |
|
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
| 348 |
|
|
break;
|
| 349 |
|
|
case JTAG_CHAIN_DEVELOPMENT:
|
| 350 |
|
|
err = SetDevelopmentInterfaceRegister(address,data);
|
| 351 |
|
|
break;
|
| 352 |
|
|
case JTAG_CHAIN_WISHBONE:
|
| 353 |
|
|
err = SetWishboneMemory(address,data);
|
| 354 |
|
|
break;
|
| 355 |
|
|
}
|
| 356 |
|
|
#ifdef DEBUG_JTAG
|
| 357 |
|
|
printf("!set reg\n");
|
| 358 |
|
|
fflush(stdout);
|
| 359 |
|
|
#endif
|
| 360 |
|
|
return err;
|
| 361 |
|
|
}
|
| 362 |
|
|
|
| 363 |
|
|
int DebugSetChain(int chain)
|
| 364 |
|
|
{
|
| 365 |
|
|
#ifdef DEBUG_JTAG
|
| 366 |
|
|
printf("Debug set chain %x\n",chain);
|
| 367 |
|
|
fflush(stdout);
|
| 368 |
|
|
#endif
|
| 369 |
|
|
switch(chain)
|
| 370 |
|
|
{
|
| 371 |
|
|
case JTAG_CHAIN_DEBUG_UNIT:
|
| 372 |
|
|
case JTAG_CHAIN_TRACE:
|
| 373 |
|
|
case JTAG_CHAIN_DEVELOPMENT:
|
| 374 |
|
|
case JTAG_CHAIN_WISHBONE:
|
| 375 |
|
|
current_scan_chain = chain;
|
| 376 |
|
|
break;
|
| 377 |
|
|
default: /* All other chains not implemented */
|
| 378 |
|
|
return JTAG_PROXY_INVALID_CHAIN;
|
| 379 |
|
|
}
|
| 380 |
|
|
|
| 381 |
|
|
#ifdef DEBUG_JTAG
|
| 382 |
|
|
printf("!set chain\n");
|
| 383 |
|
|
fflush(stdout);
|
| 384 |
|
|
#endif
|
| 385 |
|
|
return 0;
|
| 386 |
|
|
}
|
| 387 |
|
|
|
| 388 |
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
| 389 |
|
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
| 390 |
|
|
to be working in a non standard environment, you may need to rewrite
|
| 391 |
|
|
this routine or the SET_REG32 macro. */
|
| 392 |
|
|
int SetDevelopmentInterfaceRegister(unsigned int address,uint32_t data)
|
| 393 |
|
|
{
|
| 394 |
|
|
int err = 0;
|
| 395 |
|
|
uint32_t value = data;
|
| 396 |
|
|
int old_value;
|
| 397 |
|
|
char *t_ptr = (char*)&development.RISCOP;
|
| 398 |
|
|
|
| 399 |
|
|
switch(address)
|
| 400 |
|
|
{
|
| 401 |
|
|
case DEVELOPINT_MODER:
|
| 402 |
|
|
SET_REG32(development.MODER,value);
|
| 403 |
|
|
break;
|
| 404 |
|
|
case DEVELOPINT_TSEL:
|
| 405 |
|
|
SET_REG32(development.TSEL,value);
|
| 406 |
|
|
break;
|
| 407 |
|
|
case DEVELOPINT_QSEL:
|
| 408 |
|
|
SET_REG32(development.QSEL,value);
|
| 409 |
|
|
break;
|
| 410 |
|
|
case DEVELOPINT_SSEL:
|
| 411 |
|
|
SET_REG32(development.SSEL,value);
|
| 412 |
|
|
break;
|
| 413 |
|
|
case DEVELOPINT_RISCOP:
|
| 414 |
|
|
old_value = development.RISCOP.RESET;
|
| 415 |
|
|
SET_REG32(development.RISCOP,value);
|
| 416 |
|
|
|
| 417 |
|
|
in_reset = development.RISCOP.RESET;
|
| 418 |
|
|
|
| 419 |
|
|
/* Reset the cpu on the negative edge of RESET */
|
| 420 |
|
|
if(old_value && !development.RISCOP.RESET)
|
| 421 |
|
|
{
|
| 422 |
|
|
uart_reset();
|
| 423 |
|
|
tick_reset();
|
| 424 |
|
|
pm_reset();
|
| 425 |
|
|
pic_reset();
|
| 426 |
|
|
reset(); /* Old or new mode */
|
| 427 |
|
|
}
|
| 428 |
|
|
|
| 429 |
|
|
SetCPUStallState(development.RISCOP.RISCSTALL);
|
| 430 |
|
|
break;
|
| 431 |
|
|
case DEVELOPINT_RECWP0:
|
| 432 |
|
|
case DEVELOPINT_RECWP1:
|
| 433 |
|
|
case DEVELOPINT_RECWP2:
|
| 434 |
|
|
case DEVELOPINT_RECWP3:
|
| 435 |
|
|
case DEVELOPINT_RECWP4:
|
| 436 |
|
|
case DEVELOPINT_RECWP5:
|
| 437 |
|
|
case DEVELOPINT_RECWP6:
|
| 438 |
|
|
case DEVELOPINT_RECWP7:
|
| 439 |
|
|
case DEVELOPINT_RECWP8:
|
| 440 |
|
|
case DEVELOPINT_RECWP9:
|
| 441 |
|
|
case DEVELOPINT_RECWP10:
|
| 442 |
|
|
SET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value);
|
| 443 |
|
|
break;
|
| 444 |
|
|
case DEVELOPINT_RECBP0:
|
| 445 |
|
|
SET_REG32(development.RECBP[0],value);
|
| 446 |
|
|
break;
|
| 447 |
|
|
default:
|
| 448 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 449 |
|
|
break;
|
| 450 |
|
|
}
|
| 451 |
|
|
return err;
|
| 452 |
|
|
}
|
| 453 |
|
|
|
| 454 |
|
|
int GetDevelopmentInterfaceRegister(unsigned int address,uint32_t *data)
|
| 455 |
|
|
{
|
| 456 |
|
|
int err = 0;
|
| 457 |
|
|
uint32_t value = 0;
|
| 458 |
|
|
|
| 459 |
|
|
switch(address)
|
| 460 |
|
|
{
|
| 461 |
|
|
case DEVELOPINT_MODER: GET_REG32(development.MODER,value); break;
|
| 462 |
|
|
case DEVELOPINT_TSEL: GET_REG32(development.TSEL,value); break;
|
| 463 |
|
|
case DEVELOPINT_QSEL: GET_REG32(development.QSEL,value); break;
|
| 464 |
|
|
case DEVELOPINT_SSEL: GET_REG32(development.SSEL,value); break;
|
| 465 |
|
|
case DEVELOPINT_RISCOP: GET_REG32(development.RISCOP,value); break;
|
| 466 |
|
|
case DEVELOPINT_RECWP0:
|
| 467 |
|
|
case DEVELOPINT_RECWP1:
|
| 468 |
|
|
case DEVELOPINT_RECWP2:
|
| 469 |
|
|
case DEVELOPINT_RECWP3:
|
| 470 |
|
|
case DEVELOPINT_RECWP4:
|
| 471 |
|
|
case DEVELOPINT_RECWP5:
|
| 472 |
|
|
case DEVELOPINT_RECWP6:
|
| 473 |
|
|
case DEVELOPINT_RECWP7:
|
| 474 |
|
|
case DEVELOPINT_RECWP8:
|
| 475 |
|
|
case DEVELOPINT_RECWP9:
|
| 476 |
|
|
case DEVELOPINT_RECWP10: GET_REG32(development.RECWP[address-DEVELOPINT_RECWP0],value); break;
|
| 477 |
|
|
case DEVELOPINT_RECBP0: GET_REG32(development.RECBP[0],value); break;
|
| 478 |
|
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
| 479 |
|
|
}
|
| 480 |
|
|
|
| 481 |
|
|
*data = value;
|
| 482 |
|
|
return err;
|
| 483 |
|
|
}
|
| 484 |
|
|
|
| 485 |
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
| 486 |
|
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
| 487 |
|
|
to be working in a non standard environment, you may need to rewrite
|
| 488 |
|
|
this routine or the SET_REG32 macro. */
|
| 489 |
|
|
int SetDebugUnitRegister(unsigned int address,uint32_t data)
|
| 490 |
|
|
{
|
| 491 |
|
|
int err = 0;
|
| 492 |
|
|
uint32_t value = data;
|
| 493 |
|
|
int old_value;
|
| 494 |
|
|
int group = address >> 11;
|
| 495 |
|
|
|
| 496 |
|
|
address &= 0x07FF;
|
| 497 |
|
|
|
| 498 |
|
|
/*****************************************************/
|
| 499 |
|
|
/* TEMPORARY!!!! */
|
| 500 |
|
|
/*****************************************************/
|
| 501 |
|
|
if(group == 6)
|
| 502 |
|
|
address -= 32;
|
| 503 |
|
|
|
| 504 |
|
|
if(group == 6)
|
| 505 |
|
|
{
|
| 506 |
|
|
switch(address)
|
| 507 |
|
|
{
|
| 508 |
|
|
case DEBUGINT_DVR0:
|
| 509 |
|
|
case DEBUGINT_DVR1:
|
| 510 |
|
|
case DEBUGINT_DVR2:
|
| 511 |
|
|
case DEBUGINT_DVR3:
|
| 512 |
|
|
case DEBUGINT_DVR4:
|
| 513 |
|
|
case DEBUGINT_DVR5:
|
| 514 |
|
|
case DEBUGINT_DVR6:
|
| 515 |
|
|
case DEBUGINT_DVR7:
|
| 516 |
|
|
printf("DVR %d set to 0x%08x\n",address-DEBUGINT_DVR0,value);
|
| 517 |
|
|
SET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value);
|
| 518 |
|
|
break;
|
| 519 |
|
|
case DEBUGINT_DCR0:
|
| 520 |
|
|
case DEBUGINT_DCR1:
|
| 521 |
|
|
case DEBUGINT_DCR2:
|
| 522 |
|
|
case DEBUGINT_DCR3:
|
| 523 |
|
|
case DEBUGINT_DCR4:
|
| 524 |
|
|
case DEBUGINT_DCR5:
|
| 525 |
|
|
case DEBUGINT_DCR6:
|
| 526 |
|
|
case DEBUGINT_DCR7:
|
| 527 |
|
|
printf("DCR %d set to 0x%08x\n",address-DEBUGINT_DCR0,value);
|
| 528 |
|
|
SET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value);
|
| 529 |
|
|
break;
|
| 530 |
|
|
case DEBUGINT_DMR1:
|
| 531 |
|
|
SET_REG32(debug_unit.DMR1,value);
|
| 532 |
|
|
break;
|
| 533 |
|
|
case DEBUGINT_DMR2:
|
| 534 |
|
|
SET_REG32(debug_unit.DMR2,value);
|
| 535 |
|
|
break;
|
| 536 |
|
|
case DEBUGINT_DWCR0:
|
| 537 |
|
|
SET_REG32(debug_unit.DWCR[0],value);
|
| 538 |
|
|
break;
|
| 539 |
|
|
case DEBUGINT_DWCR1:
|
| 540 |
|
|
SET_REG32(debug_unit.DWCR[1],value);
|
| 541 |
|
|
break;
|
| 542 |
|
|
case DEBUGINT_DSR:
|
| 543 |
|
|
SET_REG32(debug_unit.DSR,value);
|
| 544 |
|
|
break;
|
| 545 |
|
|
case DEBUGINT_DRR:
|
| 546 |
|
|
SET_REG32(debug_unit.DRR,value);
|
| 547 |
|
|
break;
|
| 548 |
|
|
case DEBUGINT_DIR:
|
| 549 |
|
|
InduceImmediateInstruction(value);
|
| 550 |
|
|
break;
|
| 551 |
|
|
default:
|
| 552 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 553 |
|
|
break;
|
| 554 |
|
|
}
|
| 555 |
|
|
}
|
| 556 |
|
|
else if(group == 0)
|
| 557 |
|
|
{
|
| 558 |
|
|
extern unsigned long reg[32];
|
| 559 |
|
|
|
| 560 |
|
|
if(!address)
|
| 561 |
|
|
err = JTAG_PROXY_ACCESS_EXCEPTION;
|
| 562 |
|
|
else if(address < 32)
|
| 563 |
|
|
{
|
| 564 |
|
|
/* Assume that a write to the PC implies
|
| 565 |
|
|
that the debugging software has recognized
|
| 566 |
|
|
the exception and wants to do something
|
| 567 |
|
|
else instead. */
|
| 568 |
|
|
|
| 569 |
378 |
markom |
if(address == SPR_NPC)
|
| 570 |
221 |
markom |
{
|
| 571 |
|
|
ClearPendingException();
|
| 572 |
|
|
ClearPreparedPCState();
|
| 573 |
|
|
}
|
| 574 |
|
|
mtspr(address,data);
|
| 575 |
|
|
}
|
| 576 |
|
|
else if(address >= 0x0400 && address < 0x0420)
|
| 577 |
|
|
reg[address - 0x0400] = data;
|
| 578 |
|
|
else if(address < 0x0600 || address >= 0x0620)
|
| 579 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 580 |
|
|
}
|
| 581 |
|
|
else
|
| 582 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 583 |
|
|
|
| 584 |
|
|
return err;
|
| 585 |
|
|
}
|
| 586 |
|
|
|
| 587 |
|
|
int GetDebugUnitRegister(unsigned int address,uint32_t *data)
|
| 588 |
|
|
{
|
| 589 |
|
|
int err = 0;
|
| 590 |
|
|
uint32_t value = 0;
|
| 591 |
|
|
int group = address >> 11;
|
| 592 |
|
|
|
| 593 |
|
|
address &= 0x07FF;
|
| 594 |
|
|
|
| 595 |
|
|
/*****************************************************/
|
| 596 |
|
|
/* TEMPORARY!!!! */
|
| 597 |
|
|
/*****************************************************/
|
| 598 |
|
|
if(group == 6)
|
| 599 |
|
|
address -= 32;
|
| 600 |
|
|
|
| 601 |
|
|
if(group == 6)
|
| 602 |
|
|
{
|
| 603 |
|
|
switch(address)
|
| 604 |
|
|
{
|
| 605 |
|
|
case DEBUGINT_DVR0:
|
| 606 |
|
|
case DEBUGINT_DVR1:
|
| 607 |
|
|
case DEBUGINT_DVR2:
|
| 608 |
|
|
case DEBUGINT_DVR3:
|
| 609 |
|
|
case DEBUGINT_DVR4:
|
| 610 |
|
|
case DEBUGINT_DVR5:
|
| 611 |
|
|
case DEBUGINT_DVR6:
|
| 612 |
|
|
case DEBUGINT_DVR7: GET_REG32(debug_unit.DVR[address-DEBUGINT_DVR0],value); break;
|
| 613 |
|
|
case DEBUGINT_DCR0:
|
| 614 |
|
|
case DEBUGINT_DCR1:
|
| 615 |
|
|
case DEBUGINT_DCR2:
|
| 616 |
|
|
case DEBUGINT_DCR3:
|
| 617 |
|
|
case DEBUGINT_DCR4:
|
| 618 |
|
|
case DEBUGINT_DCR5:
|
| 619 |
|
|
case DEBUGINT_DCR6:
|
| 620 |
|
|
case DEBUGINT_DCR7: GET_REG32(debug_unit.DCR[address-DEBUGINT_DCR0],value); break;
|
| 621 |
|
|
case DEBUGINT_DMR1: GET_REG32(debug_unit.DMR1,value); break;
|
| 622 |
|
|
case DEBUGINT_DMR2: GET_REG32(debug_unit.DMR2,value); break;
|
| 623 |
|
|
case DEBUGINT_DWCR0: GET_REG32(debug_unit.DWCR[0],value); break;
|
| 624 |
|
|
case DEBUGINT_DWCR1: GET_REG32(debug_unit.DWCR[1],value); break;
|
| 625 |
|
|
case DEBUGINT_DSR: GET_REG32(debug_unit.DSR,value); break;
|
| 626 |
|
|
case DEBUGINT_DRR: GET_REG32(debug_unit.DRR,value); break;
|
| 627 |
|
|
case DEBUGINT_DIR: err = JTAG_PROXY_ACCESS_EXCEPTION; break;
|
| 628 |
|
|
default: err = JTAG_PROXY_INVALID_ADDRESS; break;
|
| 629 |
|
|
}
|
| 630 |
|
|
}
|
| 631 |
|
|
else if(group == 0)
|
| 632 |
|
|
{
|
| 633 |
|
|
extern unsigned long reg[32];
|
| 634 |
|
|
|
| 635 |
|
|
if(address < 32)
|
| 636 |
|
|
value = mfspr(address);
|
| 637 |
|
|
else if(address >= 0x0400 && address < 0x0420)
|
| 638 |
|
|
value = reg[address - 0x400];
|
| 639 |
|
|
else if(address >= 0x0600 && address < 0x0620)
|
| 640 |
|
|
value = 0;
|
| 641 |
|
|
else
|
| 642 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 643 |
|
|
}
|
| 644 |
|
|
else
|
| 645 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 646 |
|
|
|
| 647 |
|
|
*data = value;
|
| 648 |
|
|
return err;
|
| 649 |
|
|
}
|
| 650 |
|
|
|
| 651 |
|
|
/* Nearly all compilers today store these bit fields as a packed structure
|
| 652 |
|
|
in network byte order (Big Endian). If you happen to be unlucky enough
|
| 653 |
|
|
to be working in a non standard environment, you may need to rewrite
|
| 654 |
|
|
this routine or the SET_REG32 macro. */
|
| 655 |
|
|
int SetWishboneMemory(unsigned int address,uint32_t data)
|
| 656 |
|
|
{
|
| 657 |
|
|
int err = 0;
|
| 658 |
|
|
uint32_t value = data;
|
| 659 |
|
|
int old_value;
|
| 660 |
|
|
int group = address >> 11;
|
| 661 |
|
|
|
| 662 |
|
|
address <<= 2;
|
| 663 |
|
|
|
| 664 |
|
|
if(!verify_memoryarea(address))
|
| 665 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 666 |
|
|
else
|
| 667 |
|
|
{
|
| 668 |
|
|
unsigned char t_data[4];
|
| 669 |
|
|
int *tmp = (int*)t_data;
|
| 670 |
|
|
extern char null_str[1]; /* From cpu/common/parse.c */
|
| 671 |
|
|
int i;
|
| 672 |
|
|
|
| 673 |
|
|
*tmp = htonl(data); /* We have already converted to host order */
|
| 674 |
|
|
|
| 675 |
|
|
setsim_mem8(address++, t_data[0]); /* Back to network byte order */
|
| 676 |
|
|
setsim_mem8(address++, t_data[1]);
|
| 677 |
|
|
setsim_mem8(address++, t_data[2]);
|
| 678 |
|
|
setsim_mem8(address++, t_data[3]);
|
| 679 |
|
|
}
|
| 680 |
|
|
return err;
|
| 681 |
|
|
}
|
| 682 |
|
|
|
| 683 |
|
|
int GetWishboneMemory(unsigned int address,uint32_t *data)
|
| 684 |
|
|
{
|
| 685 |
|
|
int err = 0;
|
| 686 |
|
|
uint32_t value = 0;
|
| 687 |
|
|
int group = address >> 11;
|
| 688 |
|
|
|
| 689 |
|
|
address <<= 2;
|
| 690 |
|
|
|
| 691 |
|
|
if(!verify_memoryarea(address))
|
| 692 |
|
|
err = JTAG_PROXY_INVALID_ADDRESS;
|
| 693 |
|
|
else
|
| 694 |
|
|
{
|
| 695 |
|
|
unsigned char t_data[4];
|
| 696 |
|
|
int *tmp = (int*)t_data;
|
| 697 |
|
|
int bp;
|
| 698 |
|
|
|
| 699 |
|
|
t_data[0] = evalsim_mem8(address++);
|
| 700 |
|
|
t_data[1] = evalsim_mem8(address++);
|
| 701 |
|
|
t_data[2] = evalsim_mem8(address++);
|
| 702 |
|
|
t_data[3] = evalsim_mem8(address++); /* Already in network byte order */
|
| 703 |
|
|
|
| 704 |
|
|
*data = ntohl(*tmp); /* But we assume it is in host order later */
|
| 705 |
|
|
}
|
| 706 |
|
|
return err;
|
| 707 |
|
|
}
|
| 708 |
|
|
|
| 709 |
|
|
/* DebugCheckException returns 1 if the exception should be ignored.
|
| 710 |
|
|
Currently, this is true only if the exception is a breakpoint
|
| 711 |
|
|
exception and debug_unit.DMR1.ST is set. Sorry, this is a quick
|
| 712 |
|
|
hack to disable processing of breakpoint exceptions on single
|
| 713 |
|
|
stepping. Just one of those historical accidents. Feel free
|
| 714 |
|
|
to rewrite the behavior. */
|
| 715 |
|
|
int DebugCheckException(int exception)
|
| 716 |
|
|
{
|
| 717 |
|
|
int result = 0;
|
| 718 |
|
|
|
| 719 |
|
|
switch(exception)
|
| 720 |
|
|
{
|
| 721 |
|
|
case EXCEPT_RESET: result = debug_unit.DRR.RSTE = debug_unit.DSR.RSTE; break;
|
| 722 |
|
|
case EXCEPT_BUSERR: result = debug_unit.DRR.BUSEE = debug_unit.DSR.BUSEE; break;
|
| 723 |
|
|
case EXCEPT_DPF: result = debug_unit.DRR.DPFE = debug_unit.DSR.DPFE; break;
|
| 724 |
|
|
case EXCEPT_IPF: result = debug_unit.DRR.IPFE = debug_unit.DSR.IPFE; break;
|
| 725 |
|
|
case EXCEPT_LPINT: result = debug_unit.DRR.LPINTE = debug_unit.DSR.LPINTE; break;
|
| 726 |
|
|
case EXCEPT_ALIGN: result = debug_unit.DRR.AE = debug_unit.DSR.AE; break;
|
| 727 |
|
|
case EXCEPT_ILLEGAL: result = debug_unit.DRR.IIE = debug_unit.DSR.IIE; break;
|
| 728 |
|
|
case EXCEPT_HPINT: result = debug_unit.DRR.HPINTE = debug_unit.DSR.HPINTE; break;
|
| 729 |
|
|
case EXCEPT_DTLBMISS: result = debug_unit.DRR.DME = debug_unit.DSR.DME; break;
|
| 730 |
|
|
case EXCEPT_ITLBMISS: result = debug_unit.DRR.IME = debug_unit.DSR.IME; break;
|
| 731 |
|
|
case EXCEPT_RANGE: result = debug_unit.DRR.RE = debug_unit.DSR.RE; break;
|
| 732 |
|
|
case EXCEPT_SYSCALL: result = debug_unit.DRR.SCE = debug_unit.DSR.SCE; break;
|
| 733 |
|
|
case EXCEPT_BREAK: result = debug_unit.DRR.BE = debug_unit.DSR.BE; break;
|
| 734 |
|
|
case EXCEPT_TRAP: result = debug_unit.DRR.TE = debug_unit.DSR.TE; break;
|
| 735 |
|
|
default:
|
| 736 |
|
|
break;
|
| 737 |
|
|
}
|
| 738 |
|
|
|
| 739 |
|
|
if(result)
|
| 740 |
|
|
SetCPUStallState(true);
|
| 741 |
|
|
|
| 742 |
|
|
return (debug_unit.DMR1.ST && exception == EXCEPT_BREAK);
|
| 743 |
|
|
}
|
