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/* debug_unit.h -- Simulation of Or1k debug unit

   Copyright (C) 2001 Chris Ziomkowski, chris@asics.ws

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Registers */

/* In general, little endian machines should pack bits from the LSB to

   the MSB, while big endian machines should do the reverse. The bit

   structures are declared in both orders, and we select which structure

   definition to use based on this macro assignment. If your architecture

   is special, you may have to redefine the algorithm defined in the

   SET_REG32 and GET_REG32 macros below. */

#if (defined (__arm__) && ! defined (__ARMEB__)) || defined (__i386__) || defined (__i860__) || defined (__ns32000__) || defined (__vax__)

#define LITTLE_ENDIAN_BIT_FILL

#else

#define BIG_ENDIAN_BIT_FILL

#endif

typedef enum {

  DCR_CT_Disabled = 0,

  DCR_CT_InsnAddress = 1,

  DCR_CT_LoadAddress = 2,

  DCR_CT_StoreAddress = 3,

  DCR_CT_LoadData = 4,

  DCR_CT_StoreData = 5,

  DCR_CT_Reserved1 = 6,

  DCR_CT_Reserved2 = 7,

} DCR_CT_Settings;

typedef enum {

  DCR_SC_Signed = 0,

  DCR_SC_Unsigned = 1,

} DCR_SC_Settings;

typedef enum {

  DCR_CC_Masked = 0,

  DCR_CC_Equal = 1,

  DCR_CC_LessThan = 2,

  DCR_CC_LessEqual = 3,

  DCR_CC_GreaterThan = 4,

  DCR_CC_GreaterEqual = 5,

  DCR_CC_NotEqual = 6,

  DCR_CC_Reserved = 7,

} DCR_CC_Settings;

typedef enum {

  DCR_DP_Absent = 0,

  DCR_DP_Present = 1,

} DCR_DP_Settings;

#ifdef LITTLE_ENDIAN_BIT_FILL

typedef struct {

  DCR_DP_Settings DP:1;

  DCR_CC_Settings CC:3;

  DCR_SC_Settings SC:1;

  DCR_CT_Settings CT:3;

  unsigned int reserved:24;

} DCRregister;

typedef struct {

  unsigned int CW0:2;

  unsigned int CW1:2;

  unsigned int CW2:2;

  unsigned int CW3:2;

  unsigned int CW4:2;

  unsigned int CW5:2;

  unsigned int CW6:2;

  unsigned int CW7:2;

  unsigned int CW8:2;

  unsigned int CW9:2;

  unsigned int CW10:2;

  unsigned int ST:1;

  unsigned int BT:1;

  unsigned int DXFW:1;

  unsigned int reserved:7;

} DMR1register;

typedef struct {

  unsigned int WCE0:1;

  unsigned int WCE1:1;

  unsigned int AWPC:11;

  unsigned int WGB:11;

  unsigned int reserved:8;

} DMR2register;

typedef struct {

  unsigned int COUNT:16;

  unsigned int MATCH:16;

} DWCRregister;

typedef struct {

  unsigned int RSTE:1;

  unsigned int BUSEE:1;

  unsigned int DPFE:1;

  unsigned int IPFE:1;

  unsigned int LPINTE:1;

  unsigned int AE:1;

  unsigned int IIE:1;

  unsigned int HPINTE:1;

  unsigned int DME:1;

  unsigned int IME:1;

  unsigned int RE:1;

  unsigned int SCE:1;

  unsigned int BE:1;

  unsigned int TE:1;

  unsigned int reserved:18;

} DSRregister;

typedef struct {

  unsigned int RSTE:1;

  unsigned int BUSEE:1;

  unsigned int DPFE:1;

  unsigned int IPFE:1;

  unsigned int LPINTE:1;

  unsigned int AE:1;

  unsigned int IIE:1;

  unsigned int HPINTE:1;

  unsigned int DME:1;

  unsigned int IME:1;

  unsigned int RE:1;

  unsigned int SCE:1;

  unsigned int BE:1;

  unsigned int TE:1;

  unsigned int reserved:18;

} DRRregister;

typedef struct {

  unsigned int CONTIN:1;

  unsigned int ENABLE:1;

  unsigned int RECSELDEPEND:1;

  unsigned int reserved:29;

} MODERregister;

typedef struct {

  unsigned int WPTRIG:11;

  unsigned int WPTRIGVALID:1;

  unsigned int BPTRIG:1;

  unsigned int BPTRIGVALID:1;

  unsigned int reserved2:2;

  unsigned int LSSTRIG:4;

  unsigned int LSSTRIGVALID:1;

  unsigned int ISTRIG:4;

  unsigned int ISTRIGVALID:1;

  unsigned int reserved1:4;

  unsigned int TRIGOP:2;

} TSELregister;

typedef struct {

  unsigned int WPQUALIF:11;

  unsigned int WPQUALIFVALID:1;

  unsigned int BPQUALIF:1;

  unsigned int BPQUALIFVALID:1;

  unsigned int reserved2:2;

  unsigned int LSSQUALIF:4;

  unsigned int LSSQUALIFVALID:1;

  unsigned int ISTQUALIF:4;

  unsigned int ISTQUALIFVALID:1;

  unsigned int reserved1:4;

  unsigned int QUALIFOP:2;

} QSELregister;

typedef struct {

  unsigned int WPSTOP:11;

  unsigned int WPSTOPVALID:1;

  unsigned int BPSTOP:1;

  unsigned int BPSTOPVALID:1;

  unsigned int reserved2:2;

  unsigned int LSSSTOP:4;

  unsigned int LSSSTOPVALID:1;

  unsigned int ISTSTOP:4;

  unsigned int ISTSTOPVALID:1;

  unsigned int reserved1:4;

  unsigned int STOPOP:2;

} SSELregister;

typedef struct {

  unsigned int RISCSTALL:1;

  volatile unsigned int RESET:1;

  unsigned int reserved:30;

} RISCOPregister;

typedef struct {

  unsigned int RECPC:1;

  unsigned int RECLSEA:1;

  unsigned int RECLDATA:1;

  unsigned int RECSDATA:1;

  unsigned int RECREADSPR:1;

  unsigned int RECWRITESPR:1;

  unsigned int RECINSTR:1;

  unsigned int reserved:25;

} RECWPregister;

typedef struct {

  unsigned int RECPC:1;

  unsigned int RECLSEA:1;

  unsigned int RECLDATA:1;

  unsigned int RECSDATA:1;

  unsigned int RECREADSPR:1;

  unsigned int RECWRITESPR:1;

  unsigned int RECINSTR:1;

  unsigned int reserved:25;

} RECBPregister;

#else /* BIG_ENDIAN_BIT_FILL */

typedef struct {

  unsigned int reserved:24;

  DCR_CT_Settings CT:3;

  DCR_SC_Settings SC:1;

  DCR_CC_Settings CC:3;

  DCR_DP_Settings DP:1;

} DCRregister;

typedef struct {

  unsigned int reserved:7;

  unsigned int DXFW:1;

  unsigned int BT:1;

  unsigned int ST:1;

  unsigned int CW10:2;

  unsigned int CW9:2;

  unsigned int CW8:2;

  unsigned int CW7:2;

  unsigned int CW6:2;

  unsigned int CW5:2;

  unsigned int CW4:2;

  unsigned int CW3:2;

  unsigned int CW2:2;

  unsigned int CW1:2;

  unsigned int CW0:2;

} DMR1register;

typedef struct {

  unsigned int reserved:8;

  unsigned int WGB:11;

  unsigned int AWPC:11;

  unsigned int WCE1:1;

  unsigned int WCE0:1;

} DMR2register;

typedef struct {

  unsigned int MATCH:16;

  unsigned int COUNT:16;

} DWCRregister;

typedef struct {

  unsigned int reserved:18;

  unsigned int TE:1;

  unsigned int BE:1;

  unsigned int SCE:1;

  unsigned int RE:1;

  unsigned int IME:1;

  unsigned int DME:1;

  unsigned int HPINTE:1;

  unsigned int IIE:1;

  unsigned int AE:1;

  unsigned int LPINTE:1;

  unsigned int IPFE:1;

  unsigned int DPFE:1;

  unsigned int BUSEE:1;

  unsigned int RSTE:1;

} DSRregister;

typedef struct {

  unsigned int reserved:18;

  unsigned int TE:1;

  unsigned int BE:1;

  unsigned int SCE:1;

  unsigned int RE:1;

  unsigned int IME:1;

  unsigned int DME:1;

  unsigned int HPINTE:1;

  unsigned int IIE:1;

  unsigned int AE:1;

  unsigned int LPINTE:1;

  unsigned int IPFE:1;

  unsigned int DPFE:1;

  unsigned int BUSEE:1;

  unsigned int RSTE:1;

} DRRregister;

typedef struct {

  unsigned int reserved:29;

  unsigned int RECSELDEPEND:1;

  unsigned int ENABLE:1;

  unsigned int CONTIN:1;

} MODERregister;

typedef struct {

  unsigned int TRIGOP:2;

  unsigned int reserved1:4;

  unsigned int ISTRIGVALID:1;

  unsigned int ISTRIG:4;

  unsigned int LSSTRIGVALID:1;

  unsigned int LSSTRIG:4;

  unsigned int reserved2:2;

  unsigned int BPTRIGVALID:1;

  unsigned int BPTRIG:1;

  unsigned int WPTRIGVALID:1;

  unsigned int WPTRIG:11;

} TSELregister;

typedef struct {

  unsigned int QUALIFOP:2;

  unsigned int reserved1:4;

  unsigned int ISTQUALIFVALID:1;

  unsigned int ISTQUALIF:4;

  unsigned int LSSQUALIFVALID:1;

  unsigned int LSSQUALIF:4;

  unsigned int reserved2:2;

  unsigned int BPQUALIFVALID:1;

  unsigned int BPQUALIF:1;

  unsigned int WPQUALIFVALID:1;

  unsigned int WPQUALIF:11;

} QSELregister;

typedef struct {

  unsigned int STOPOP:2;

  unsigned int reserved1:4;

  unsigned int ISTSTOPVALID:1;

  unsigned int ISTSTOP:4;

  unsigned int LSSSTOPVALID:1;

  unsigned int LSSSTOP:4;

  unsigned int reserved2:2;

  unsigned int BPSTOPVALID:1;

  unsigned int BPSTOP:1;

  unsigned int WPSTOPVALID:1;

  unsigned int WPSTOP:11;

} SSELregister;

typedef struct {

  unsigned int reserved:30;

  unsigned int RESET:1;

  unsigned int RISCSTALL:1;

} RISCOPregister;

typedef struct {

  unsigned int reserved:25;

  unsigned int RECINSTR:1;

  unsigned int RECWRITESPR:1;

  unsigned int RECREADSPR:1;

  unsigned int RECSDATA:1;

  unsigned int RECLDATA:1;

  unsigned int RECLSEA:1;

  unsigned int RECPC:1;

} RECWPregister;

typedef struct {

  unsigned int reserved:25;

  unsigned int RECINSTR:1;

  unsigned int RECWRITESPR:1;

  unsigned int RECREADSPR:1;

  unsigned int RECSDATA:1;

  unsigned int RECLDATA:1;

  unsigned int RECLSEA:1;

  unsigned int RECPC:1;

} RECBPregister;

#endif /* LITTLE_ENDIAN_BIT_FILL */

typedef struct {

  unsigned int DVR[8];

  DCRregister DCR[8];

  unsigned int DCR_hit;

  unsigned int watchpoint;

  DMR1register DMR1;

  DMR2register DMR2;

  DWCRregister DWCR[2];

  DSRregister DSR;

  DRRregister DRR;

  unsigned int DIR;

} DebugUnit;

typedef enum {

  DebugInstructionFetch = 1,

  DebugLoadAddress = 2,

  DebugStoreAddress = 3,

  DebugLoadData = 4,

  DebugStoreData = 5,

} DebugUnitAction;

extern DebugUnit debug_unit;

void InitializeDebugUnit(void);

void InduceImmediateInstruction(unsigned long);

void SetCPUStallState(int state);

typedef enum {

  JTAG_CHAIN_GLOBAL = 0,

  JTAG_CHAIN_DEBUG_UNIT = 1,

  JTAG_CHAIN_TEST = 2,

  JTAG_CHAIN_TRACE = 3,

  JTAG_CHAIN_DEVELOPMENT = 4,

  JTAG_CHAIN_WISHBONE = 5,

  JTAG_CHAIN_BLOCK1 = 6,

  JTAG_CHAIN_BLOCK2 = 7,

  JTAG_CHAIN_OPTIONAL0 = 8,

  JTAG_CHAIN_OPTIONAL1 = 9,

  JTAG_CHAIN_OPTIONAL2 = 10,

  JTAG_CHAIN_OPTIONAL3 = 11,

  JTAG_CHAIN_OPTIONAL4 = 12,

  JTAG_CHAIN_OPTIONAL5 = 13,

  JTAG_CHAIN_OPTIONAL6 = 14,

  JTAG_CHAIN_OPTIONAL7 = 15,

} DebugScanChainIDs;

typedef struct {

  MODERregister  MODER;

  TSELregister   TSEL;

  QSELregister   QSEL;

  SSELregister   SSEL;

  RISCOPregister RISCOP;

  RECWPregister  RECWP[11];

  RECBPregister  RECBP[1];

} DevelopmentInterface;

typedef enum {

  DEVELOPINT_MODER = 0,

  DEVELOPINT_TSEL = 1,

  DEVELOPINT_QSEL = 2,

  DEVELOPINT_SSEL = 3,

  DEVELOPINT_RISCOP = 4,

  DEVELOPINT_RECWP0 = 16,

  DEVELOPINT_RECWP1 = 17,

  DEVELOPINT_RECWP2 = 18,

  DEVELOPINT_RECWP3 = 19,

  DEVELOPINT_RECWP4 = 20,

  DEVELOPINT_RECWP5 = 21,

  DEVELOPINT_RECWP6 = 22,

  DEVELOPINT_RECWP7 = 23,

  DEVELOPINT_RECWP8 = 24,

  DEVELOPINT_RECWP9 = 25,

  DEVELOPINT_RECWP10 = 26,

  DEVELOPINT_RECBP0 = 27,

} DevelopmentInterfaceAddressSpace;

typedef enum {

  DEBUGINT_DVR0 = 0,

  DEBUGINT_DVR1 = 1,

  DEBUGINT_DVR2 = 2,

  DEBUGINT_DVR3 = 3,

  DEBUGINT_DVR4 = 4,

  DEBUGINT_DVR5 = 5,

  DEBUGINT_DVR6 = 6,

  DEBUGINT_DVR7 = 7,

  DEBUGINT_DCR0 = 8,

  DEBUGINT_DCR1 = 9,

  DEBUGINT_DCR2 = 10,

  DEBUGINT_DCR3 = 11,

  DEBUGINT_DCR4 = 12,

  DEBUGINT_DCR5 = 13,

  DEBUGINT_DCR6 = 14,

  DEBUGINT_DCR7 = 15,

  DEBUGINT_DMR1 = 16,

  DEBUGINT_DMR2 = 17,

  DEBUGINT_DWCR0 = 18,

  DEBUGINT_DWCR1 = 19,

  DEBUGINT_DSR = 20,

  DEBUGINT_DRR = 21,

  DEBUGINT_DIR = 22,

} DebugInterfaceAddressSpace;

/* This assumes a pointer to a 32 bit aligned bit field has

   been passed and that the compiler aligns bit fields on

   32 bit boundaries in big endian order. If either one of

   these two conditions are not true for your architecture

   you may need to adjust this macro. */

#define SET_REG32(x,y)  *((uint32_t*)&x) = (uint32_t)y

#define GET_REG32(x,y)  y = *((uint32_t*)&x)

#ifdef DEBUGMOD_OFF

#define CheckDebugUnit(x,y) 0

#endif