OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [pic/] [pic.c] - Blame information for rev 611

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 102 lampret
/* pic.c -- Simulation of OpenRISC 1000 programmable interrupt controller
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* This is functional simulation of OpenRISC 1000 architectural
21
   programmable interrupt controller.
22
*/
23
 
24
#include <stdlib.h>
25
#include <stdio.h>
26
#include <string.h>
27
 
28
#include "pic.h"
29
#include "spr_defs.h"
30
#include "except.h"
31 167 markom
#include "sprs.h"
32 102 lampret
 
33
extern int cont_run;
34
 
35
/* Reset. It initializes PIC registers. */
36
void pic_reset()
37
{
38 409 markom
  printf("Resetting PIC.\n");
39
  mtspr(SPR_PICMR, 0);
40
  mtspr(SPR_PICPR, 0);
41
  mtspr(SPR_PICSR, 0);
42 102 lampret
}
43
 
44
/* Simulation hook. Must be called every clock cycle to simulate PIC
45
   It does internal functional PIC simulation. */
46 261 markom
inline void pic_clock()
47 102 lampret
{
48 138 markom
  unsigned long picsr;
49 188 chris
  unsigned long sr;
50
 
51 561 simons
  /* From Sections 16.3 & 16.4, bits 0 & 1 are reserved */
52
  picsr = mfspr(SPR_PICSR);
53 188 chris
  sr = mfspr(SPR_SR);
54
 
55 600 simons
  /* Don't do anything if interrupts not currently enabled or
56
     higher priority exception was allready reported */
57
  if(((sr & SPR_SR_IEE) != SPR_SR_IEE) || pending.valid)
58 188 chris
    return;
59 557 markom
 
60 600 simons
  if(picsr)
61 611 simons
    except_handle(EXCEPT_INT, mfspr(SPR_EEAR_BASE));
62 102 lampret
}
63
 
64
/* Asserts interrupt to the PIC. */
65
void report_interrupt(int line)
66
{
67 409 markom
  setsprbits(SPR_PMR, SPR_PMR_DME, 0); /* Disable doze mode */
68
  setsprbits(SPR_PMR, SPR_PMR_SME, 0); /* Disable sleep mode */
69 102 lampret
 
70 409 markom
  debug(4, "Asserting interrupt %d.\n", line);
71
 
72
  if (getsprbit(SPR_PICMR, line) || line < 2)
73
  setsprbit(SPR_PICSR, line, 1);
74 102 lampret
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.