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lampret |
This directory includes some test case programs that should be used to verify correct operation
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of the or1ksim, OR32 GCC and OR32 GNU Binutils.
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All programs should be built inside their directories (ie. dhrystone should be built
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inside testbench/dhrystone). You need to have all GNU OR32 tools installed and in path.
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All makefiles assume or32-rtems target.
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!!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in
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cpu/or1k/except.h !!!
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Dhrystone 2.1: a benchmark modified to use simulator's timing facility. It should finish with exit(0).
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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running simulation:
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# ./sim testbench/dhrystone/dhry.or32
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(sim) run 1000000 hush
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MTSPR(0x1234, 20070);
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MTSPR(0x1234, 20013);
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MTSPR(0x1234, 7);
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MTSPR(0x1234, 30010);
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MTSPR(0x1234, 30010);
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MTSPR(0x1234, 8);
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MTSPR(0x1234, 20020);
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MTSPR(0x1234, 9);
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syscall exit(0)
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(sim)
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stdout.txt should read like this:
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Execution starts, 20 runs through Dhrystone
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Begin Time = 549
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End Time = 22701
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OR1K at 200 MHz
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Microseconds for one run through Dhrystone: 110 us / 20 runs
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Dhrystones per Second: 181
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test1: a test for "all" instructions and their combinations. If everything is ok, RESULT == 0xdeadead.
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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# ./sim testbench/test1/test1.or32
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(sim) run 100000000 hush
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MTSPR(0x1234, ffffffda);
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MTSPR(0x1234, ffffffc5);
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MTSPR(0x1234, 6805);
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MTSPR(0x1234, ffff97f9);
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MTSPR(0x1234, ffff97f9);
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MTSPR(0x1234, 7a77952e);
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MTSPR(0x1234, 81e5e000);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, 1);
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MTSPR(0x1234, d7c);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, 74);
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MTSPR(0x1234, ffffffff);
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MTSPR(0x1234, d7a);
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MTSPR(0x1234, d7a);
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MTSPR(0x1234, deaddead);
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syscall exit(0)
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(sim)
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Standard output:
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RESULT: deaddead
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compress: UNIX compressed modified not to use libc calls. Should finish with exit(0).
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Simulation:
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./sim testbench/compress/mycompress.or32
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(sim) run 100000000 hush
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Interrupt reported.
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Interrupt reported.
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syscall exit(0)
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(sim)
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Standard output:
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main: bytes_out 3... hsize 5003
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main: hshift 4...
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main: bytes_out 3...
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main: hsize_reg 5003...
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main: before compress 1...
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main: compressing 1...
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main: compressing 2...
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main: compressing 3...
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main: compressing 997...
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main: compressing 998...
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main: compressing 999...
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main: output...
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main: end...
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