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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [basic.S] - Blame information for rev 432

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Line No. Rev Author Line
1 432 markom 
/* Basic instruction set test */
2 
#include "spr_defs.h"
3 
 
4 
#define MEM_RAM 0x40000000
5 
 
6 
        .section .except
7 
        .org 0x100
8 
_reset:
9 
        l.nop
10 
        l.movhi r1,hi(_regs)
11 
        l.ori   r1,r1,lo(_regs)
12 
        l.jr    r1
13 
        l.nop
14 
 
15 
  .section .text
16 
_regs:
17 
        l.addi  r1,r0,0x1
18 
        l.addi  r2,r1,0x2
19 
        l.addi  r3,r2,0x4
20 
        l.addi  r4,r3,0x8
21 
        l.addi  r5,r4,0x10
22 
        l.addi  r6,r5,0x20
23 
        l.addi  r7,r6,0x40
24 
        l.addi  r8,r7,0x80
25 
        l.addi  r9,r8,0x100
26 
        l.addi  r10,r9,0x200
27 
        l.addi  r11,r10,0x400
28 
        l.addi  r12,r11,0x800
29 
        l.addi  r13,r12,0x1000
30 
        l.addi  r14,r13,0x2000
31 
        l.addi  r15,r14,0x4000
32 
        l.addi  r16,r15,0x8000
33 
 
34 
        l.sub   r31,r0,r1
35 
        l.sub   r30,r31,r2
36 
        l.sub   r29,r30,r3
37 
        l.sub   r28,r29,r4
38 
        l.sub   r27,r28,r5
39 
        l.sub   r26,r27,r6
40 
        l.sub   r25,r26,r7
41 
        l.sub   r24,r25,r8
42 
        l.sub   r23,r24,r9
43 
        l.sub   r22,r23,r10
44 
        l.sub   r21,r22,r11
45 
        l.sub   r20,r21,r12
46 
        l.sub   r19,r20,r13
47 
        l.sub   r18,r19,r14
48 
        l.sub   r17,r18,r15
49 
        l.sub   r16,r17,r16
50 
 
51 
        l.mtspr r0,r16,0x1234   /* Should be 0xffff0012 */
52 
 
53 
        l.movhi r31, hi(MEM_RAM)
54 
        l.ori  r31,r31, lo(MEM_RAM)
55 
        l.sw    0(r31),r16
56 
 
57 
_mem:   l.movhi r3,0x1234
58 
        l.ori   r3,r3,0x5678
59 
 
60 
        l.sw    4(r31),r3
61 
 
62 
        l.lbz   r4,4(r31)
63 
        l.add   r8,r8,r4
64 
        l.sb    11(r31),r4
65 
        l.lbz   r4,5(r31)
66 
        l.add   r8,r8,r4
67 
        l.sb    10(r31),r4
68 
        l.lbz   r4,6(r31)
69 
        l.add   r8,r8,r4
70 
        l.sb    9(r31),r4
71 
        l.lbz   r4,7(r31)
72 
        l.add   r8,r8,r4
73 
        l.sb    8(r31),r4
74 
 
75 
        l.lbs   r4,8(r31)
76 
        l.add   r8,r8,r4
77 
        l.sb    7(r31),r4
78 
        l.lbs   r4,9(r31)
79 
        l.add   r8,r8,r4
80 
        l.sb    6(r31),r4
81 
        l.lbs   r4,10(r31)
82 
        l.add   r8,r8,r4
83 
        l.sb    5(r31),r4
84 
        l.lbs   r4,11(r31)
85 
        l.add   r8,r8,r4
86 
        l.sb    4(r31),r4
87 
 
88 
        l.lhz   r4,4(r31)
89 
        l.add   r8,r8,r4
90 
        l.sh    10(r31),r4
91 
        l.lhz   r4,6(r31)
92 
        l.add   r8,r8,r4
93 
        l.sh    8(r31),r4
94 
 
95 
        l.lhs   r4,8(r31)
96 
        l.add   r8,r8,r4
97 
        l.sh    6(r31),r4
98 
        l.lhs   r4,10(r31)
99 
        l.add   r8,r8,r4
100 
        l.sh    4(r31),r4
101 
 
102 
        l.lwz   r4,4(r31)
103 
        l.add   r8,r8,r4
104 
 
105 
        l.mtspr r0,r8,0x1234   /* Should be 0x12352af7 */
106 
 
107 
        l.lwz   r9,0(r31)
108 
        l.add   r8,r9,r8
109 
        l.sw    0(r31),r8
110 
 
111 
_arith:
112 
        l.addi  r3,r0,1
113 
        l.addi  r4,r0,2
114 
        l.addi  r5,r0,-1
115 
        l.addi  r6,r0,-1
116 
        l.addi  r8,r0,0
117 
 
118 
        l.sub   r7,r5,r3
119 
        l.sub   r8,r3,r5
120 
        l.add   r8,r8,r7
121 
 
122 
        l.div   r7,r7,r4
123 
        l.add   r9,r3,r4
124 
        l.mul   r7,r9,r7
125 
        l.divu  r7,r7,r4
126 
        l.add   r8,r8,r7
127 
 
128 
        l.mtspr r0,r8,0x1234   /* Should be 0x7ffffffe */
129 
 
130 
        l.lwz   r9,0(r31)
131 
        l.add   r8,r9,r8
132 
        l.sw    0(r31),r8
133 
 
134 
_log:
135 
        l.addi  r3,r0,1
136 
        l.addi  r4,r0,2
137 
        l.addi  r5,r0,-1
138 
        l.addi  r6,r0,-1
139 
        l.addi  r8,r0,0
140 
 
141 
        l.andi  r8,r8,1
142 
        l.and   r8,r8,r3
143 
 
144 
        l.xori  r8,r5,0xa5a5
145 
        l.xor   r8,r8,r5
146 
 
147 
        l.ori   r8,r8,2
148 
        l.or    r8,r8,r4
149 
 
150 
        l.mtspr r0,r8,0x1234   /* Should be 0xffffa5a7 */
151 
 
152 
        l.lwz   r9,0(r31)
153 
        l.add   r8,r9,r8
154 
        l.sw    0(r31),r8
155 
 
156 
_shift:
157 
        l.addi  r3,r0,1
158 
        l.addi  r4,r0,2
159 
        l.addi  r5,r0,-1
160 
        l.addi  r6,r0,-1
161 
        l.addi  r8,r0,0
162 
 
163 
        l.slli  r8,r5,6
164 
        l.sll   r8,r8,r4
165 
 
166 
        l.srli  r8,r8,6
167 
        l.srl   r8,r8,r4
168 
 
169 
        l.srai  r8,r8,2
170 
        l.sra   r8,r8,r4
171 
 
172 
        l.mtspr r0,r8,0x1234   /* Should be 0x000fffff */
173 
 
174 
        l.lwz   r9,0(r31)
175 
        l.add   r8,r9,r8
176 
        l.sw    0(r31),r8
177 
 
178 
_flag:
179 
        l.addi  r3,r0,1
180 
        l.addi  r4,r0,-2
181 
        l.addi  r8,r0,0
182 
 
183 
        l.sfeq  r3,r3
184 
        l.mfspr r5,r0,17
185 
        l.andi  r4,r5,0x200
186 
        l.add   r8,r8,r4
187 
 
188 
        l.sfeq  r3,r4
189 
        l.mfspr r5,r0,17
190 
        l.andi  r4,r5,0x200
191 
        l.add   r8,r8,r4
192 
 
193 
        l.sfeqi r3,1
194 
        l.mfspr r5,r0,17
195 
        l.andi  r4,r5,0x200
196 
        l.add   r8,r8,r4
197 
 
198 
        l.sfeqi r3,-2
199 
        l.mfspr r5,r0,17
200 
        l.andi  r4,r5,0x200
201 
        l.add   r8,r8,r4
202 
 
203 
        l.sfne  r3,r3
204 
        l.mfspr r5,r0,17
205 
        l.andi  r4,r5,0x200
206 
        l.add   r8,r8,r4
207 
 
208 
        l.sfne  r3,r4
209 
        l.mfspr r5,r0,17
210 
        l.andi  r4,r5,0x200
211 
        l.add   r8,r8,r4
212 
 
213 
        l.sfnei r3,1
214 
        l.mfspr r5,r0,17
215 
        l.andi  r4,r5,0x200
216 
        l.add   r8,r8,r4
217 
 
218 
        l.sfnei r3,-2
219 
        l.mfspr r5,r0,17
220 
        l.andi  r4,r5,0x200
221 
        l.add   r8,r8,r4
222 
 
223 
        l.sfgtu r3,r3
224 
        l.mfspr r5,r0,17
225 
        l.andi  r4,r5,0x200
226 
        l.add   r8,r8,r4
227 
 
228 
        l.sfgtu r3,r4
229 
        l.mfspr r5,r0,17
230 
        l.andi  r4,r5,0x200
231 
        l.add   r8,r8,r4
232 
 
233 
        l.sfgtui        r3,1
234 
        l.mfspr r5,r0,17
235 
        l.andi  r4,r5,0x200
236 
        l.add   r8,r8,r4
237 
 
238 
        l.sfgtui        r3,-2
239 
        l.mfspr r5,r0,17
240 
        l.andi  r4,r5,0x200
241 
        l.add   r8,r8,r4
242 
 
243 
        l.sfgeu r3,r3
244 
        l.mfspr r5,r0,17
245 
        l.andi  r4,r5,0x200
246 
        l.add   r8,r8,r4
247 
 
248 
        l.sfgeu r3,r4
249 
        l.mfspr r5,r0,17
250 
        l.andi  r4,r5,0x200
251 
        l.add   r8,r8,r4
252 
 
253 
        l.sfgeui        r3,1
254 
        l.mfspr r5,r0,17
255 
        l.andi  r4,r5,0x200
256 
        l.add   r8,r8,r4
257 
 
258 
        l.sfgeui        r3,-2
259 
        l.mfspr r5,r0,17
260 
        l.andi  r4,r5,0x200
261 
        l.add   r8,r8,r4
262 
 
263 
        l.sfltu r3,r3
264 
        l.mfspr r5,r0,17
265 
        l.andi  r4,r5,0x200
266 
        l.add   r8,r8,r4
267 
 
268 
        l.sfltu r3,r4
269 
        l.mfspr r5,r0,17
270 
        l.andi  r4,r5,0x200
271 
        l.add   r8,r8,r4
272 
 
273 
        l.sfltui        r3,1
274 
        l.mfspr r5,r0,17
275 
        l.andi  r4,r5,0x200
276 
        l.add   r8,r8,r4
277 
 
278 
        l.sfltui        r3,-2
279 
        l.mfspr r5,r0,17
280 
        l.andi  r4,r5,0x200
281 
        l.add   r8,r8,r4
282 
 
283 
        l.sfleu r3,r3
284 
        l.mfspr r5,r0,17
285 
        l.andi  r4,r5,0x200
286 
        l.add   r8,r8,r4
287 
 
288 
        l.sfleu r3,r4
289 
        l.mfspr r5,r0,17
290 
        l.andi  r4,r5,0x200
291 
        l.add   r8,r8,r4
292 
 
293 
        l.sfleui        r3,1
294 
        l.mfspr r5,r0,17
295 
        l.andi  r4,r5,0x200
296 
        l.add   r8,r8,r4
297 
 
298 
        l.sfleui        r3,-2
299 
        l.mfspr r5,r0,17
300 
        l.andi  r4,r5,0x200
301 
        l.add   r8,r8,r4
302 
 
303 
        l.sfgts r3,r3
304 
        l.mfspr r5,r0,17
305 
        l.andi  r4,r5,0x200
306 
        l.add   r8,r8,r4
307 
 
308 
        l.sfgts r3,r4
309 
        l.mfspr r5,r0,17
310 
        l.andi  r4,r5,0x200
311 
        l.add   r8,r8,r4
312 
 
313 
        l.sfgtsi        r3,1
314 
        l.mfspr r5,r0,17
315 
        l.andi  r4,r5,0x200
316 
        l.add   r8,r8,r4
317 
 
318 
        l.sfgtsi        r3,-2
319 
        l.mfspr r5,r0,17
320 
        l.andi  r4,r5,0x200
321 
        l.add   r8,r8,r4
322 
 
323 
        l.sfges r3,r3
324 
        l.mfspr r5,r0,17
325 
        l.andi  r4,r5,0x200
326 
        l.add   r8,r8,r4
327 
 
328 
        l.sfges r3,r4
329 
        l.mfspr r5,r0,17
330 
        l.andi  r4,r5,0x200
331 
        l.add   r8,r8,r4
332 
 
333 
        l.sfgesi        r3,1
334 
        l.mfspr r5,r0,17
335 
        l.andi  r4,r5,0x200
336 
        l.add   r8,r8,r4
337 
 
338 
        l.sfgesi        r3,-2
339 
        l.mfspr r5,r0,17
340 
        l.andi  r4,r5,0x200
341 
        l.add   r8,r8,r4
342 
 
343 
        l.sflts r3,r3
344 
        l.mfspr r5,r0,17
345 
        l.andi  r4,r5,0x200
346 
        l.add   r8,r8,r4
347 
 
348 
        l.sflts r3,r4
349 
        l.mfspr r5,r0,17
350 
        l.andi  r4,r5,0x200
351 
        l.add   r8,r8,r4
352 
 
353 
        l.sfltsi        r3,1
354 
        l.mfspr r5,r0,17
355 
        l.andi  r4,r5,0x200
356 
        l.add   r8,r8,r4
357 
 
358 
        l.sfltsi        r3,-2
359 
        l.mfspr r5,r0,17
360 
        l.andi  r4,r5,0x200
361 
        l.add   r8,r8,r4
362 
 
363 
        l.sfles r3,r3
364 
        l.mfspr r5,r0,17
365 
        l.andi  r4,r5,0x200
366 
        l.add   r8,r8,r4
367 
 
368 
        l.sfles r3,r4
369 
        l.mfspr r5,r0,17
370 
        l.andi  r4,r5,0x200
371 
        l.add   r8,r8,r4
372 
 
373 
        l.sflesi        r3,1
374 
        l.mfspr r5,r0,17
375 
        l.andi  r4,r5,0x200
376 
        l.add   r8,r8,r4
377 
 
378 
        l.sflesi        r3,-2
379 
        l.mfspr r5,r0,17
380 
        l.andi  r4,r5,0x200
381 
        l.add   r8,r8,r4
382 
 
383 
        l.mtspr r0,r8,0x1234   /* Should be 0x00002800 */
384 
 
385 
        l.lwz   r9,0(r31)
386 
        l.add   r8,r9,r8
387 
        l.sw    0(r31),r8
388 
 
389 
_jump:
390 
        l.addi  r8,r0,0
391 
 
392 
        l.j     _T1
393 
        l.addi  r8,r8,1
394 
 
395 
_T2:    l.jr    r9
396 
        l.addi  r8,r8,1
397 
 
398 
_T1:    l.jal   _T2
399 
        l.addi  r8,r8,1
400 
 
401 
        l.sfeqi r0,0
402 
        l.bf    _T3
403 
        l.addi  r8,r8,1
404 
 
405 
_T3:    l.sfeqi r0,1
406 
        l.bf    _T4
407 
        l.addi  r8,r8,1
408 
 
409 
        l.addi  r8,r8,1
410 
 
411 
_T4:    l.sfeqi r0,0
412 
        l.bnf    _T5
413 
        l.addi  r8,r8,1
414 
 
415 
        l.addi  r8,r8,1
416 
 
417 
_T5:    l.sfeqi r0,1
418 
        l.bnf    _T6
419 
        l.addi  r8,r8,1
420 
 
421 
        l.addi  r8,r8,1
422 
 
423 
_T6:    l.movhi r3,hi(_T7)
424 
        l.ori  r3,r0,lo(_T7)
425 
        l.mtspr r0,r3,32
426 
        l.mfspr r5,r0,17
427 
        l.mtspr r0,r5,64
428 
        l.rfe
429 
        l.addi  r8,r8,1 /* l.rfe should not have a delay slot */
430 
 
431 
        l.addi  r8,r8,1
432 
 
433 
_T7:    l.mtspr r0,r8,0x1234   /* Should be 0x000000009 */
434 
 
435 
        l.lwz   r9,0(r31)
436 
        l.add   r8,r9,r8
437 
        l.sw    0(r31),r8
438 
 
439 
        l.lwz   r9,0(r31)
440 
        l.movhi r3,0x4c69
441 
        l.ori   r3,r3,0xe5f7
442 
        l.add   r8,r8,r3
443 
 
444 
        l.mtspr r0,r8,0x1234   /* Should be 0xdeaddead */
445 
 
446 
        l.addi  r3,r0,0
447 
        l.sys   203
448 
 

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