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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [board.h] - Blame information for rev 1782

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#ifndef _BOARD_H_
#define _BOARD_H_
 
#define MC_CSR_VAL      0x0B000300
#define MC_MASK_VAL     0x000003f0
#define FLASH_BASE_ADDR 0xf0000000
#define FLASH_TMS_VAL   0x00000103
#define SDRAM_BASE_ADDR 0x00000000
#define SDRAM_TMS_VAL   0x19220057
 
 
#define UART_BASE           0x90000000
#define UART_IRQ        2
#define ETH_BASE        0x92000000
#define ETH_IRQ         4
#define KBD_BASE_ADD    0x94000000
#define KBD_IRQ         5
#define MC_BASE_ADDR    0x93000000
#define DMA_BASE        0xb8000000
 
#endif

Line No.	Rev	Author	Line
1	970	simons	`#ifndef _BOARD_H_`
2			`#define _BOARD_H_`
3
4			`#define MC_CSR_VAL 0x0B000300`
5			`#define MC_MASK_VAL 0x000003f0`
6			`#define FLASH_BASE_ADDR 0xf0000000`
7			`#define FLASH_TMS_VAL 0x00000103`
8			`#define SDRAM_BASE_ADDR 0x00000000`
9			`#define SDRAM_TMS_VAL 0x19220057`
10
11
12			`#define UART_BASE 0x90000000`
13	972	simons	`#define UART_IRQ 2`
14	970	simons	`#define ETH_BASE 0x92000000`
15	972	simons	`#define ETH_IRQ 4`
16	970	simons	`#define KBD_BASE_ADD 0x94000000`
17			`#define KBD_IRQ 5`
18			`#define MC_BASE_ADDR 0x93000000`
19			`#define DMA_BASE 0xb8000000`
20
21			`#endif`

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [board.h] - Blame information for rev 1782