URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.c] - Blame information for rev 1782

Go to most recent revision | Details | Compare with Previous | View Log


/* Cache test */
#include "support.h"
#include "spr_defs.h"
 
 
#undef  UART
 
#define MEM_RAM 0x00100000
 
/* Number of IC sets (power of 2) */
#define IC_SETS 256
#define DC_SETS 256
 
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
#define IC_BLOCK_SIZE 16
#define DC_BLOCK_SIZE 16
 
/* Number of IC ways (1, 2, 3 etc.). */
#define IC_WAYS 1
#define DC_WAYS 1
 
/* Cache size */
#define IC_SIZE (IC_WAYS*IC_SETS*IC_BLOCK_SIZE)
#define DC_SIZE (DC_WAYS*DC_SETS*DC_BLOCK_SIZE)
 
/* Memory access macros */
#define REG8(add) *((volatile unsigned char *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG32(add) *((volatile unsigned long *)(add))
 
#if UART
#include "uart.h"
#define IN_CLK  20000000
#define UART_BASE  0x9c000000
#define UART_BAUD_RATE 9600
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
        do { \
                lsr = REG8(UART_BASE + UART_LSR); \
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
        do { \
                lsr = REG8(UART_BASE + UART_LSR); \
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR \
        (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
         do { \
                lsr = REG8(UART_BASE + UART_LSR); \
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
#define print_n(x)  \
  { \
    uart_putc(s[((x) >> 28) & 0x0f]); \
    uart_putc(s[((x) >> 24) & 0x0f]); \
    uart_putc(s[((x) >> 20) & 0x0f]); \
    uart_putc(s[((x) >> 16) & 0x0f]); \
    uart_putc(s[((x) >> 12) & 0x0f]); \
    uart_putc(s[((x) >> 8) & 0x0f]);  \
    uart_putc(s[((x) >> 4) & 0x0f]);  \
    uart_putc(s[((x) >> 0) & 0x0f]);  \
  }
 
const char s[] = "0123456789abcdef";
 
void uart_init(void)
{
        int devisor;
 
        /* Reset receiver and transmiter */
        REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
        /* Disable all interrupts */
        REG8(UART_BASE + UART_IER) = 0x00;
 
        /* Set 8 bit char, 1 stop bit, no parity */
        REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
        /* Set baud rate */
        devisor = IN_CLK/(16 * UART_BAUD_RATE);
        REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
        REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
        REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
        REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
 
        return;
}
 
static inline void uart_putc(char c)
{
        unsigned char lsr;
 
        WAIT_FOR_THRE;
        REG8(UART_BASE + UART_TX) = c;
        if(c == '\n') {
          WAIT_FOR_THRE;
          REG8(UART_BASE + UART_TX) = '\r';
        }
        WAIT_FOR_XMITR;
}
 
static inline void print_str(char *str)
{
  while(*str != 0) {
    uart_putc(*str);
    str++;
  }
}
 
static inline char uart_getc()
{
        unsigned char lsr;
        char c;
 
        WAIT_FOR_CHAR;
        c = REG8(UART_BASE + UART_RX);
        return c;
}
#endif
 
extern void ic_enable(void);
extern void ic_disable(void);
extern void dc_enable(void);
extern void dc_disable(void);
extern void dc_inv(void);
extern unsigned long ic_inv_test(void);
extern unsigned long dc_inv_test(unsigned long);
 
extern void (*jalr)(void);
extern void (*jr)(void);
 
/* Index on jump table */
unsigned long jump_indx;
 
/* Jump address table */
unsigned long jump_add[15*IC_WAYS];
 
void dummy();
 
void jump_and_link(void)
{
        asm("_jalr:");
  asm("l.jr\tr9");
  asm("l.nop");
}
 
void jump(void)
{
        asm("_jr:");
        /* Read and increment index */
        asm("l.lwz\t\tr3,0(r11)");
        asm("l.addi\t\tr3,r3,4");
        asm("l.sw\t\t0(r11),r3");
        /* Load next executin address from table */
        asm("l.lwz\t\tr3,0(r3)");
        /* Jump to that address */
        asm("l.jr\t\tr3") ;
        /* Report that we succeeded */
        asm("l.nop\t0");
}
 
void copy_jr(unsigned long add)
{
        memcpy((void *)add, (void *)&jr, 24);
}
 
void call(unsigned long add)
{
  asm("l.movhi\tr11,hi(_jump_indx)" : :);
  asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
        asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
        asm("l.nop" : :);
}
 
int dc_test(void)
{
        int i;
        unsigned long base, add, ul;
 
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
 
        dc_enable();
 
        /* Cache miss r */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                ul = REG32(add);
                ul = REG32(add + DC_BLOCK_SIZE + 4);
                ul = REG32(add + 2*DC_BLOCK_SIZE + 8);
                ul = REG32(add + 3*DC_BLOCK_SIZE + 12);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG32(add + 0) = 0x00000001;
                REG32(add + 4) = 0x00000000;
                REG32(add + 8) = 0x00000000;
                REG32(add + 12) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
                REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
                REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit r/w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG8(add + DC_BLOCK_SIZE - 4) = REG8(add + 3);
                REG8(add + 2*DC_BLOCK_SIZE - 8) = REG8(add + DC_BLOCK_SIZE + 7);
                REG8(add + 3*DC_BLOCK_SIZE - 12) = REG8(add + 2*DC_BLOCK_SIZE + 11);
                REG8(add + 4*DC_BLOCK_SIZE - 16) = REG8(add + 3*DC_BLOCK_SIZE + 15);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit/miss r/w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) = REG16(add + DC_BLOCK_SIZE - 4) + REG16(add + 2);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) = REG16(add + DC_BLOCK_SIZE - 8) + REG16(add + DC_BLOCK_SIZE + 6);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) = REG16(add + DC_BLOCK_SIZE - 12) + REG16(add + 2*DC_BLOCK_SIZE + 10);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) = REG16(add+ DC_BLOCK_SIZE - 16) + REG16(add + 2*DC_BLOCK_SIZE + 14);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Fill cache with unused data */
        add = base + DC_WAYS*DC_SETS*DC_BLOCK_SIZE;
        for(i = 0; i < DC_WAYS; i++) {
                ul = REG32(add);
                ul = REG32(add + DC_BLOCK_SIZE);
                ul = REG32(add + 2*DC_BLOCK_SIZE);
                ul = REG32(add + 3*DC_BLOCK_SIZE);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit/miss r */
        ul = 0;
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) +
                        REG16(add + DC_BLOCK_SIZE - 4) +
                        REG16(add + 2);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) +
                        REG16(add + DC_BLOCK_SIZE - 8) +
                        REG16(add + DC_BLOCK_SIZE + 6);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) +
                        REG16(add + DC_BLOCK_SIZE - 12) +
                        REG16(add + 2*DC_BLOCK_SIZE + 10);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) +
                        REG16(add+ DC_BLOCK_SIZE - 16) +
                        REG16(add + 2*DC_BLOCK_SIZE + 14);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        dc_disable();
 
        return ul;
}
 
int ic_test(void)
{
        int i;
        unsigned long base, add;
 
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
 
        /* Copy jr to various location */
        add = base;
        for(i = 0; i < IC_WAYS; i++) {
                copy_jr(add);
                copy_jr(add + 2*IC_BLOCK_SIZE + 4);
                copy_jr(add + 4*IC_BLOCK_SIZE + 8);
                copy_jr(add + 6*IC_BLOCK_SIZE + 12);
 
                copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);
                copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);
                copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);
                copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);
                add += IC_SETS*IC_BLOCK_SIZE;
        }
 
        /* Load execution table which starts at address 4 (at address 0 is table index) */
        add = base;
        for(i = 0; i < IC_WAYS; i++) {
                /* Cache miss */
                jump_add[15*i + 0] = add + 2*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 1] = add + 4*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 2] = add + 6*IC_BLOCK_SIZE + 12;
                /* Cache hit/miss */
                jump_add[15*i + 3] = add;
                jump_add[15*i + 4] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
                jump_add[15*i + 5] = add + 2*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 6] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 7] = add + 4*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 8] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 9] = add + 6*IC_BLOCK_SIZE + 12;
                jump_add[15*i + 10] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
                /* Cache hit */
                jump_add[15*i + 11] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
                jump_add[15*i + 12] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 13] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 14] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
 
                add += IC_SETS*IC_BLOCK_SIZE;
        }
 
        /* Go home */
        jump_add[15*i] = (unsigned long)&jalr;
 
        /* Initilalize table index */
        jump_indx = (unsigned long)&jump_add[0];
 
        ic_enable();
 
        /* Go */
        call(base);
 
        ic_disable();
 
        return 0;
}
 
int main(void)
{
        unsigned long rc, ret = 0;
 
#ifdef UART
  /* Initialize controller */
  uart_init();
#endif
 
#ifdef UART
  print_str("DC test :            ");
#endif
        rc = dc_test();
  ret += rc;
#ifdef UART
  print_n(rc+0xdeaddca1);
  print_str("\n");
#else
        report(rc + 0xdeaddca1);
#endif
 
#ifdef UART
  print_str("DC invalidate test : ");
#endif
        rc = dc_inv_test(MEM_RAM);
  ret += rc;
#ifdef UART
  print_n(rc + 0x9e8daa91);
  print_str("\n");
#else
        report(rc + 0x9e8daa91);
#endif
 
#ifdef UART
  print_str("IC test :            ");
#endif
        rc = ic_test();
  ret += rc;
#ifdef UART
  print_n(rc + 0xdeaddead);
  print_str("\n");
#else
        report(rc + 0xdeaddead);
#endif
 
 
#ifdef UART
  print_str("IC invalidate test : ");
#endif
  ic_enable();
  rc = ic_inv_test();
  ret += rc;
#ifdef UART
  print_n(rc + 0xdeadde8f);
  print_str("\n");
  while(1);
#else
        report(rc + 0xdeadde8f);
#endif
 
 
        report(ret + 0x9e8da867);
  exit(0);
 
        return 0;
}
 
/* just for size calculation */
void dummy()
{
}

Line No.	Rev	Author	Line
1	224	markom	`/* Cache test */`
2			`#include "support.h"`
3			`#include "spr_defs.h"`
4
5	424	markom
6	621	simons	`#undef UART`
7
8			`#define MEM_RAM 0x00100000`
9
10	224	markom	`/* Number of IC sets (power of 2) */`
11	621	simons	`#define IC_SETS 256`
12			`#define DC_SETS 256`
13	224	markom
14			`/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */`
15			`#define IC_BLOCK_SIZE 16`
16			`#define DC_BLOCK_SIZE 16`
17
18			`/* Number of IC ways (1, 2, 3 etc.). */`
19			`#define IC_WAYS 1`
20			`#define DC_WAYS 1`
21
22			`/* Cache size */`
23			`#define IC_SIZE (IC_WAYSIC_SETSIC_BLOCK_SIZE)`
24			`#define DC_SIZE (DC_WAYSDC_SETSDC_BLOCK_SIZE)`
25
26			`/* Memory access macros */`
27			`#define REG8(add) ((volatile unsigned char )(add))`
28			`#define REG16(add) ((volatile unsigned short )(add))`
29			`#define REG32(add) ((volatile unsigned long )(add))`
30
31	621	simons	`#if UART`
32			`#include "uart.h"`
33			`#define IN_CLK 20000000`
34			`#define UART_BASE 0x9c000000`
35			`#define UART_BAUD_RATE 9600`
36
37			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
38
39			`#define WAIT_FOR_XMITR \`
40			`do { \`
41			`lsr = REG8(UART_BASE + UART_LSR); \`
42			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
43
44			`#define WAIT_FOR_THRE \`
45			`do { \`
46			`lsr = REG8(UART_BASE + UART_LSR); \`
47			`} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)`
48
49			`#define CHECK_FOR_CHAR \`
50			`(REG8(UART_BASE + UART_LSR) & UART_LSR_DR)`
51
52			`#define WAIT_FOR_CHAR \`
53			`do { \`
54			`lsr = REG8(UART_BASE + UART_LSR); \`
55			`} while ((lsr & UART_LSR_DR) != UART_LSR_DR)`
56
57			`#define UART_TX_BUFF_LEN 32`
58			`#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)`
59
60			`#define print_n(x) \`
61			`{ \`
62			`uart_putc(s[((x) >> 28) & 0x0f]); \`
63			`uart_putc(s[((x) >> 24) & 0x0f]); \`
64			`uart_putc(s[((x) >> 20) & 0x0f]); \`
65			`uart_putc(s[((x) >> 16) & 0x0f]); \`
66			`uart_putc(s[((x) >> 12) & 0x0f]); \`
67			`uart_putc(s[((x) >> 8) & 0x0f]); \`
68			`uart_putc(s[((x) >> 4) & 0x0f]); \`
69			`uart_putc(s[((x) >> 0) & 0x0f]); \`
70			`}`
71
72			`const char s[] = "0123456789abcdef";`
73
74			`void uart_init(void)`
75			`{`
76			`int devisor;`
77
78			`/* Reset receiver and transmiter */`
79			`REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT \| UART_FCR_TRIGGER_14;`
80
81			`/* Disable all interrupts */`
82			`REG8(UART_BASE + UART_IER) = 0x00;`
83
84			`/* Set 8 bit char, 1 stop bit, no parity */`
85			`REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP \| UART_LCR_PARITY);`
86
87			`/* Set baud rate */`
88			`devisor = IN_CLK/(16 * UART_BAUD_RATE);`
89			`REG8(UART_BASE + UART_LCR) \|= UART_LCR_DLAB;`
90			`REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;`
91			`REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;`
92			`REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);`
93
94			`return;`
95			`}`
96
97			`static inline void uart_putc(char c)`
98			`{`
99			`unsigned char lsr;`
100
101			`WAIT_FOR_THRE;`
102			`REG8(UART_BASE + UART_TX) = c;`
103			`if(c == '\n') {`
104			`WAIT_FOR_THRE;`
105			`REG8(UART_BASE + UART_TX) = '\r';`
106			`}`
107			`WAIT_FOR_XMITR;`
108			`}`
109
110			`static inline void print_str(char *str)`
111			`{`
112			`while(*str != 0) {`
113			`uart_putc(*str);`
114			`str++;`
115			`}`
116			`}`
117
118			`static inline char uart_getc()`
119			`{`
120			`unsigned char lsr;`
121			`char c;`
122
123			`WAIT_FOR_CHAR;`
124			`c = REG8(UART_BASE + UART_RX);`
125			`return c;`
126			`}`
127			`#endif`
128
129			`extern void ic_enable(void);`
130			`extern void ic_disable(void);`
131			`extern void dc_enable(void);`
132			`extern void dc_disable(void);`
133			`extern void dc_inv(void);`
134			`extern unsigned long ic_inv_test(void);`
135			`extern unsigned long dc_inv_test(unsigned long);`
136
137	224	markom	`extern void (*jalr)(void);`
138			`extern void (*jr)(void);`
139
140	484	simons	`/* Index on jump table */`
141			`unsigned long jump_indx;`
142
143			`/* Jump address table */`
144			`unsigned long jump_add[15*IC_WAYS];`
145
146	224	markom	`void dummy();`
147
148			`void jump_and_link(void)`
149			`{`
150			`asm("_jalr:");`
151	575	simons	`asm("l.jr\tr9");`
152			`asm("l.nop");`
153	224	markom	`}`
154
155			`void jump(void)`
156			`{`
157			`asm("_jr:");`
158			`/* Read and increment index */`
159	484	simons	`asm("l.lwz\t\tr3,0(r11)");`
160	224	markom	`asm("l.addi\t\tr3,r3,4");`
161	484	simons	`asm("l.sw\t\t0(r11),r3");`
162	224	markom	`/* Load next executin address from table */`
163			`asm("l.lwz\t\tr3,0(r3)");`
164			`/* Jump to that address */`
165			`asm("l.jr\t\tr3") ;`
166			`/* Report that we succeeded */`
167	621	simons	`asm("l.nop\t0");`
168	224	markom	`}`
169
170			`void copy_jr(unsigned long add)`
171			`{`
172	322	simons	`memcpy((void )add, (void )&jr, 24);`
173	224	markom	`}`
174
175			`void call(unsigned long add)`
176			`{`
177	484	simons	`asm("l.movhi\tr11,hi(_jump_indx)" : :);`
178			`asm("l.ori\tr11,r11,lo(_jump_indx)" : :);`
179	575	simons	`asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");`
180	224	markom	`asm("l.nop" : :);`
181			`}`
182
183			`int dc_test(void)`
184			`{`
185			`int i;`
186			`unsigned long base, add, ul;`
187
188	484	simons	`base = (((unsigned long)MEM_RAM / (IC_SETSIC_BLOCK_SIZE)) IC_SETSIC_BLOCK_SIZE) + IC_SETSIC_BLOCK_SIZE;`
189	224	markom
190	621	simons	`dc_enable();`
191	224	markom
192			`/* Cache miss r */`
193			`add = base;`
194			`for(i = 0; i < DC_WAYS; i++) {`
195			`ul = REG32(add);`
196	621	simons	`ul = REG32(add + DC_BLOCK_SIZE + 4);`
197			`ul = REG32(add + 2*DC_BLOCK_SIZE + 8);`
198			`ul = REG32(add + 3*DC_BLOCK_SIZE + 12);`
199	224	markom	`add += DC_SETS*DC_BLOCK_SIZE;`
200			`}`
201
202			`/* Cache hit w */`
203			`add = base;`
204			`for(i = 0; i < DC_WAYS; i++) {`
205			`REG32(add + 0) = 0x00000001;`
206	621	simons	`REG32(add + 4) = 0x00000000;`
207			`REG32(add + 8) = 0x00000000;`
208			`REG32(add + 12) = 0x00000000;`
209			`REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;`
210	224	markom	`REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;`
211	621	simons	`REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;`
212			`REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;`
213			`REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;`
214			`REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;`
215	224	markom	`REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;`
216	621	simons	`REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;`
217			`REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;`
218			`REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;`
219			`REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;`
220	224	markom	`REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;`
221			`add += DC_SETS*DC_BLOCK_SIZE;`
222			`}`
223
224			`/* Cache hit r/w */`
225			`add = base;`
226			`for(i = 0; i < DC_WAYS; i++) {`
227			`REG8(add + DC_BLOCK_SIZE - 4) = REG8(add + 3);`
228			`REG8(add + 2*DC_BLOCK_SIZE - 8) = REG8(add + DC_BLOCK_SIZE + 7);`
229			`REG8(add + 3DC_BLOCK_SIZE - 12) = REG8(add + 2DC_BLOCK_SIZE + 11);`
230			`REG8(add + 4DC_BLOCK_SIZE - 16) = REG8(add + 3DC_BLOCK_SIZE + 15);`
231			`add += DC_SETS*DC_BLOCK_SIZE;`
232			`}`
233
234			`/* Cache hit/miss r/w */`
235			`add = base;`
236			`for(i = 0; i < DC_WAYS; i++) {`
237			`REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) = REG16(add + DC_BLOCK_SIZE - 4) + REG16(add + 2);`
238			`REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) = REG16(add + DC_BLOCK_SIZE - 8) + REG16(add + DC_BLOCK_SIZE + 6);`
239			`REG16(add + (IC_SETS - 1)IC_BLOCK_SIZE + 4) = REG16(add + DC_BLOCK_SIZE - 12) + REG16(add + 2DC_BLOCK_SIZE + 10);`
240			`REG16(add + (IC_SETS - 1)IC_BLOCK_SIZE + 6) = REG16(add+ DC_BLOCK_SIZE - 16) + REG16(add + 2DC_BLOCK_SIZE + 14);`
241			`add += DC_SETS*DC_BLOCK_SIZE;`
242			`}`
243
244			`/* Fill cache with unused data */`
245			`add = base + DC_WAYSDC_SETSDC_BLOCK_SIZE;`
246			`for(i = 0; i < DC_WAYS; i++) {`
247			`ul = REG32(add);`
248			`ul = REG32(add + DC_BLOCK_SIZE);`
249			`ul = REG32(add + 2*DC_BLOCK_SIZE);`
250			`ul = REG32(add + 3*DC_BLOCK_SIZE);`
251			`add += DC_SETS*DC_BLOCK_SIZE;`
252			`}`
253
254			`/* Cache hit/miss r */`
255			`ul = 0;`
256			`add = base;`
257			`for(i = 0; i < DC_WAYS; i++) {`
258			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) +`
259			`REG16(add + DC_BLOCK_SIZE - 4) +`
260			`REG16(add + 2);`
261			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) +`
262			`REG16(add + DC_BLOCK_SIZE - 8) +`
263			`REG16(add + DC_BLOCK_SIZE + 6);`
264			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) +`
265			`REG16(add + DC_BLOCK_SIZE - 12) +`
266			`REG16(add + 2*DC_BLOCK_SIZE + 10);`
267			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) +`
268			`REG16(add+ DC_BLOCK_SIZE - 16) +`
269			`REG16(add + 2*DC_BLOCK_SIZE + 14);`
270			`add += DC_SETS*DC_BLOCK_SIZE;`
271			`}`
272
273	621	simons	`dc_disable();`
274	224	markom
275			`return ul;`
276			`}`
277
278			`int ic_test(void)`
279			`{`
280	322	simons	`int i;`
281			`unsigned long base, add;`
282
283	484	simons	`base = (((unsigned long)MEM_RAM / (IC_SETSIC_BLOCK_SIZE)) IC_SETSIC_BLOCK_SIZE) + IC_SETSIC_BLOCK_SIZE;`
284	349	simons
285	322	simons	`/* Copy jr to various location */`
286			`add = base;`
287			`for(i = 0; i < IC_WAYS; i++) {`
288			`copy_jr(add);`
289			`copy_jr(add + 2*IC_BLOCK_SIZE + 4);`
290			`copy_jr(add + 4*IC_BLOCK_SIZE + 8);`
291			`copy_jr(add + 6*IC_BLOCK_SIZE + 12);`
292
293			`copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);`
294			`copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);`
295			`copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);`
296			`copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);`
297			`add += IC_SETS*IC_BLOCK_SIZE;`
298			`}`
299
300			`/* Load execution table which starts at address 4 (at address 0 is table index) */`
301			`add = base;`
302			`for(i = 0; i < IC_WAYS; i++) {`
303			`/* Cache miss */`
304	484	simons	`jump_add[15i + 0] = add + 2IC_BLOCK_SIZE + 4;`
305			`jump_add[15i + 1] = add + 4IC_BLOCK_SIZE + 8;`
306			`jump_add[15i + 2] = add + 6IC_BLOCK_SIZE + 12;`
307	322	simons	`/* Cache hit/miss */`
308	484	simons	`jump_add[15*i + 3] = add;`
309			`jump_add[15i + 4] = add + (IC_SETS - 2)IC_BLOCK_SIZE + 0;`
310			`jump_add[15i + 5] = add + 2IC_BLOCK_SIZE + 4;`
311			`jump_add[15i + 6] = add + (IC_SETS - 4)IC_BLOCK_SIZE + 4;`
312			`jump_add[15i + 7] = add + 4IC_BLOCK_SIZE + 8;`
313			`jump_add[15i + 8] = add + (IC_SETS - 6)IC_BLOCK_SIZE + 8;`
314			`jump_add[15i + 9] = add + 6IC_BLOCK_SIZE + 12;`
315			`jump_add[15i + 10] = add + (IC_SETS - 8)IC_BLOCK_SIZE + 12;`
316	322	simons	`/* Cache hit */`
317	484	simons	`jump_add[15i + 11] = add + (IC_SETS - 2)IC_BLOCK_SIZE + 0;`
318			`jump_add[15i + 12] = add + (IC_SETS - 4)IC_BLOCK_SIZE + 4;`
319			`jump_add[15i + 13] = add + (IC_SETS - 6)IC_BLOCK_SIZE + 8;`
320			`jump_add[15i + 14] = add + (IC_SETS - 8)IC_BLOCK_SIZE + 12;`
321
322	322	simons	`add += IC_SETS*IC_BLOCK_SIZE;`
323			`}`
324
325			`/* Go home */`
326	484	simons	`jump_add[15*i] = (unsigned long)&jalr;`
327	322	simons
328			`/* Initilalize table index */`
329	621	simons	`jump_indx = (unsigned long)&jump_add[0];`
330	322	simons
331	621	simons	`ic_enable();`
332	349	simons
333	322	simons	`/* Go */`
334			`call(base);`
335
336	621	simons	`ic_disable();`
337	322	simons
338	621	simons	`return 0;`
339	224	markom	`}`
340
341			`int main(void)`
342			`{`
343	621	simons	`unsigned long rc, ret = 0;`
344	224	markom
345	621	simons	`#ifdef UART`
346			`/* Initialize controller */`
347			`uart_init();`
348			`#endif`
349
350			`#ifdef UART`
351			`print_str("DC test : ");`
352			`#endif`
353	224	markom	`rc = dc_test();`
354	621	simons	`ret += rc;`
355			`#ifdef UART`
356			`print_n(rc+0xdeaddca1);`
357			`print_str("\n");`
358			`#else`
359	224	markom	`report(rc + 0xdeaddca1);`
360	621	simons	`#endif`
361	224	markom
362	621	simons	`#ifdef UART`
363			`print_str("DC invalidate test : ");`
364			`#endif`
365			`rc = dc_inv_test(MEM_RAM);`
366			`ret += rc;`
367			`#ifdef UART`
368			`print_n(rc + 0x9e8daa91);`
369			`print_str("\n");`
370			`#else`
371			`report(rc + 0x9e8daa91);`
372			`#endif`
373	224	markom
374	621	simons	`#ifdef UART`
375			`print_str("IC test : ");`
376			`#endif`
377	322	simons	`rc = ic_test();`
378	621	simons	`ret += rc;`
379			`#ifdef UART`
380			`print_n(rc + 0xdeaddead);`
381			`print_str("\n");`
382			`#else`
383			`report(rc + 0xdeaddead);`
384			`#endif`
385	574	markom
386	621	simons
387			`#ifdef UART`
388			`print_str("IC invalidate test : ");`
389			`#endif`
390			`ic_enable();`
391			`rc = ic_inv_test();`
392			`ret += rc;`
393			`#ifdef UART`
394			`print_n(rc + 0xdeadde8f);`
395			`print_str("\n");`
396			`while(1);`
397			`#else`
398			`report(rc + 0xdeadde8f);`
399			`#endif`
400
401
402	631	simons	`report(ret + 0x9e8da867);`
403	621	simons	`exit(0);`
404
405	574	markom	`return 0;`
406	224	markom	`}`
407
408			`/* just for size calculation */`
409			`void dummy()`
410			`{`
411			`}`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.c] - Blame information for rev 1782