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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.c] - Blame information for rev 224

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1 224 markom 
/* Cache test */
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#include "support.h"
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#include "spr_defs.h"
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/* Number of IC sets (power of 2) */
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#define IC_SETS 512
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#define DC_SETS 512
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/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
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#define IC_BLOCK_SIZE 16
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#define DC_BLOCK_SIZE 16
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/* Number of IC ways (1, 2, 3 etc.). */
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#define IC_WAYS 1
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#define DC_WAYS 1
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/* Cache size */
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#define IC_SIZE (IC_WAYS*IC_SETS*IC_BLOCK_SIZE)
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#define DC_SIZE (DC_WAYS*DC_SETS*DC_BLOCK_SIZE)
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/* Memory access macros */
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#define REG8(add) *((volatile unsigned char *)(add))
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#define REG16(add) *((volatile unsigned short *)(add))
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#define REG32(add) *((volatile unsigned long *)(add))
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extern void (*jalr)(void);
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extern void (*jr)(void);
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void dummy();
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void jump_and_link(void)
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{
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        asm("_jalr:");
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}
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void copy_jalr(unsigned long add)
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{
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        memcpy((void *)add, (void *)jr, 8);
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}
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void jump(void)
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{
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        asm("_jr:");
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        /* Read and increment index */
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        asm("l.lwz\t\tr3,0(r0)");
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        asm("l.addi\t\tr3,r3,4");
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        asm("l.sw\t\t0(r0),r3");
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        /* Load next executin address from table */
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        asm("l.lwz\t\tr3,0(r3)");
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        /* Jump to that address */
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        asm("l.jr\t\tr3") ;
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        /* Report that we succeeded */
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        asm("l.mtspr\t\tr0,r3,0x1234");
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}
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void copy_jr(unsigned long add)
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{
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        memcpy((void *)add, (void *)jr, 24);
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}
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void call(unsigned long add)
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{
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        asm("l.jalr\t\t%0" : : "r" (add) : "r11");
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        asm("l.nop" : :);
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}
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void icache_enable(void)
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{
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        unsigned long add;
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        /* First invalidate the cache. As at this point cache is disabled,
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           the cache acts as it contains image of lowest memory block */
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        for(add = 1; add <= IC_SIZE; add += IC_BLOCK_SIZE)
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                mtspr(SPR_ICBIR, add);
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_ICE);
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}
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void dcache_enable(void)
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{
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        unsigned long add;
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        /* First invalidate the cache. As at this point cache is disabled,
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           the cache acts as it contains image of lowest memory block */
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        for(add = 1; add <= DC_SIZE; add += DC_BLOCK_SIZE)
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                mtspr(SPR_DCBIR, add);
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        mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_DCE);
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}
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void icache_disable(void)
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{
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        /* This is write trough cache so we dont have to flush it */
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        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_ICE);
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}
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void dcache_disable(void)
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{
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        /* This is write trough cache so we dont have to flush it */
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        mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_DCE);
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}
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int dc_test(void)
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{
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        int i;
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        unsigned long base, add, ul;
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        base = ((unsigned long)dummy / (IC_SETS*IC_BLOCK_SIZE)) + IC_SETS*IC_BLOCK_SIZE;
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        dcache_enable();
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        /* Cache miss r */
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        add = base;
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        for(i = 0; i < DC_WAYS; i++) {
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                ul = REG32(add);
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                ul = REG32(add + DC_BLOCK_SIZE);
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                ul = REG32(add + 2*DC_BLOCK_SIZE);
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                ul = REG32(add + 3*DC_BLOCK_SIZE);
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                add += DC_SETS*DC_BLOCK_SIZE;
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        }
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        /* Cache hit w */
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        add = base;
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        for(i = 0; i < DC_WAYS; i++) {
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                REG32(add + 0) = 0x00000001;
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                REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
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                REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
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                REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
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                add += DC_SETS*DC_BLOCK_SIZE;
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        }
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        /* Cache hit r/w */
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        add = base;
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        for(i = 0; i < DC_WAYS; i++) {
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                REG8(add + DC_BLOCK_SIZE - 4) = REG8(add + 3);
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                REG8(add + 2*DC_BLOCK_SIZE - 8) = REG8(add + DC_BLOCK_SIZE + 7);
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                REG8(add + 3*DC_BLOCK_SIZE - 12) = REG8(add + 2*DC_BLOCK_SIZE + 11);
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                REG8(add + 4*DC_BLOCK_SIZE - 16) = REG8(add + 3*DC_BLOCK_SIZE + 15);
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                add += DC_SETS*DC_BLOCK_SIZE;
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        }
143 
 
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        /* Cache hit/miss r/w */
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        add = base;
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        for(i = 0; i < DC_WAYS; i++) {
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                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) = REG16(add + DC_BLOCK_SIZE - 4) + REG16(add + 2);
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                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) = REG16(add + DC_BLOCK_SIZE - 8) + REG16(add + DC_BLOCK_SIZE + 6);
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                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) = REG16(add + DC_BLOCK_SIZE - 12) + REG16(add + 2*DC_BLOCK_SIZE + 10);
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                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) = REG16(add+ DC_BLOCK_SIZE - 16) + REG16(add + 2*DC_BLOCK_SIZE + 14);
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                add += DC_SETS*DC_BLOCK_SIZE;
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        }
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        /* Fill cache with unused data */
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        add = base + DC_WAYS*DC_SETS*DC_BLOCK_SIZE;
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        for(i = 0; i < DC_WAYS; i++) {
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                ul = REG32(add);
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                ul = REG32(add + DC_BLOCK_SIZE);
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                ul = REG32(add + 2*DC_BLOCK_SIZE);
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                ul = REG32(add + 3*DC_BLOCK_SIZE);
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                add += DC_SETS*DC_BLOCK_SIZE;
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        }
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        /* Cache hit/miss r */
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        ul = 0;
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        add = base;
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        for(i = 0; i < DC_WAYS; i++) {
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                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) +
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                        REG16(add + DC_BLOCK_SIZE - 4) +
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                        REG16(add + 2);
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                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) +
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                        REG16(add + DC_BLOCK_SIZE - 8) +
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                        REG16(add + DC_BLOCK_SIZE + 6);
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                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) +
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                        REG16(add + DC_BLOCK_SIZE - 12) +
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                        REG16(add + 2*DC_BLOCK_SIZE + 10);
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                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) +
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                        REG16(add+ DC_BLOCK_SIZE - 16) +
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                        REG16(add + 2*DC_BLOCK_SIZE + 14);
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                add += DC_SETS*DC_BLOCK_SIZE;
181 
        }
182 
 
183 
        dcache_disable();
184 
 
185 
        return ul;
186 
}
187 
 
188 
int ic_test(void)
189 
{
190 
        int i;
191 
        unsigned long base, add;
192 
 
193 
        base = ((unsigned long)dummy / (IC_SETS*IC_BLOCK_SIZE)) + IC_SETS*IC_BLOCK_SIZE;
194 
 
195 
        icache_enable();
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        /* Copy jr to various location */
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        add = base;
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        for(i = 0; i < IC_WAYS; i++) {
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                copy_jr(add);
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                copy_jr(add + 2*IC_BLOCK_SIZE + 4);
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                copy_jr(add + 4*IC_BLOCK_SIZE + 8);
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                copy_jr(add + 6*IC_BLOCK_SIZE + 12);
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                copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);
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                copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);
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                copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);
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                copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);
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                add += IC_WAYS*IC_SETS*IC_BLOCK_SIZE;
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        }
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        /* Load execution table which starts at address 4 (at address 0 is table index) */
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        add = base;
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        for(i = 0; i < IC_WAYS; i++) {
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                /* Cache miss */
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                REG32(0x40*i + 0x04) = add + 2*IC_BLOCK_SIZE + 4;
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                REG32(0x40*i + 0x08) = add + 4*IC_BLOCK_SIZE + 8;
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                REG32(0x40*i + 0x0c) = add + 6*IC_BLOCK_SIZE + 12;
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                /* Cache hit/miss */
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                REG32(0x40*i + 0x10) = add;
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                REG32(0x40*i + 0x14) = add + (IC_SETS - 0)*IC_BLOCK_SIZE + 0;
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                REG32(0x40*i + 0x18) = add + 2*IC_BLOCK_SIZE + 4;
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                REG32(0x40*i + 0x1c) = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 4;
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                REG32(0x40*i + 0x20) = add + 4*IC_BLOCK_SIZE + 8;
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                REG32(0x40*i + 0x24) = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 8;
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                REG32(0x40*i + 0x28) = add + 6*IC_BLOCK_SIZE + 12;
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                REG32(0x40*i + 0x2c) = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 12;
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                /* Cache hit */
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                REG32(0x40*i + 0x30) = add + (IC_SETS - 0)*IC_BLOCK_SIZE + 0;
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                REG32(0x40*i + 0x34) = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 4;
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                REG32(0x40*i + 0x38) = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 8;
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                REG32(0x40*i + 0x3c) = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 12;
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234 
                add += IC_WAYS*IC_SETS*IC_BLOCK_SIZE;
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        }
236 
 
237 
        /* Go home */
238 
        REG32(0x40*i) = (unsigned long)jalr;
239 
 
240 
        /* Initilalize table index */
241 
        REG32(4) = 0;
242 
 
243 
        /* Go */
244 
        call(base);
245 
 
246 
        icache_disable();
247 
 
248 
        return 0xdeaddead;
249 
}
250 
 
251 
 
252 
int main(void)
253 
{
254 
        int rc;
255 
 
256 
        rc = dc_test();
257 
        report(rc + 0xdeaddca1);
258 
 
259 
        /* Be aware that this test doesn't report result troug report call.
260 
           It writes to spr 0x1234 directly (in jump function)!!!
261 
 
262 
           This test can not be run on or1ksim. */
263 
/*      ic_test();
264 
        report(rc);
265 
*/
266 
        exit(0);
267 
}
268 
 
269 
/* just for size calculation */
270 
void dummy()
271 
{
272 
}

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