URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.c] - Blame information for rev 621

Go to most recent revision | Details | Compare with Previous | View Log


/* Cache test */
#include "support.h"
#include "spr_defs.h"
 
#define OR1KSIM 1
 
#ifdef OR1KSIM
#undef  UART
#else
#define UART 1
#endif
 
#define MEM_RAM 0x00100000
 
/* Number of IC sets (power of 2) */
#define IC_SETS 256
#define DC_SETS 256
 
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
#define IC_BLOCK_SIZE 16
#define DC_BLOCK_SIZE 16
 
/* Number of IC ways (1, 2, 3 etc.). */
#define IC_WAYS 1
#define DC_WAYS 1
 
/* Cache size */
#define IC_SIZE (IC_WAYS*IC_SETS*IC_BLOCK_SIZE)
#define DC_SIZE (DC_WAYS*DC_SETS*DC_BLOCK_SIZE)
 
/* Memory access macros */
#define REG8(add) *((volatile unsigned char *)(add))
#define REG16(add) *((volatile unsigned short *)(add))
#define REG32(add) *((volatile unsigned long *)(add))
 
#if UART
#include "uart.h"
#define IN_CLK  20000000
#define UART_BASE  0x9c000000
#define UART_BAUD_RATE 9600
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
        do { \
                lsr = REG8(UART_BASE + UART_LSR); \
        } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
        do { \
                lsr = REG8(UART_BASE + UART_LSR); \
        } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR \
        (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
         do { \
                lsr = REG8(UART_BASE + UART_LSR); \
         } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
#define print_n(x)  \
  { \
    uart_putc(s[((x) >> 28) & 0x0f]); \
    uart_putc(s[((x) >> 24) & 0x0f]); \
    uart_putc(s[((x) >> 20) & 0x0f]); \
    uart_putc(s[((x) >> 16) & 0x0f]); \
    uart_putc(s[((x) >> 12) & 0x0f]); \
    uart_putc(s[((x) >> 8) & 0x0f]);  \
    uart_putc(s[((x) >> 4) & 0x0f]);  \
    uart_putc(s[((x) >> 0) & 0x0f]);  \
  }
 
const char s[] = "0123456789abcdef";
 
void uart_init(void)
{
        int devisor;
 
        /* Reset receiver and transmiter */
        REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
        /* Disable all interrupts */
        REG8(UART_BASE + UART_IER) = 0x00;
 
        /* Set 8 bit char, 1 stop bit, no parity */
        REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
        /* Set baud rate */
        devisor = IN_CLK/(16 * UART_BAUD_RATE);
        REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
        REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
        REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
        REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
 
        return;
}
 
static inline void uart_putc(char c)
{
        unsigned char lsr;
 
        WAIT_FOR_THRE;
        REG8(UART_BASE + UART_TX) = c;
        if(c == '\n') {
          WAIT_FOR_THRE;
          REG8(UART_BASE + UART_TX) = '\r';
        }
        WAIT_FOR_XMITR;
}
 
static inline void print_str(char *str)
{
  while(*str != 0) {
    uart_putc(*str);
    str++;
  }
}
 
static inline char uart_getc()
{
        unsigned char lsr;
        char c;
 
        WAIT_FOR_CHAR;
        c = REG8(UART_BASE + UART_RX);
        return c;
}
#endif
 
extern void ic_enable(void);
extern void ic_disable(void);
extern void dc_enable(void);
extern void dc_disable(void);
extern void dc_inv(void);
extern unsigned long ic_inv_test(void);
extern unsigned long dc_inv_test(unsigned long);
 
extern void (*jalr)(void);
extern void (*jr)(void);
 
/* Index on jump table */
unsigned long jump_indx;
 
/* Jump address table */
unsigned long jump_add[15*IC_WAYS];
 
void dummy();
 
void jump_and_link(void)
{
        asm("_jalr:");
  asm("l.jr\tr9");
  asm("l.nop");
}
 
void jump(void)
{
        asm("_jr:");
        /* Read and increment index */
        asm("l.lwz\t\tr3,0(r11)");
        asm("l.addi\t\tr3,r3,4");
        asm("l.sw\t\t0(r11),r3");
        /* Load next executin address from table */
        asm("l.lwz\t\tr3,0(r3)");
        /* Jump to that address */
        asm("l.jr\t\tr3") ;
        /* Report that we succeeded */
        asm("l.nop\t0");
}
 
void copy_jr(unsigned long add)
{
        memcpy((void *)add, (void *)&jr, 24);
}
 
void call(unsigned long add)
{
  asm("l.movhi\tr11,hi(_jump_indx)" : :);
  asm("l.ori\tr11,r11,lo(_jump_indx)" : :);
        asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");
        asm("l.nop" : :);
}
 
int dc_test(void)
{
        int i;
        unsigned long base, add, ul;
 
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
 
        dc_enable();
 
        /* Cache miss r */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                ul = REG32(add);
                ul = REG32(add + DC_BLOCK_SIZE + 4);
                ul = REG32(add + 2*DC_BLOCK_SIZE + 8);
                ul = REG32(add + 3*DC_BLOCK_SIZE + 12);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG32(add + 0) = 0x00000001;
                REG32(add + 4) = 0x00000000;
                REG32(add + 8) = 0x00000000;
                REG32(add + 12) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;
                REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;
                REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;
                REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;
                REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;
                REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit r/w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG8(add + DC_BLOCK_SIZE - 4) = REG8(add + 3);
                REG8(add + 2*DC_BLOCK_SIZE - 8) = REG8(add + DC_BLOCK_SIZE + 7);
                REG8(add + 3*DC_BLOCK_SIZE - 12) = REG8(add + 2*DC_BLOCK_SIZE + 11);
                REG8(add + 4*DC_BLOCK_SIZE - 16) = REG8(add + 3*DC_BLOCK_SIZE + 15);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit/miss r/w */
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) = REG16(add + DC_BLOCK_SIZE - 4) + REG16(add + 2);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) = REG16(add + DC_BLOCK_SIZE - 8) + REG16(add + DC_BLOCK_SIZE + 6);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) = REG16(add + DC_BLOCK_SIZE - 12) + REG16(add + 2*DC_BLOCK_SIZE + 10);
                REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) = REG16(add+ DC_BLOCK_SIZE - 16) + REG16(add + 2*DC_BLOCK_SIZE + 14);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Fill cache with unused data */
        add = base + DC_WAYS*DC_SETS*DC_BLOCK_SIZE;
        for(i = 0; i < DC_WAYS; i++) {
                ul = REG32(add);
                ul = REG32(add + DC_BLOCK_SIZE);
                ul = REG32(add + 2*DC_BLOCK_SIZE);
                ul = REG32(add + 3*DC_BLOCK_SIZE);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        /* Cache hit/miss r */
        ul = 0;
        add = base;
        for(i = 0; i < DC_WAYS; i++) {
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) +
                        REG16(add + DC_BLOCK_SIZE - 4) +
                        REG16(add + 2);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) +
                        REG16(add + DC_BLOCK_SIZE - 8) +
                        REG16(add + DC_BLOCK_SIZE + 6);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) +
                        REG16(add + DC_BLOCK_SIZE - 12) +
                        REG16(add + 2*DC_BLOCK_SIZE + 10);
                ul +=   REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) +
                        REG16(add+ DC_BLOCK_SIZE - 16) +
                        REG16(add + 2*DC_BLOCK_SIZE + 14);
                add += DC_SETS*DC_BLOCK_SIZE;
        }
 
        dc_disable();
 
        return ul;
}
 
int ic_test(void)
{
        int i;
        unsigned long base, add;
 
        base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
 
        /* Copy jr to various location */
        add = base;
        for(i = 0; i < IC_WAYS; i++) {
                copy_jr(add);
                copy_jr(add + 2*IC_BLOCK_SIZE + 4);
                copy_jr(add + 4*IC_BLOCK_SIZE + 8);
                copy_jr(add + 6*IC_BLOCK_SIZE + 12);
 
                copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);
                copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);
                copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);
                copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);
                add += IC_SETS*IC_BLOCK_SIZE;
        }
 
        /* Load execution table which starts at address 4 (at address 0 is table index) */
        add = base;
        for(i = 0; i < IC_WAYS; i++) {
                /* Cache miss */
                jump_add[15*i + 0] = add + 2*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 1] = add + 4*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 2] = add + 6*IC_BLOCK_SIZE + 12;
                /* Cache hit/miss */
                jump_add[15*i + 3] = add;
                jump_add[15*i + 4] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
                jump_add[15*i + 5] = add + 2*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 6] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 7] = add + 4*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 8] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 9] = add + 6*IC_BLOCK_SIZE + 12;
                jump_add[15*i + 10] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
                /* Cache hit */
                jump_add[15*i + 11] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
                jump_add[15*i + 12] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
                jump_add[15*i + 13] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
                jump_add[15*i + 14] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
 
                add += IC_SETS*IC_BLOCK_SIZE;
        }
 
        /* Go home */
        jump_add[15*i] = (unsigned long)&jalr;
 
        /* Initilalize table index */
        jump_indx = (unsigned long)&jump_add[0];
 
        ic_enable();
 
        /* Go */
        call(base);
 
        ic_disable();
 
        return 0;
}
 
int main(void)
{
        unsigned long rc, ret = 0;
 
#ifdef UART
  /* Initialize controller */
  uart_init();
#endif
 
#ifdef UART
  print_str("DC test :            ");
#endif
        rc = dc_test();
  ret += rc;
#ifdef UART
  print_n(rc+0xdeaddca1);
  print_str("\n");
#else
        report(rc + 0xdeaddca1);
#endif
 
#ifndef OR1KSIM
#ifdef UART
  print_str("DC invalidate test : ");
#endif
        rc = dc_inv_test(MEM_RAM);
  ret += rc;
#ifdef UART
  print_n(rc + 0x9e8daa91);
  print_str("\n");
#else
        report(rc + 0x9e8daa91);
#endif
#endif
 
#ifdef UART
  print_str("IC test :            ");
#endif
        rc = ic_test();
  ret += rc;
#ifdef UART
  print_n(rc + 0xdeaddead);
  print_str("\n");
#else
        report(rc + 0xdeaddead);
#endif
 
 
#ifndef OR1KSIM
#ifdef UART
  print_str("IC invalidate test : ");
#endif
  ic_enable();
  rc = ic_inv_test();
  ret += rc;
#ifdef UART
  print_n(rc + 0xdeadde8f);
  print_str("\n");
  while(1);
#else
        report(rc + 0xdeadde8f);
#endif
#endif
 
 
        report(ret + 0xdeaddca1);
  exit(0);
 
        return 0;
}
 
/* just for size calculation */
void dummy()
{
}

Line No.	Rev	Author	Line
1	224	markom	`/* Cache test */`
2			`#include "support.h"`
3			`#include "spr_defs.h"`
4
5	621	simons	`#define OR1KSIM 1`
6	424	markom
7	621	simons	`#ifdef OR1KSIM`
8			`#undef UART`
9			`#else`
10			`#define UART 1`
11			`#endif`
12
13			`#define MEM_RAM 0x00100000`
14
15	224	markom	`/* Number of IC sets (power of 2) */`
16	621	simons	`#define IC_SETS 256`
17			`#define DC_SETS 256`
18	224	markom
19			`/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */`
20			`#define IC_BLOCK_SIZE 16`
21			`#define DC_BLOCK_SIZE 16`
22
23			`/* Number of IC ways (1, 2, 3 etc.). */`
24			`#define IC_WAYS 1`
25			`#define DC_WAYS 1`
26
27			`/* Cache size */`
28			`#define IC_SIZE (IC_WAYSIC_SETSIC_BLOCK_SIZE)`
29			`#define DC_SIZE (DC_WAYSDC_SETSDC_BLOCK_SIZE)`
30
31			`/* Memory access macros */`
32			`#define REG8(add) ((volatile unsigned char )(add))`
33			`#define REG16(add) ((volatile unsigned short )(add))`
34			`#define REG32(add) ((volatile unsigned long )(add))`
35
36	621	simons	`#if UART`
37			`#include "uart.h"`
38			`#define IN_CLK 20000000`
39			`#define UART_BASE 0x9c000000`
40			`#define UART_BAUD_RATE 9600`
41
42			`#define BOTH_EMPTY (UART_LSR_TEMT \| UART_LSR_THRE)`
43
44			`#define WAIT_FOR_XMITR \`
45			`do { \`
46			`lsr = REG8(UART_BASE + UART_LSR); \`
47			`} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)`
48
49			`#define WAIT_FOR_THRE \`
50			`do { \`
51			`lsr = REG8(UART_BASE + UART_LSR); \`
52			`} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)`
53
54			`#define CHECK_FOR_CHAR \`
55			`(REG8(UART_BASE + UART_LSR) & UART_LSR_DR)`
56
57			`#define WAIT_FOR_CHAR \`
58			`do { \`
59			`lsr = REG8(UART_BASE + UART_LSR); \`
60			`} while ((lsr & UART_LSR_DR) != UART_LSR_DR)`
61
62			`#define UART_TX_BUFF_LEN 32`
63			`#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)`
64
65			`#define print_n(x) \`
66			`{ \`
67			`uart_putc(s[((x) >> 28) & 0x0f]); \`
68			`uart_putc(s[((x) >> 24) & 0x0f]); \`
69			`uart_putc(s[((x) >> 20) & 0x0f]); \`
70			`uart_putc(s[((x) >> 16) & 0x0f]); \`
71			`uart_putc(s[((x) >> 12) & 0x0f]); \`
72			`uart_putc(s[((x) >> 8) & 0x0f]); \`
73			`uart_putc(s[((x) >> 4) & 0x0f]); \`
74			`uart_putc(s[((x) >> 0) & 0x0f]); \`
75			`}`
76
77			`const char s[] = "0123456789abcdef";`
78
79			`void uart_init(void)`
80			`{`
81			`int devisor;`
82
83			`/* Reset receiver and transmiter */`
84			`REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO \| UART_FCR_CLEAR_RCVR \| UART_FCR_CLEAR_XMIT \| UART_FCR_TRIGGER_14;`
85
86			`/* Disable all interrupts */`
87			`REG8(UART_BASE + UART_IER) = 0x00;`
88
89			`/* Set 8 bit char, 1 stop bit, no parity */`
90			`REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP \| UART_LCR_PARITY);`
91
92			`/* Set baud rate */`
93			`devisor = IN_CLK/(16 * UART_BAUD_RATE);`
94			`REG8(UART_BASE + UART_LCR) \|= UART_LCR_DLAB;`
95			`REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;`
96			`REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;`
97			`REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);`
98
99			`return;`
100			`}`
101
102			`static inline void uart_putc(char c)`
103			`{`
104			`unsigned char lsr;`
105
106			`WAIT_FOR_THRE;`
107			`REG8(UART_BASE + UART_TX) = c;`
108			`if(c == '\n') {`
109			`WAIT_FOR_THRE;`
110			`REG8(UART_BASE + UART_TX) = '\r';`
111			`}`
112			`WAIT_FOR_XMITR;`
113			`}`
114
115			`static inline void print_str(char *str)`
116			`{`
117			`while(*str != 0) {`
118			`uart_putc(*str);`
119			`str++;`
120			`}`
121			`}`
122
123			`static inline char uart_getc()`
124			`{`
125			`unsigned char lsr;`
126			`char c;`
127
128			`WAIT_FOR_CHAR;`
129			`c = REG8(UART_BASE + UART_RX);`
130			`return c;`
131			`}`
132			`#endif`
133
134			`extern void ic_enable(void);`
135			`extern void ic_disable(void);`
136			`extern void dc_enable(void);`
137			`extern void dc_disable(void);`
138			`extern void dc_inv(void);`
139			`extern unsigned long ic_inv_test(void);`
140			`extern unsigned long dc_inv_test(unsigned long);`
141
142	224	markom	`extern void (*jalr)(void);`
143			`extern void (*jr)(void);`
144
145	484	simons	`/* Index on jump table */`
146			`unsigned long jump_indx;`
147
148			`/* Jump address table */`
149			`unsigned long jump_add[15*IC_WAYS];`
150
151	224	markom	`void dummy();`
152
153			`void jump_and_link(void)`
154			`{`
155			`asm("_jalr:");`
156	575	simons	`asm("l.jr\tr9");`
157			`asm("l.nop");`
158	224	markom	`}`
159
160			`void jump(void)`
161			`{`
162			`asm("_jr:");`
163			`/* Read and increment index */`
164	484	simons	`asm("l.lwz\t\tr3,0(r11)");`
165	224	markom	`asm("l.addi\t\tr3,r3,4");`
166	484	simons	`asm("l.sw\t\t0(r11),r3");`
167	224	markom	`/* Load next executin address from table */`
168			`asm("l.lwz\t\tr3,0(r3)");`
169			`/* Jump to that address */`
170			`asm("l.jr\t\tr3") ;`
171			`/* Report that we succeeded */`
172	621	simons	`asm("l.nop\t0");`
173	224	markom	`}`
174
175			`void copy_jr(unsigned long add)`
176			`{`
177	322	simons	`memcpy((void )add, (void )&jr, 24);`
178	224	markom	`}`
179
180			`void call(unsigned long add)`
181			`{`
182	484	simons	`asm("l.movhi\tr11,hi(_jump_indx)" : :);`
183			`asm("l.ori\tr11,r11,lo(_jump_indx)" : :);`
184	575	simons	`asm("l.jalr\t\t%0" : : "r" (add) : "r11", "r9");`
185	224	markom	`asm("l.nop" : :);`
186			`}`
187
188			`int dc_test(void)`
189			`{`
190			`int i;`
191			`unsigned long base, add, ul;`
192
193	484	simons	`base = (((unsigned long)MEM_RAM / (IC_SETSIC_BLOCK_SIZE)) IC_SETSIC_BLOCK_SIZE) + IC_SETSIC_BLOCK_SIZE;`
194	224	markom
195	621	simons	`dc_enable();`
196	224	markom
197			`/* Cache miss r */`
198			`add = base;`
199			`for(i = 0; i < DC_WAYS; i++) {`
200			`ul = REG32(add);`
201	621	simons	`ul = REG32(add + DC_BLOCK_SIZE + 4);`
202			`ul = REG32(add + 2*DC_BLOCK_SIZE + 8);`
203			`ul = REG32(add + 3*DC_BLOCK_SIZE + 12);`
204	224	markom	`add += DC_SETS*DC_BLOCK_SIZE;`
205			`}`
206
207			`/* Cache hit w */`
208			`add = base;`
209			`for(i = 0; i < DC_WAYS; i++) {`
210			`REG32(add + 0) = 0x00000001;`
211	621	simons	`REG32(add + 4) = 0x00000000;`
212			`REG32(add + 8) = 0x00000000;`
213			`REG32(add + 12) = 0x00000000;`
214			`REG32(add + DC_BLOCK_SIZE + 0) = 0x00000000;`
215	224	markom	`REG32(add + DC_BLOCK_SIZE + 4) = 0x00000002;`
216	621	simons	`REG32(add + DC_BLOCK_SIZE + 8) = 0x00000000;`
217			`REG32(add + DC_BLOCK_SIZE + 12) = 0x00000000;`
218			`REG32(add + 2*DC_BLOCK_SIZE + 0) = 0x00000000;`
219			`REG32(add + 2*DC_BLOCK_SIZE + 4) = 0x00000000;`
220	224	markom	`REG32(add + 2*DC_BLOCK_SIZE + 8) = 0x00000003;`
221	621	simons	`REG32(add + 2*DC_BLOCK_SIZE + 12) = 0x00000000;`
222			`REG32(add + 3*DC_BLOCK_SIZE + 0) = 0x00000000;`
223			`REG32(add + 3*DC_BLOCK_SIZE + 4) = 0x00000000;`
224			`REG32(add + 3*DC_BLOCK_SIZE + 8) = 0x00000000;`
225	224	markom	`REG32(add + 3*DC_BLOCK_SIZE + 12) = 0x00000004;`
226			`add += DC_SETS*DC_BLOCK_SIZE;`
227			`}`
228
229			`/* Cache hit r/w */`
230			`add = base;`
231			`for(i = 0; i < DC_WAYS; i++) {`
232			`REG8(add + DC_BLOCK_SIZE - 4) = REG8(add + 3);`
233			`REG8(add + 2*DC_BLOCK_SIZE - 8) = REG8(add + DC_BLOCK_SIZE + 7);`
234			`REG8(add + 3DC_BLOCK_SIZE - 12) = REG8(add + 2DC_BLOCK_SIZE + 11);`
235			`REG8(add + 4DC_BLOCK_SIZE - 16) = REG8(add + 3DC_BLOCK_SIZE + 15);`
236			`add += DC_SETS*DC_BLOCK_SIZE;`
237			`}`
238
239			`/* Cache hit/miss r/w */`
240			`add = base;`
241			`for(i = 0; i < DC_WAYS; i++) {`
242			`REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) = REG16(add + DC_BLOCK_SIZE - 4) + REG16(add + 2);`
243			`REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) = REG16(add + DC_BLOCK_SIZE - 8) + REG16(add + DC_BLOCK_SIZE + 6);`
244			`REG16(add + (IC_SETS - 1)IC_BLOCK_SIZE + 4) = REG16(add + DC_BLOCK_SIZE - 12) + REG16(add + 2DC_BLOCK_SIZE + 10);`
245			`REG16(add + (IC_SETS - 1)IC_BLOCK_SIZE + 6) = REG16(add+ DC_BLOCK_SIZE - 16) + REG16(add + 2DC_BLOCK_SIZE + 14);`
246			`add += DC_SETS*DC_BLOCK_SIZE;`
247			`}`
248
249			`/* Fill cache with unused data */`
250			`add = base + DC_WAYSDC_SETSDC_BLOCK_SIZE;`
251			`for(i = 0; i < DC_WAYS; i++) {`
252			`ul = REG32(add);`
253			`ul = REG32(add + DC_BLOCK_SIZE);`
254			`ul = REG32(add + 2*DC_BLOCK_SIZE);`
255			`ul = REG32(add + 3*DC_BLOCK_SIZE);`
256			`add += DC_SETS*DC_BLOCK_SIZE;`
257			`}`
258
259			`/* Cache hit/miss r */`
260			`ul = 0;`
261			`add = base;`
262			`for(i = 0; i < DC_WAYS; i++) {`
263			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE) +`
264			`REG16(add + DC_BLOCK_SIZE - 4) +`
265			`REG16(add + 2);`
266			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 2) +`
267			`REG16(add + DC_BLOCK_SIZE - 8) +`
268			`REG16(add + DC_BLOCK_SIZE + 6);`
269			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 4) +`
270			`REG16(add + DC_BLOCK_SIZE - 12) +`
271			`REG16(add + 2*DC_BLOCK_SIZE + 10);`
272			`ul += REG16(add + (IC_SETS - 1)*IC_BLOCK_SIZE + 6) +`
273			`REG16(add+ DC_BLOCK_SIZE - 16) +`
274			`REG16(add + 2*DC_BLOCK_SIZE + 14);`
275			`add += DC_SETS*DC_BLOCK_SIZE;`
276			`}`
277
278	621	simons	`dc_disable();`
279	224	markom
280			`return ul;`
281			`}`
282
283			`int ic_test(void)`
284			`{`
285	322	simons	`int i;`
286			`unsigned long base, add;`
287
288	484	simons	`base = (((unsigned long)MEM_RAM / (IC_SETSIC_BLOCK_SIZE)) IC_SETSIC_BLOCK_SIZE) + IC_SETSIC_BLOCK_SIZE;`
289	349	simons
290	322	simons	`/* Copy jr to various location */`
291			`add = base;`
292			`for(i = 0; i < IC_WAYS; i++) {`
293			`copy_jr(add);`
294			`copy_jr(add + 2*IC_BLOCK_SIZE + 4);`
295			`copy_jr(add + 4*IC_BLOCK_SIZE + 8);`
296			`copy_jr(add + 6*IC_BLOCK_SIZE + 12);`
297
298			`copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);`
299			`copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);`
300			`copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);`
301			`copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);`
302			`add += IC_SETS*IC_BLOCK_SIZE;`
303			`}`
304
305			`/* Load execution table which starts at address 4 (at address 0 is table index) */`
306			`add = base;`
307			`for(i = 0; i < IC_WAYS; i++) {`
308			`/* Cache miss */`
309	484	simons	`jump_add[15i + 0] = add + 2IC_BLOCK_SIZE + 4;`
310			`jump_add[15i + 1] = add + 4IC_BLOCK_SIZE + 8;`
311			`jump_add[15i + 2] = add + 6IC_BLOCK_SIZE + 12;`
312	322	simons	`/* Cache hit/miss */`
313	484	simons	`jump_add[15*i + 3] = add;`
314			`jump_add[15i + 4] = add + (IC_SETS - 2)IC_BLOCK_SIZE + 0;`
315			`jump_add[15i + 5] = add + 2IC_BLOCK_SIZE + 4;`
316			`jump_add[15i + 6] = add + (IC_SETS - 4)IC_BLOCK_SIZE + 4;`
317			`jump_add[15i + 7] = add + 4IC_BLOCK_SIZE + 8;`
318			`jump_add[15i + 8] = add + (IC_SETS - 6)IC_BLOCK_SIZE + 8;`
319			`jump_add[15i + 9] = add + 6IC_BLOCK_SIZE + 12;`
320			`jump_add[15i + 10] = add + (IC_SETS - 8)IC_BLOCK_SIZE + 12;`
321	322	simons	`/* Cache hit */`
322	484	simons	`jump_add[15i + 11] = add + (IC_SETS - 2)IC_BLOCK_SIZE + 0;`
323			`jump_add[15i + 12] = add + (IC_SETS - 4)IC_BLOCK_SIZE + 4;`
324			`jump_add[15i + 13] = add + (IC_SETS - 6)IC_BLOCK_SIZE + 8;`
325			`jump_add[15i + 14] = add + (IC_SETS - 8)IC_BLOCK_SIZE + 12;`
326
327	322	simons	`add += IC_SETS*IC_BLOCK_SIZE;`
328			`}`
329
330			`/* Go home */`
331	484	simons	`jump_add[15*i] = (unsigned long)&jalr;`
332	322	simons
333			`/* Initilalize table index */`
334	621	simons	`jump_indx = (unsigned long)&jump_add[0];`
335	322	simons
336	621	simons	`ic_enable();`
337	349	simons
338	322	simons	`/* Go */`
339			`call(base);`
340
341	621	simons	`ic_disable();`
342	322	simons
343	621	simons	`return 0;`
344	224	markom	`}`
345
346			`int main(void)`
347			`{`
348	621	simons	`unsigned long rc, ret = 0;`
349	224	markom
350	621	simons	`#ifdef UART`
351			`/* Initialize controller */`
352			`uart_init();`
353			`#endif`
354
355			`#ifdef UART`
356			`print_str("DC test : ");`
357			`#endif`
358	224	markom	`rc = dc_test();`
359	621	simons	`ret += rc;`
360			`#ifdef UART`
361			`print_n(rc+0xdeaddca1);`
362			`print_str("\n");`
363			`#else`
364	224	markom	`report(rc + 0xdeaddca1);`
365	621	simons	`#endif`
366	224	markom
367	621	simons	`#ifndef OR1KSIM`
368			`#ifdef UART`
369			`print_str("DC invalidate test : ");`
370			`#endif`
371			`rc = dc_inv_test(MEM_RAM);`
372			`ret += rc;`
373			`#ifdef UART`
374			`print_n(rc + 0x9e8daa91);`
375			`print_str("\n");`
376			`#else`
377			`report(rc + 0x9e8daa91);`
378			`#endif`
379			`#endif`
380	224	markom
381	621	simons	`#ifdef UART`
382			`print_str("IC test : ");`
383			`#endif`
384	322	simons	`rc = ic_test();`
385	621	simons	`ret += rc;`
386			`#ifdef UART`
387			`print_n(rc + 0xdeaddead);`
388			`print_str("\n");`
389			`#else`
390			`report(rc + 0xdeaddead);`
391			`#endif`
392	574	markom
393	621	simons
394			`#ifndef OR1KSIM`
395			`#ifdef UART`
396			`print_str("IC invalidate test : ");`
397			`#endif`
398			`ic_enable();`
399			`rc = ic_inv_test();`
400			`ret += rc;`
401			`#ifdef UART`
402			`print_n(rc + 0xdeadde8f);`
403			`print_str("\n");`
404			`while(1);`
405			`#else`
406			`report(rc + 0xdeadde8f);`
407			`#endif`
408			`#endif`
409
410
411			`report(ret + 0xdeaddca1);`
412			`exit(0);`
413
414	574	markom	`return 0;`
415	224	markom	`}`
416
417			`/* just for size calculation */`
418			`void dummy()`
419			`{`
420			`}`

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.c] - Blame information for rev 621