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MEMORY
        {
        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
        flash  : ORIGIN = 0xf0000000, LENGTH = 0x00200000
        ram    : ORIGIN = 0x00002000, LENGTH = 0x001fe000
        }
 
SECTIONS
{
      .reset :
        {
        *(.reset)
         _src_beg = .;
        } > flash
      .text :
        AT ( ADDR (.reset) + SIZEOF (.reset) )
        {
        _dst_beg = .;
        *(.text)
        } > ram
      .data :
        AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
        {
        *(.data)
        *(.rodata)
        _dst_end = .;
        } > ram
      .bss :
        {
        *(.bss)
        } > ram
      .stack  ALIGN(0x10) (NOLOAD):
        {
        *(.stack)
        _ram_end = .;
        } > ram
}

Line No.	Rev	Author	Line
1	622	simons	`MEMORY`
2			`{`
3			`except : ORIGIN = 0x00000000, LENGTH = 0x00002000`
4	970	simons	`flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000`
5			`ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000`
6	622	simons	`}`
7
8			`SECTIONS`
9			`{`
10	970	simons	`.reset :`
11	622	simons	`{`
12	970	simons	`*(.reset)`
13			`_src_beg = .;`
14			`} > flash`
15			`.text :`
16			`AT ( ADDR (.reset) + SIZEOF (.reset) )`
17	622	simons	`{`
18	970	simons	`_dst_beg = .;`
19	622	simons	`*(.text)`
20			`} > ram`
21			`.data :`
22	970	simons	`AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )`
23	622	simons	`{`
24			`*(.data)`
25	970	simons	`*(.rodata)`
26	622	simons	`_dst_end = .;`
27			`} > ram`
28			`.bss :`
29			`{`
30			`*(.bss)`
31			`} > ram`
32			`.stack ALIGN(0x10) (NOLOAD):`
33			`{`
34			`*(.stack)`
35			`_ram_end = .;`
36			`} > ram`
37			`}`

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [cache.ld] - Blame information for rev 1782