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/* default.cfg -- Simulator testbench default configuration script file

   Copyright (C) 2001, Marko Mlinar, markom@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

section memory

  memory_table_file = "defaultmem.cfg"

  /*random_seed = 12345

  type = random*/

  pattern = 0x00

  type = unknown /* Fastest */

end

section cpu

  ver = 0x1200

  rev = 0x0001

  /* upr = */

  superscalar = 0

  hazards = 0

  dependstats = 0

  slp = 0

  btic = 0

  bpb = 0

end

section debug

  /*enabled = 0

  gdb_enabled = 0*/

  server_port = 9999

end

section sim

  debug = 0

  profile = 0

  prof_fn = "sim.profile"

  /* iprompt = 0 */

  exe_log = 0

  exe_log_fn = "executed.log"

end

section mc

  enabled = 0

  baseaddr = 0xa0000000

  POC = 0x00000008                 /* Power on configuration register */

end

section uart

  enabled = 0

  nuarts = 1

  device 0

    baseaddr = 0x80000000

    rxfile = "/tmp/uart0.rx"

    txfile = "/tmp/uart0.tx"

    jitter = -1                     /* async behaviour */

  enddevice

end

section dma

  enabled = 0

  ndmas = 1

  device 0

    baseaddr = 0x90000000

    irq = 4

  enddevice

end

section VAPI

  enabled = 0

  server_port = 9998

end

section ethernet

  enabled = 0

end

section tick

  enabled = 1

  irq = 3

end