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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [default.cfg] - Blame information for rev 532

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/* default.cfg -- Simulator testbench default configuration script file
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  nmemories = 2
  device 0
    name = "RAM"
    ce = 0
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
 
  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 2
    delayw = 4
  enddevice
end
 
section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
  btic = 0
  bpb = 0
end
 
section debug
  /*enabled = 0
  gdb_enabled = 0*/
  server_port = 9999
end
 
section sim
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  /* iprompt = 0 */
  exe_log = 0
  exe_log_fn = "executed.log"
end
 
section mc
  enabled = 0
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
section uart
  enabled = 0
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
 
section dma
  enabled = 0
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end
 
section VAPI
  enabled = 0
  server_port = 9998
end
 
section ethernet
  enabled = 0
end
 
section tick
  enabled = 1
  irq = 3
end

Line No.	Rev	Author	Line
1	311	markom	`/* default.cfg -- Simulator testbench default configuration script file`
2			`Copyright (C) 2001, Marko Mlinar, markom@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`section memory`
21			`/*random_seed = 12345`
22			`type = random*/`
23			`pattern = 0x00`
24			`type = unknown /* Fastest */`
25	424	markom
26			`nmemories = 2`
27			`device 0`
28			`name = "RAM"`
29			`ce = 0`
30			`baseaddr = 0x00000000`
31			`size = 0x00200000`
32			`delayr = 10`
33			`delayw = -1`
34			`enddevice`
35
36			`device 1`
37			`name = "FLASH"`
38			`ce = 1`
39			`baseaddr = 0x40000000`
40			`size = 0x00200000`
41			`delayr = 2`
42			`delayw = 4`
43			`enddevice`
44	311	markom	`end`
45
46			`section cpu`
47			`ver = 0x1200`
48			`rev = 0x0001`
49			`/* upr = */`
50			`superscalar = 0`
51			`hazards = 0`
52			`dependstats = 0`
53			`btic = 0`
54			`bpb = 0`
55			`end`
56
57			`section debug`
58			`/*enabled = 0`
59			`gdb_enabled = 0*/`
60			`server_port = 9999`
61			`end`
62
63			`section sim`
64	409	markom	`debug = 0`
65	311	markom	`profile = 0`
66			`prof_fn = "sim.profile"`
67
68			`/* iprompt = 0 */`
69			`exe_log = 0`
70			`exe_log_fn = "executed.log"`
71			`end`
72
73			`section mc`
74			`enabled = 0`
75			`baseaddr = 0xa0000000`
76			`POC = 0x00000008 /* Power on configuration register */`
77			`end`
78
79			`section uart`
80			`enabled = 0`
81			`nuarts = 1`
82
83			`device 0`
84			`baseaddr = 0x80000000`
85			`rxfile = "/tmp/uart0.rx"`
86			`txfile = "/tmp/uart0.tx"`
87			`jitter = -1 /* async behaviour */`
88			`enddevice`
89			`end`
90
91			`section dma`
92			`enabled = 0`
93			`ndmas = 1`
94
95			`device 0`
96			`baseaddr = 0x90000000`
97			`irq = 4`
98			`enddevice`
99			`end`
100
101			`section VAPI`
102			`enabled = 0`
103			`server_port = 9998`
104			`end`
105
106			`section ethernet`
107			`enabled = 0`
108			`end`
109	332	markom
110			`section tick`
111			`enabled = 1`
112			`irq = 3`
113			`end`

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [default.cfg] - Blame information for rev 532