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/* Support file for c based tests */
 
#include "spr_defs.h"
 
#define reset _main
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .stack
        .space 0x1000
_stack:
 
  .section .except, "ax"
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
 
        .org    0x100
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r1,hi(_stack)
        l.ori   r1,r1,lo(_stack)
 
        /* Check if this is RTL version */
        l.lbz   r3,0(r0)
        l.sfeqi r3,0xff
        l.bf    2f
        l.nop
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
 
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
        .org    0x200
_buserr_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.lwz   r10,0x0(r10)
        l.jr    r10
        l.nop
 
        .org    0x300
_dpfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x400
_ipfault_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x500
_tick_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x600
_align_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x700
_illinsn_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x800
_int_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0x900
_dtlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xa00
_itlbmiss_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xb00
_range_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xc00
_syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
        .org    0xd00
_break_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
        .org    0xe00
_trap_vector:
        l.addi  r1,r1,-116
        l.sw    0x18(r1),r9
        l.jal   store_regs
        l.nop
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
store_regs:
        l.sw    0x00(r1),r3
        l.sw    0x04(r1),r4
        l.sw    0x08(r1),r5
        l.sw    0x0c(r1),r6
        l.sw    0x10(r1),r7
        l.sw    0x14(r1),r8
        l.sw    0x1c(r1),r10
        l.sw    0x20(r1),r11
        l.sw    0x24(r1),r12
        l.sw    0x28(r1),r13
        l.sw    0x2c(r1),r14
        l.sw    0x30(r1),r15
        l.sw    0x34(r1),r16
        l.sw    0x38(r1),r17
        l.sw    0x3c(r1),r18
        l.sw    0x40(r1),r19
        l.sw    0x44(r1),r20
        l.sw    0x48(r1),r21
        l.sw    0x4c(r1),r22
        l.sw    0x50(r1),r23
        l.sw    0x54(r1),r24
        l.sw    0x58(r1),r25
        l.sw    0x5c(r1),r26
        l.sw    0x60(r1),r27
        l.sw    0x64(r1),r28
        l.sw    0x68(r1),r29
        l.sw    0x6c(r1),r30
        l.sw    0x70(r1),r31
        l.jr    r9
        l.nop
 
end_except:
        l.lwz   r3,0x00(r1)
        l.lwz   r4,0x04(r1)
        l.lwz   r5,0x08(r1)
        l.lwz   r6,0x0c(r1)
        l.lwz   r7,0x10(r1)
        l.lwz   r8,0x14(r1)
        l.lwz   r9,0x18(r1)
        l.lwz   r10,0x1c(r1)
        l.lwz   r11,0x20(r1)
        l.lwz   r12,0x24(r1)
        l.lwz   r13,0x28(r1)
        l.lwz   r14,0x2c(r1)
        l.lwz   r15,0x30(r1)
        l.lwz   r16,0x34(r1)
        l.lwz   r17,0x38(r1)
        l.lwz   r18,0x3c(r1)
        l.lwz   r19,0x40(r1)
        l.lwz   r20,0x44(r1)
        l.lwz   r21,0x48(r1)
        l.lwz   r22,0x4c(r1)
        l.lwz   r23,0x50(r1)
        l.lwz   r24,0x54(r1)
        l.lwz   r25,0x58(r1)
        l.lwz   r26,0x5c(r1)
        l.lwz   r27,0x60(r1)
        l.lwz   r28,0x64(r1)
        l.lwz   r29,0x68(r1)
        l.lwz   r30,0x6c(r1)
        l.lwz   r31,0x70(r1)
        l.addi  r1,r1,116
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [except_test_s.S] - Blame information for rev 956

Line No.	Rev	Author	Line
1	519	simons	`/* Support file for c based tests */`
2
3			`#include "spr_defs.h"`
4
5			`#define reset _main`
6
7			`.global _except_basic`
8			`.global _lo_dmmu_en`
9			`.global _lo_immu_en`
10			`.global _call`
11			`.global _call_with_int`
12			`.global _load_acc_32`
13			`.global _load_acc_16`
14			`.global _store_acc_32`
15			`.global _store_acc_16`
16			`.global _load_b_acc_32`
17			`.global _trap`
18			`.global _b_trap`
19			`.global _range`
20			`.global _b_range`
21			`.global _int_trigger`
22			`.global _int_loop`
23			`.global _jump_back`
24
25			`.section .stack`
26			`.space 0x1000`
27			`_stack:`
28
29	956	simons	`.section .except, "ax"`
30	519	simons	`.extern _reset_support`
31			`.extern _c_reset`
32			`.extern _excpt_buserr`
33			`.extern _excpt_dpfault`
34			`.extern _excpt_ipfault`
35	600	simons	`.extern _excpt_tick`
36	519	simons	`.extern _excpt_align`
37			`.extern _excpt_illinsn`
38	600	simons	`.extern _excpt_int`
39	519	simons	`.extern _excpt_dtlbmiss`
40			`.extern _excpt_itlbmiss`
41			`.extern _excpt_range`
42			`.extern _excpt_syscall`
43			`.extern _excpt_break`
44			`.extern _excpt_trap`
45
46
47			`.org 0x100`
48			`_reset_vector:`
49			`l.nop`
50			`l.nop`
51			`l.addi r2,r0,0x0`
52			`l.addi r3,r0,0x0`
53			`l.addi r4,r0,0x0`
54			`l.addi r5,r0,0x0`
55			`l.addi r6,r0,0x0`
56			`l.addi r7,r0,0x0`
57			`l.addi r8,r0,0x0`
58			`l.addi r9,r0,0x0`
59			`l.addi r10,r0,0x0`
60			`l.addi r11,r0,0x0`
61			`l.addi r12,r0,0x0`
62			`l.addi r13,r0,0x0`
63			`l.addi r14,r0,0x0`
64			`l.addi r15,r0,0x0`
65			`l.addi r16,r0,0x0`
66			`l.addi r17,r0,0x0`
67			`l.addi r18,r0,0x0`
68			`l.addi r19,r0,0x0`
69			`l.addi r20,r0,0x0`
70			`l.addi r21,r0,0x0`
71			`l.addi r22,r0,0x0`
72			`l.addi r23,r0,0x0`
73			`l.addi r24,r0,0x0`
74			`l.addi r25,r0,0x0`
75			`l.addi r26,r0,0x0`
76			`l.addi r27,r0,0x0`
77			`l.addi r28,r0,0x0`
78			`l.addi r29,r0,0x0`
79			`l.addi r30,r0,0x0`
80			`l.addi r31,r0,0x0`
81
82			`l.movhi r1,hi(_stack)`
83			`l.ori r1,r1,lo(_stack)`
84
85			`/* Check if this is RTL version */`
86			`l.lbz r3,0(r0)`
87			`l.sfeqi r3,0xff`
88			`l.bf 2f`
89			`l.nop`
90			`l.movhi r3,hi(_src_beg)`
91			`l.ori r3,r3,lo(_src_beg)`
92			`l.movhi r4,hi(_dst_beg)`
93			`l.ori r4,r4,lo(_dst_beg)`
94			`l.movhi r5,hi(_dst_end)`
95			`l.ori r5,r5,lo(_dst_end)`
96			`l.sub r5,r5,r4`
97			`l.sfeqi r5,0`
98			`l.bf 2f`
99			`l.nop`
100			`1: l.lwz r6,0(r3)`
101			`l.sw 0(r4),r6`
102			`l.addi r3,r3,4`
103			`l.addi r4,r4,4`
104			`l.addi r5,r5,-4`
105			`l.sfgtsi r5,0`
106			`l.bf 1b`
107			`l.nop`
108
109			`2:`
110
111			`l.movhi r2,hi(reset)`
112			`l.ori r2,r2,lo(reset)`
113			`l.jr r2`
114			`l.nop`
115
116			`.org 0x200`
117			`_buserr_vector:`
118			`l.addi r1,r1,-116`
119			`l.sw 0x18(r1),r9`
120			`l.jal store_regs`
121			`l.nop`
122
123			`l.mfspr r3,r0,SPR_EPCR_BASE`
124			`l.movhi r4,hi(_except_pc)`
125			`l.ori r4,r4,lo(_except_pc)`
126			`l.sw 0(r4),r3`
127
128			`l.mfspr r3,r0,SPR_EEAR_BASE`
129			`l.movhi r4,hi(_except_ea)`
130			`l.ori r4,r4,lo(_except_ea)`
131			`l.sw 0(r4),r3`
132
133			`l.movhi r9,hi(end_except)`
134			`l.ori r9,r9,lo(end_except)`
135			`l.movhi r10,hi(_excpt_buserr)`
136			`l.ori r10,r10,lo(_excpt_buserr)`
137			`l.lwz r10,0x0(r10)`
138			`l.jr r10`
139			`l.nop`
140
141			`.org 0x300`
142			`_dpfault_vector:`
143			`l.addi r1,r1,-116`
144			`l.sw 0x18(r1),r9`
145			`l.jal store_regs`
146			`l.nop`
147
148			`l.mfspr r3,r0,SPR_EPCR_BASE`
149			`l.movhi r4,hi(_except_pc)`
150			`l.ori r4,r4,lo(_except_pc)`
151			`l.sw 0(r4),r3`
152
153			`l.mfspr r3,r0,SPR_EEAR_BASE`
154			`l.movhi r4,hi(_except_ea)`
155			`l.ori r4,r4,lo(_except_ea)`
156			`l.sw 0(r4),r3`
157
158			`l.movhi r9,hi(end_except)`
159			`l.ori r9,r9,lo(end_except)`
160			`l.movhi r10,hi(_excpt_dpfault)`
161			`l.ori r10,r10,lo(_excpt_dpfault)`
162			`l.lwz r10,0(r10)`
163			`l.jr r10`
164			`l.nop`
165
166			`.org 0x400`
167			`_ipfault_vector:`
168			`l.addi r1,r1,-116`
169			`l.sw 0x18(r1),r9`
170			`l.jal store_regs`
171			`l.nop`
172
173			`l.mfspr r3,r0,SPR_EPCR_BASE`
174			`l.movhi r4,hi(_except_pc)`
175			`l.ori r4,r4,lo(_except_pc)`
176			`l.sw 0(r4),r3`
177
178			`l.mfspr r3,r0,SPR_EEAR_BASE`
179			`l.movhi r4,hi(_except_ea)`
180			`l.ori r4,r4,lo(_except_ea)`
181			`l.sw 0(r4),r3`
182
183			`l.movhi r9,hi(end_except)`
184			`l.ori r9,r9,lo(end_except)`
185			`l.movhi r10,hi(_excpt_ipfault)`
186			`l.ori r10,r10,lo(_excpt_ipfault)`
187			`l.lwz r10,0(r10)`
188			`l.jr r10`
189			`l.nop`
190
191			`.org 0x500`
192	600	simons	`_tick_vector:`
193	519	simons	`l.addi r1,r1,-116`
194			`l.sw 0x18(r1),r9`
195			`l.jal store_regs`
196			`l.nop`
197
198			`l.mfspr r3,r0,SPR_EPCR_BASE`
199			`l.movhi r4,hi(_except_pc)`
200			`l.ori r4,r4,lo(_except_pc)`
201			`l.sw 0(r4),r3`
202
203			`l.mfspr r3,r0,SPR_EEAR_BASE`
204			`l.movhi r4,hi(_except_ea)`
205			`l.ori r4,r4,lo(_except_ea)`
206			`l.sw 0(r4),r3`
207
208			`l.movhi r9,hi(end_except)`
209			`l.ori r9,r9,lo(end_except)`
210	600	simons	`l.movhi r10,hi(_excpt_tick)`
211			`l.ori r10,r10,lo(_excpt_tick)`
212	519	simons	`l.lwz r10,0(r10)`
213			`l.jr r10`
214			`l.nop`
215
216			`.org 0x600`
217			`_align_vector:`
218			`l.addi r1,r1,-116`
219			`l.sw 0x18(r1),r9`
220			`l.jal store_regs`
221			`l.nop`
222
223			`l.mfspr r3,r0,SPR_EPCR_BASE`
224			`l.movhi r4,hi(_except_pc)`
225			`l.ori r4,r4,lo(_except_pc)`
226			`l.sw 0(r4),r3`
227
228			`l.mfspr r3,r0,SPR_EEAR_BASE`
229			`l.movhi r4,hi(_except_ea)`
230			`l.ori r4,r4,lo(_except_ea)`
231			`l.sw 0(r4),r3`
232
233			`l.movhi r9,hi(end_except)`
234			`l.ori r9,r9,lo(end_except)`
235			`l.movhi r10,hi(_excpt_align)`
236			`l.ori r10,r10,lo(_excpt_align)`
237			`l.lwz r10,0(r10)`
238			`l.jr r10`
239			`l.nop`
240
241			`.org 0x700`
242			`_illinsn_vector:`
243			`l.addi r1,r1,-116`
244			`l.sw 0x18(r1),r9`
245			`l.jal store_regs`
246			`l.nop`
247
248			`l.mfspr r3,r0,SPR_EPCR_BASE`
249			`l.movhi r4,hi(_except_pc)`
250			`l.ori r4,r4,lo(_except_pc)`
251			`l.sw 0(r4),r3`
252
253			`l.mfspr r3,r0,SPR_EEAR_BASE`
254			`l.movhi r4,hi(_except_ea)`
255			`l.ori r4,r4,lo(_except_ea)`
256			`l.sw 0(r4),r3`
257
258			`l.movhi r9,hi(end_except)`
259			`l.ori r9,r9,lo(end_except)`
260			`l.movhi r10,hi(_excpt_illinsn)`
261			`l.ori r10,r10,lo(_excpt_illinsn)`
262			`l.lwz r10,0(r10)`
263			`l.jr r10`
264			`l.nop`
265
266			`.org 0x800`
267	600	simons	`_int_vector:`
268	519	simons	`l.addi r1,r1,-116`
269			`l.sw 0x18(r1),r9`
270			`l.jal store_regs`
271			`l.nop`
272
273			`l.mfspr r3,r0,SPR_EPCR_BASE`
274			`l.movhi r4,hi(_except_pc)`
275			`l.ori r4,r4,lo(_except_pc)`
276			`l.sw 0(r4),r3`
277
278			`l.mfspr r3,r0,SPR_EEAR_BASE`
279			`l.movhi r4,hi(_except_ea)`
280			`l.ori r4,r4,lo(_except_ea)`
281			`l.sw 0(r4),r3`
282
283			`l.movhi r9,hi(end_except)`
284			`l.ori r9,r9,lo(end_except)`
285	600	simons	`l.movhi r10,hi(_excpt_int)`
286			`l.ori r10,r10,lo(_excpt_int)`
287	519	simons	`l.lwz r10,0(r10)`
288			`l.jr r10`
289			`l.nop`
290
291			`.org 0x900`
292			`_dtlbmiss_vector:`
293			`l.addi r1,r1,-116`
294			`l.sw 0x18(r1),r9`
295			`l.jal store_regs`
296			`l.nop`
297
298			`l.mfspr r3,r0,SPR_EPCR_BASE`
299			`l.movhi r4,hi(_except_pc)`
300			`l.ori r4,r4,lo(_except_pc)`
301			`l.sw 0(r4),r3`
302
303			`l.mfspr r3,r0,SPR_EEAR_BASE`
304			`l.movhi r4,hi(_except_ea)`
305			`l.ori r4,r4,lo(_except_ea)`
306			`l.sw 0(r4),r3`
307
308			`l.movhi r9,hi(end_except)`
309			`l.ori r9,r9,lo(end_except)`
310			`l.movhi r10,hi(_excpt_dtlbmiss)`
311			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
312			`l.lwz r10,0(r10)`
313			`l.jr r10`
314			`l.nop`
315
316			`.org 0xa00`
317			`_itlbmiss_vector:`
318			`l.addi r1,r1,-116`
319			`l.sw 0x18(r1),r9`
320			`l.jal store_regs`
321			`l.nop`
322
323			`l.mfspr r3,r0,SPR_EPCR_BASE`
324			`l.movhi r4,hi(_except_pc)`
325			`l.ori r4,r4,lo(_except_pc)`
326			`l.sw 0(r4),r3`
327
328			`l.mfspr r3,r0,SPR_EEAR_BASE`
329			`l.movhi r4,hi(_except_ea)`
330			`l.ori r4,r4,lo(_except_ea)`
331			`l.sw 0(r4),r3`
332
333			`l.movhi r9,hi(end_except)`
334			`l.ori r9,r9,lo(end_except)`
335			`l.movhi r10,hi(_excpt_itlbmiss)`
336			`l.ori r10,r10,lo(_excpt_itlbmiss)`
337			`l.lwz r10,0(r10)`
338			`l.jr r10`
339			`l.nop`
340
341			`.org 0xb00`
342			`_range_vector:`
343			`l.addi r1,r1,-116`
344			`l.sw 0x18(r1),r9`
345			`l.jal store_regs`
346			`l.nop`
347
348			`l.mfspr r3,r0,SPR_EPCR_BASE`
349			`l.movhi r4,hi(_except_pc)`
350			`l.ori r4,r4,lo(_except_pc)`
351			`l.sw 0(r4),r3`
352
353			`l.mfspr r3,r0,SPR_EEAR_BASE`
354			`l.movhi r4,hi(_except_ea)`
355			`l.ori r4,r4,lo(_except_ea)`
356			`l.sw 0(r4),r3`
357
358			`l.movhi r9,hi(end_except)`
359			`l.ori r9,r9,lo(end_except)`
360			`l.movhi r10,hi(_excpt_range)`
361			`l.ori r10,r10,lo(_excpt_range)`
362			`l.lwz r10,0(r10)`
363			`l.jr r10`
364			`l.nop`
365
366			`.org 0xc00`
367			`_syscall_vector:`
368			`l.addi r3,r3,4`
369
370			`l.mfspr r4,r0,SPR_SR`
371			`l.andi r4,r4,7`
372			`l.add r6,r0,r4`
373
374			`l.mfspr r4,r0,SPR_EPCR_BASE`
375			`l.movhi r5,hi(_sys1)`
376			`l.ori r5,r5,lo(_sys1)`
377			`l.sub r5,r4,r5`
378
379			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
380	600	simons	`l.ori r4,r4,SPR_SR_SM`
381	519	simons	`l.mtspr r0,r4,SPR_ESR_BASE`
382
383			`l.movhi r4,hi(_sys2)`
384			`l.ori r4,r4,lo(_sys2)`
385			`l.mtspr r0,r4,SPR_EPCR_BASE`
386
387			`l.rfe`
388			`l.addi r3,r3,8`
389
390			`.org 0xd00`
391			`_break_vector:`
392			`l.addi r1,r1,-116`
393			`l.sw 0x18(r1),r9`
394			`l.jal store_regs`
395			`l.nop`
396
397			`l.mfspr r3,r0,SPR_EPCR_BASE`
398			`l.movhi r4,hi(_except_pc)`
399			`l.ori r4,r4,lo(_except_pc)`
400			`l.sw 0(r4),r3`
401
402			`l.mfspr r3,r0,SPR_EEAR_BASE`
403			`l.movhi r4,hi(_except_ea)`
404			`l.ori r4,r4,lo(_except_ea)`
405			`l.sw 0(r4),r3`
406
407			`l.movhi r9,hi(end_except)`
408			`l.ori r9,r9,lo(end_except)`
409			`l.movhi r10,hi(_excpt_break)`
410			`l.ori r10,r10,lo(_excpt_break)`
411			`l.lwz r10,0(r10)`
412			`l.jr r10`
413			`l.nop`
414
415			`.org 0xe00`
416			`_trap_vector:`
417			`l.addi r1,r1,-116`
418			`l.sw 0x18(r1),r9`
419			`l.jal store_regs`
420			`l.nop`
421
422			`l.mfspr r3,r0,SPR_EPCR_BASE`
423			`l.movhi r4,hi(_except_pc)`
424			`l.ori r4,r4,lo(_except_pc)`
425			`l.sw 0(r4),r3`
426
427			`l.mfspr r3,r0,SPR_EEAR_BASE`
428			`l.movhi r4,hi(_except_ea)`
429			`l.ori r4,r4,lo(_except_ea)`
430			`l.sw 0(r4),r3`
431
432			`l.movhi r9,hi(end_except)`
433			`l.ori r9,r9,lo(end_except)`
434			`l.movhi r10,hi(_excpt_trap)`
435			`l.ori r10,r10,lo(_excpt_trap)`
436			`l.lwz r10,0(r10)`
437			`l.jr r10`
438			`l.nop`
439
440			`store_regs:`
441			`l.sw 0x00(r1),r3`
442			`l.sw 0x04(r1),r4`
443			`l.sw 0x08(r1),r5`
444			`l.sw 0x0c(r1),r6`
445			`l.sw 0x10(r1),r7`
446			`l.sw 0x14(r1),r8`
447			`l.sw 0x1c(r1),r10`
448			`l.sw 0x20(r1),r11`
449			`l.sw 0x24(r1),r12`
450			`l.sw 0x28(r1),r13`
451			`l.sw 0x2c(r1),r14`
452			`l.sw 0x30(r1),r15`
453			`l.sw 0x34(r1),r16`
454			`l.sw 0x38(r1),r17`
455			`l.sw 0x3c(r1),r18`
456			`l.sw 0x40(r1),r19`
457			`l.sw 0x44(r1),r20`
458			`l.sw 0x48(r1),r21`
459			`l.sw 0x4c(r1),r22`
460			`l.sw 0x50(r1),r23`
461			`l.sw 0x54(r1),r24`
462			`l.sw 0x58(r1),r25`
463			`l.sw 0x5c(r1),r26`
464			`l.sw 0x60(r1),r27`
465			`l.sw 0x64(r1),r28`
466			`l.sw 0x68(r1),r29`
467			`l.sw 0x6c(r1),r30`
468			`l.sw 0x70(r1),r31`
469			`l.jr r9`
470			`l.nop`
471
472			`end_except:`
473			`l.lwz r3,0x00(r1)`
474			`l.lwz r4,0x04(r1)`
475			`l.lwz r5,0x08(r1)`
476			`l.lwz r6,0x0c(r1)`
477			`l.lwz r7,0x10(r1)`
478			`l.lwz r8,0x14(r1)`
479			`l.lwz r9,0x18(r1)`
480			`l.lwz r10,0x1c(r1)`
481			`l.lwz r11,0x20(r1)`
482			`l.lwz r12,0x24(r1)`
483			`l.lwz r13,0x28(r1)`
484			`l.lwz r14,0x2c(r1)`
485			`l.lwz r15,0x30(r1)`
486			`l.lwz r16,0x34(r1)`
487			`l.lwz r17,0x38(r1)`
488			`l.lwz r18,0x3c(r1)`
489			`l.lwz r19,0x40(r1)`
490			`l.lwz r20,0x44(r1)`
491			`l.lwz r21,0x48(r1)`
492			`l.lwz r22,0x4c(r1)`
493			`l.lwz r23,0x50(r1)`
494			`l.lwz r24,0x54(r1)`
495			`l.lwz r25,0x58(r1)`
496			`l.lwz r26,0x5c(r1)`
497			`l.lwz r27,0x60(r1)`
498			`l.lwz r28,0x64(r1)`
499			`l.lwz r29,0x68(r1)`
500			`l.lwz r30,0x6c(r1)`
501			`l.lwz r31,0x70(r1)`
502			`l.addi r1,r1,116`
503			`l.mtspr r0,r9,SPR_EPCR_BASE`
504			`l.rfe`
505			`l.nop`
506
507			`.section .text`
508
509			`_except_basic:`
510			`_sys1:`
511			`l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */`
512			`l.mfspr r4,r0,SPR_SR`
513			`l.and r4,r4,r3`
514	600	simons	`l.ori r4,r4,(SPR_SR_IEE\|SPR_SR_TEE)`
515	519	simons	`l.mtspr r0,r4,SPR_SR`
516
517			`l.addi r3,r0,0`
518			`l.sys 1`
519			`l.addi r3,r3,2`
520
521			`_sys2:`
522			`l.addi r11,r0,0`
523
524			`l.mfspr r4,r0,SPR_SR /* Check SR */`
525	600	simons	`l.andi r4,r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
526			`l.sfeqi r4,(SPR_SR_IEE\|SPR_SR_TEE\|SPR_SR_SM)`
527	519	simons	`l.bf 1f`
528			`l.nop`
529			`l.addi r11,r11,1`
530			`1:`
531			`l.sfeqi r3,4 /* Check if l.sys or l.rfe has delay slot */`
532			`l.bf 1f`
533			`l.nop`
534			`l.addi r11,r11,2`
535			`1:`
536			`l.sfeqi r5,0x1c /* Check the EPCR */`
537			`l.bf 1f`
538			`l.nop`
539			`l.addi r11,r11,4`
540			`1:`
541	600	simons	`l.sfeqi r6,SPR_SR_SM /* Check the SR when exception is taken */`
542	519	simons	`l.bf 1f`
543			`l.nop`
544			`l.addi r11,r11,8`
545			`1:`
546			`l.jr r9`
547			`l.nop`
548
549			`_lo_dmmu_en:`
550			`l.mfspr r3,r0,SPR_SR`
551			`l.ori r3,r3,SPR_SR_DME`
552			`l.mtspr r0,r3,SPR_ESR_BASE`
553			`l.mtspr r0,r9,SPR_EPCR_BASE`
554			`l.rfe`
555			`l.nop`
556
557			`_lo_immu_en:`
558			`l.mfspr r3,r0,SPR_SR`
559			`l.ori r3,r3,SPR_SR_IME`
560			`l.mtspr r0,r3,SPR_ESR_BASE`
561			`l.mtspr r0,r9,SPR_EPCR_BASE`
562			`l.rfe`
563			`l.nop`
564
565			`_call:`
566	522	simons	`l.addi r11,r0,0`
567	519	simons	`l.jr r3`
568			`l.nop`
569
570			`_call_with_int:`
571			`l.mfspr r8,r0,SPR_SR`
572	600	simons	`l.ori r8,r8,SPR_SR_TEE`
573	519	simons	`l.mtspr r0,r8,SPR_ESR_BASE`
574			`l.mtspr r0,r3,SPR_EPCR_BASE`
575			`l.rfe`
576
577			`_load_acc_32:`
578			`l.movhi r11,hi(0x12345678)`
579			`l.ori r11,r11,lo(0x12345678)`
580			`l.lwz r11,0(r4)`
581			`l.jr r9`
582			`l.nop`
583
584			`_load_acc_16:`
585			`l.movhi r11,hi(0x12345678)`
586			`l.ori r11,r11,lo(0x12345678)`
587			`l.lhz r11,0(r4)`
588			`l.jr r9`
589			`l.nop`
590
591			`_store_acc_32:`
592			`l.movhi r3,hi(0x12345678)`
593			`l.ori r3,r3,lo(0x12345678)`
594			`l.sw 0(r4),r3`
595			`l.jr r9`
596			`l.nop`
597
598			`_store_acc_16:`
599			`l.movhi r3,hi(0x12345678)`
600			`l.ori r3,r3,lo(0x12345678)`
601			`l.sh 0(r4),r3`
602			`l.jr r9`
603			`l.nop`
604
605			`_load_b_acc_32:`
606			`l.movhi r11,hi(0x12345678)`
607			`l.ori r11,r11,lo(0x12345678)`
608			`l.jr r9`
609			`l.lwz r11,0(r4)`
610
611			`_b_trap:`
612			`l.jr r9`
613			`_trap:`
614			`l.trap 1`
615	608	simons	`l.jr r9`
616	519	simons	`l.nop`
617
618			`_b_range:`
619			`l.jr r9`
620			`_range:`
621			`l.addi r3,r0,-1`
622	608	simons	`l.jr r9`
623	519	simons	`l.nop`
624
625			`_int_trigger:`
626			`l.addi r11,r0,0`
627			`l.mfspr r3,r0,SPR_SR`
628	600	simons	`l.ori r3,r3,SPR_SR_TEE`
629	519	simons	`l.mtspr r0,r3,SPR_SR`
630			`l.addi r11,r11,1`
631
632			`_int_loop:`
633			`l.j _int_loop`
634			`l.lwz r5,0(r4);`
635
636			`_jump_back:`
637			`l.addi r11,r0,0`
638			`l.jr r9`
639			`l.addi r11,r11,1`
640