OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [mc_dram.c] - Blame information for rev 454

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 454 ivang 
/* mc_dram.c - Memory Controller testbench dram test
2 
         Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
3 
 
4 
         This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
         This program is free software; you can redistribute it and/or modify
7 
         it under the terms of the GNU General Public License as published by
8 
         the Free Software Foundation; either version 2 of the License, or
9 
         (at your option) any later version.
10 
 
11 
         This program is distributed in the hope that it will be useful,
12 
         but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
14 
         GNU General Public License for more details.
15 
 
16 
         You should have received a copy of the GNU General Public License
17 
         along with this program; if not, write to the Free Software
18 
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 
*/
20 
 
21 
#include "support.h"
22 
 
23 
#include "mc_common.h"
24 
#include "mc_dram.h"
25 
#include "../peripheral/mc.h"
26 
#include "../peripheral/fields.h"
27 
 
28 
typedef volatile unsigned long *REGISTER;
29 
 
30 
unsigned long nRowSize = 0;
31 
unsigned long nColumns = 0;
32 
REGISTER mc_poc        = (unsigned long*)(MC_BASE + MC_POC);
33 
REGISTER mc_csr        = (unsigned long*)(MC_BASE + MC_CSR);
34 
REGISTER mc_ba_mask    = (unsigned long*)(MC_BASE + MC_BA_MASK);
35 
 
36 
unsigned long lpoc;
37 
 
38 
unsigned long set_config()
39 
{
40 
    REGISTER mc_csc;
41 
    unsigned char ch;
42 
 
43 
    lpoc = *mc_poc;
44 
 
45 
    for (ch=0; ch<8; ch++) {
46 
        if (MC_SDRAM_CSMASK & (0x01 << ch) ) {
47 
            mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
48 
            SET_FIELD(*mc_csc, MC_CSC, MS,  mc_sdram_cs[ch].MS);
49 
            SET_FIELD(*mc_csc, MC_CSC, BW,  mc_sdram_cs[ch].BW);
50 
            SET_FIELD(*mc_csc, MC_CSC, SEL, mc_sdram_cs[ch].M);
51 
            SET_FLAG(*mc_csc, MC_CSC, EN);
52 
            printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
53 
        }
54 
    }
55 
 
56 
    return 0;
57 
}
58 
 
59 
int main()
60 
{
61 
    unsigned long ret;
62 
    unsigned char ch;
63 
 
64 
    unsigned long j, i;
65 
    unsigned long test;
66 
 
67 
    unsigned long nRowSize = 0;
68 
    unsigned long nRows    = 0;
69 
    unsigned long nRowSh   = 0;
70 
    unsigned long nRowGrp  = 0;
71 
    unsigned long nGroups  = 0;
72 
 
73 
    unsigned long nAddress;
74 
    unsigned long mc_sel;
75 
    REGISTER mc_tms;
76 
    REGISTER mc_cs;
77 
 
78 
    /* set configuration */
79 
    randomin(7435);
80 
    /*
81 
    if ( (ret = set_config()) != 0) {
82 
        exit(ret);
83 
    }
84 
    */
85 
 
86 
    for (ch=0; ch<8; ch++) {
87 
        if (MC_SDRAM_CSMASK & (0x01 << ch) ) {
88 
            printf ("--- Begin Test on CS%d ---\n", ch);
89 
 
90 
            mc_cs  = (unsigned long*)(MC_BASE + MC_CSC(ch));
91 
            mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
92 
            mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
93 
 
94 
            SET_FIELD(*mc_tms, MC_TMS_SDRAM, OM, 0); /*normal op*/
95 
            SET_FIELD(*mc_tms, MC_TMS_SDRAM, CL, 3); /*CAS*/
96 
 
97 
            switch ( mc_sdram_cs[ch].BW + (3 * mc_sdram_cs[ch].MS) ) {
98 
            case 0:
99 
            case 4:
100 
                nRowSize = MC_SDRAM_ROWSIZE_0;
101 
                nRows    = MC_SDRAM_ROWS_0;
102 
                nRowSh   = MC_SDRAM_ROWSH_0; break;
103 
            case 1:
104 
            case 5:
105 
                nRowSize = MC_SDRAM_ROWSIZE_1;
106 
                nRows    = MC_SDRAM_ROWS_1;
107 
                nRowSh   = MC_SDRAM_ROWSH_1; break;
108 
            case 2:
109 
                nRowSize = MC_SDRAM_ROWSIZE_2;
110 
                nRows    = MC_SDRAM_ROWS_2;
111 
                nRowSh   = MC_SDRAM_ROWSH_2;  break;
112 
            case 3:
113 
                nRowSize = MC_SDRAM_ROWSIZE_3;
114 
                nRows    = MC_SDRAM_ROWS_3;
115 
                nRowSh   = MC_SDRAM_ROWSH_3; break;
116 
            case 6:
117 
                nRowSize = MC_SDRAM_ROWSIZE_6;
118 
                nRows    = MC_SDRAM_ROWS_6;
119 
                nRowSh   = MC_SDRAM_ROWSH_6; break;
120 
            case 7:
121 
                nRowSize = MC_SDRAM_ROWSIZE_7;
122 
                nRows    = MC_SDRAM_ROWS_7;
123 
                nRowSh   = MC_SDRAM_ROWSH_7; break;
124 
            case 8:
125 
                nRowSize = MC_SDRAM_ROWSIZE_8;
126 
                nRows    = MC_SDRAM_ROWS_8;
127 
                nRowSh   = MC_SDRAM_ROWSH_8; break;
128 
            }
129 
 
130 
            printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lX, rs = %lu, nr = %lu, sh = %lu, sel = %lu\n",
131 
                    *mc_cs, *mc_tms, nRowSize, nRows, nRowSh, mc_sel);
132 
 
133 
            nRows -= MC_SDRAM_ROW_OFF;
134 
            for (test=0; test<16; test++) {
135 
                /* configure MC*/
136 
                CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
137 
                CLEAR_FLAG(*mc_cs, MC_CSC, KRO); /* close row */
138 
                CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
139 
                CLEAR_FLAG(*mc_cs, MC_CSC, WP);  /* write enable */
140 
                SET_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* single loc access */
141 
                CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* sequential burst */
142 
                SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 0); /* 1 */
143 
                switch (test) {
144 
                case 0:
145 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST0) != MC_SDRAM_TEST0)
146 
                        continue;
147 
                    break;
148 
                case 1:
149 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST1) != MC_SDRAM_TEST1)
150 
                        continue;
151 
                    SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
152 
                    break;
153 
                case 2:
154 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST2) != MC_SDRAM_TEST2)
155 
                        continue;
156 
                    SET_FLAG(*mc_cs, MC_CSC, KRO); /* keep row */
157 
                    break;
158 
                case 3:
159 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST3) != MC_SDRAM_TEST3)
160 
                        continue;
161 
                    SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row*/
162 
                    break;
163 
                case 4:
164 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST4) != MC_SDRAM_TEST4)
165 
                        continue;
166 
                    SET_FLAG(*mc_cs, MC_CSC, WP);  /* RO */
167 
                    break;
168 
                case 5:
169 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST5) != MC_SDRAM_TEST5)
170 
                        continue;
171 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
172 
                    break;
173 
                case 6:
174 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST6) != MC_SDRAM_TEST6)
175 
                        continue;
176 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
177 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
178 
                    break;
179 
                case 7:
180 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST7) != MC_SDRAM_TEST7)
181 
                        continue;
182 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
183 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
184 
                    break;
185 
                case 8:
186 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST8) != MC_SDRAM_TEST8)
187 
                        continue;
188 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
189 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
190 
                    break;
191 
                case 9:
192 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST9) != MC_SDRAM_TEST9)
193 
                        continue;
194 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
195 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* full page */
196 
                    break;
197 
                case 10:
198 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST10) != MC_SDRAM_TEST10)
199 
                        continue;
200 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
201 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
202 
                    break;
203 
                case 11:
204 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST11) != MC_SDRAM_TEST11)
205 
                        continue;
206 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
207 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
208 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
209 
                    break;
210 
                case 12:
211 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST12) != MC_SDRAM_TEST12)
212 
                        continue;
213 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
214 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
215 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 2); /* 4 */
216 
                    break;
217 
                case 13:
218 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST13) != MC_SDRAM_TEST13)
219 
                        continue;
220 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
221 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
222 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 3); /* 8 */
223 
                    break;
224 
                case 14:
225 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST14) != MC_SDRAM_TEST14)
226 
                        continue;
227 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
228 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
229 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 7); /* fullrow */
230 
                    break;
231 
                case 15:
232 
                    if ((MC_SDRAM_TESTS & MC_SDRAM_TEST15) != MC_SDRAM_TEST15)
233 
                        continue;
234 
                    SET_FLAG(*mc_cs, MC_CSC, KRO);  /* keep row */
235 
                    CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
236 
                    SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
237 
                    SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
238 
                    break;
239 
                } /*switch test*/
240 
 
241 
                printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
242 
 
243 
                if (MC_SDRAM_ACC & MC_SDRAM_SROW) {
244 
                    /* perform sequential row access */
245 
                    printf("Seuential Row\n");
246 
                    for (j=MC_SDRAM_ROW_OFF; j<nRows/2; j++) {
247 
                        nAddress  = mc_sel << 21;
248 
                        nAddress |= MC_MEM_BASE;
249 
                        nAddress += (j << nRowSh);
250 
                        ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
251 
 
252 
                        printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
253 
 
254 
                        if (ret) {
255 
                            report(ret);
256 
                            return ret;
257 
                        }
258 
                    }
259 
                }
260 
 
261 
                if (MC_SDRAM_ACC & MC_SDRAM_RROW) {
262 
                    /* perform random row access */
263 
                    printf("Random Row\n");
264 
                    for (j=MC_SDRAM_ROW_OFF; j<nRows/2; j++) {
265 
                        nAddress = mc_sel << 21;
266 
                        nAddress |= MC_MEM_BASE;
267 
                        nAddress += ( (MC_SDRAM_ROW_OFF + random(nRows)) << nRowSh);
268 
                        ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
269 
 
270 
                        printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
271 
 
272 
                        if (ret) {
273 
                            return ret;
274 
                        }
275 
                    }
276 
                }
277 
 
278 
                if (MC_SDRAM_ACC & MC_SDRAM_SGRP) {
279 
                    /* perform sequential row in group access */
280 
                    printf("Sequential Group ");
281 
 
282 
                    nGroups = MC_SDRAM_GROUPSIZE;
283 
                    printf("Group Size = %lu\n", nGroups);
284 
                    for (i=nRows/nGroups-1; i<nRows/nGroups; i++) {
285 
                        nRowGrp = random(nRows - nGroups) + MC_SDRAM_ROW_OFF;
286 
                        for (j=0; j<nGroups; j++) {
287 
                            nAddress = mc_sel << 21;
288 
                            nAddress |= MC_MEM_BASE;
289 
                            nAddress += ((nRowGrp+j) << nRowSh);
290 
                            ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
291 
 
292 
                            printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
293 
 
294 
                            if (ret) {
295 
                                report(ret);
296 
                                return ret;
297 
                            }
298 
                        }
299 
                    }
300 
                }
301 
 
302 
                if (MC_SDRAM_ACC & MC_SDRAM_RGRP) {
303 
                    /* perform random row in group access */
304 
                    printf("Random Group ");
305 
 
306 
                    nGroups = MC_SDRAM_GROUPSIZE;
307 
                    printf("Group Size = %lu\n", nGroups);
308 
                    for (i=(nRows/nGroups)-1; i<nRows/nGroups; i++) {
309 
                        nRowGrp = random(nRows - nGroups) + MC_SDRAM_ROW_OFF;
310 
                        for (j=0; j<nGroups; j++) {
311 
                            nAddress = mc_sel << 21;
312 
                            nAddress |= MC_MEM_BASE;
313 
                            nAddress += ((nRowGrp + random(nGroups)) << nRowSh);
314 
                            ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
315 
 
316 
                            printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
317 
 
318 
                            if (ret) {
319 
                                report(ret);
320 
                                return ret;
321 
                            }
322 
                        }
323 
                    }
324 
                } /*for groups*/
325 
 
326 
            } /*for test*/
327 
        } /*if*/
328 
    } /*for CS*/
329 
    printf("--- End SDRAM tests ---\n");
330 
    report(0xDEADDEAD);
331 
    return 0;
332 
} /* main */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.