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/* This is MMU test for OpenRISC 1200 */
 
#include "spr_defs.h"
#include "support.h"
 
/* Define RAM physical location and size
   Bottom half will be used for this program, the rest
   will be used for testing */
#define FLASH_START 0x00000000
#define FLASH_SIZE  0x00200000
#define RAM_START   0x40000000
#define RAM_SIZE    0x00200000
 
/* What is the last address in ram that is used by this program */
#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))
#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))
 
/* MMU page size */
#define PAGE_SIZE 4096
 
/* Number of DTLB sets used (power of 2, max is 256) */
#define DTLB_SETS 16
 
/* Number of DTLB ways (1, 2, 3 etc., max is 4). */
#define DTLB_WAYS 2
 
/* Number of ITLB sets used (power of 2, max is 256) */
#define ITLB_SETS 16
 
/* Number of ITLB ways (1, 2, 3 etc., max is 4). */
#define ITLB_WAYS 2
 
/* TLB mode codes */
#define TLB_CODE_ONE_TO_ONE     0x00000000
#define TLB_CODE_PLUS_ONE_PAGE  0x10000000
#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
 
#define TLB_CODE_MASK   0xfffff000
#define TLB_PR_MASK     0x00000fff
#define TLB_PR_NOLIMIT  ( SPR_DTLBTR_CI   | \
                          SPR_DTLBTR_URE  | \
                          SPR_DTLBTR_UWE  | \
                          SPR_DTLBTR_SRE  | \
                          SPR_DTLBTR_SWE  )
 
/* fails if x is false */
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
 
#define TEST_JUMP(x) testjump( ((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD, (x))
 
/* Extern functions */
extern void lo_dmmu_en (void);
extern void lo_immu_en (void);
extern void testjump(unsigned long phy_addr, unsigned long virt_addr);
 
/* Local functions prototypes */
void dmmu_disable (void);
void immu_disable (void);
 
/* Global variables */
extern unsigned long ram_end;
 
/* DTLB mode status */
unsigned long dtlb_val;
 
/* ITLB mode status */
unsigned long itlb_val;
 
/* DTLB miss counter */
volatile int dtlb_miss_count;
 
/* ITLB miss counter */
volatile int itlb_miss_count;
 
/* EA of last DTLB miss exception */
unsigned long dtlb_miss_ea;
 
/* EA of last ITLB miss exception */
unsigned long itlb_miss_ea;
 
void fail (char *func, int line)
{
#ifndef __FUNCTION__
#define __FUNCTION__ "?"
#endif
  immu_disable ();
  dmmu_disable ();
  printf ("Test failed in %s:%i\n", func, line);
  report (0xeeeeeeee);
  exit (1);
}
 
/* Bus error exception handler */
void bus_err_handler (void)
{
  /* This shouldn't happend */
  printf ("Test failed: Bus error\n");
  report (0xeeeeeeee);
  exit (1);
}
 
/* Illegal insn exception handler */
void ill_insn_handler (void)
{
  /* This shouldn't happend */
  printf ("Test failed: Illegal insn\n");
  report (0xeeeeeeee);
  exit (1);
}
 
/* DTLB miss exception handler */
void dtlb_miss_handler (void)
{
  unsigned long ea, ta, tlbtr;
  int set, way = 0;
  int i;
 
  /* Get EA that cause the exception */
  ea = mfspr (SPR_EEAR_BASE);
 
  /* Find TLB set and LRU way */
  set = (ea / PAGE_SIZE) % DTLB_SETS;
  for (i = 0; i < DTLB_WAYS; i++) {
    if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {
      way = i;
      break;
    }
  }
 
printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
 
  if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) || ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {
    /* If this is acces to data of this program set one to one translation */
    mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | TLB_PR_NOLIMIT);
    return;
  }
 
  /* Update DTLB miss counter and EA */
  dtlb_miss_count++;
  dtlb_miss_ea = ea;
 
  /* Whatever access is in progress, translated address have to point to physical RAM */
  ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);
  tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
printf("ta = %.8lx\n", ta);
 
  /* Set DTLB entry */
  mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
  mtspr (SPR_DTLBTR_BASE(way) + set, tlbtr);
}
 
 
/* ITLB miss exception handler */
void itlb_miss_handler (void)
{
  unsigned long ea, ta, tlbtr;
  int set, way = 0;
  int i;
 
  /* Get EA that cause the exception */
  ea = mfspr (SPR_EPCR_BASE);
 
  /* Find TLB set and LRU way */
  set = (ea / PAGE_SIZE) % ITLB_SETS;
  for (i = 0; i < ITLB_WAYS; i++) {
    if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {
      way = i;
      break;
    }
  }
 
printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
 
  if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {
    /* If this is acces to data of this program set one to one translation */
    mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
    mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | TLB_PR_NOLIMIT);
    return;
  }
 
  /* Update ITLB miss counter and EA */
  itlb_miss_count++;
  itlb_miss_ea = ea;
 
  /* Whatever access is in progress, translated address have to point to physical RAM */
  ta = (ea & ((FLASH_SIZE/2) - 1)) + TEXT_END_ADD;
  tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
printf("ta = %.8lx\n", ta);
 
  /* Set ITLB entry */
  mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
  mtspr (SPR_ITLBTR_BASE(way) + set, tlbtr);
}
 
/* Invalidate all entries in DTLB and enable DMMU */
void dmmu_enable (void)
{
  /* Register DTLB miss handler */
  excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
 
  /* Enable DMMU */
  lo_dmmu_en ();
}
 
/* Disable DMMU */
void dmmu_disable (void)
{
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);
}
 
/* Invalidate all entries in ITLB and enable IMMU */
void immu_enable (void)
{
  /* Register ITLB miss handler */
  excpt_itlbmiss = (unsigned long)itlb_miss_handler;
 
  /* Enable IMMU */
  lo_immu_en ();
}
 
/* Disable IMMU */
void immu_disable (void)
{
  mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);
}
 
void write_pattern(unsigned long start, unsigned long end)
{
  unsigned long add;
 
  add = start;
  while (add < end) {
    REG32(add) = add;
    add += PAGE_SIZE;
  }
 
}
 
/* Translation address register test
   Set various translation and check the pattern */
int dtlb_translation_test (void)
{
  int i, j;
  unsigned long ea, ta;
 
  /* Disable DMMU */
  dmmu_disable();
 
  /* Invalidate all entries in DTLB */
  for (i = 0; i < DTLB_WAYS; i++) {
    for (j = 0; j < DTLB_SETS; j++) {
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
    }
  }
 
  /* Set one to one translation for the use of this program */
  for (i = 0; i < 2; i++) {
    ea = RAM_START + (i*PAGE_SIZE);
    ta = RAM_START + (i*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | TLB_PR_NOLIMIT);
  }
 
   /* Set dtlb permisions */
  dtlb_val = TLB_PR_NOLIMIT;
 
  /* Write test pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = i;
    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;
  }
 
  /* Set one to one translation of the last way of DTLB */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | TLB_PR_NOLIMIT);
  }
 
  /* Enable DMMU */
  dmmu_enable();
 
  /* Check the pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    ASSERT(REG32(ea) == i);
    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
    ASSERT(REG32(ea) == (0xffffffff - i));
  }
 
  /* Write new pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;
    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;
  }
 
  /* Set 0 -> RAM_START + (RAM_SIZE/2) translation */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = i*PAGE_SIZE;
    ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | TLB_PR_NOLIMIT);
  }
 
  /* Check the pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = i*PAGE_SIZE;
    ASSERT(REG32(ea) == (0xffffffff - i));
    ea = ((i + 1)*PAGE_SIZE) - 4;
    ASSERT(REG32(ea) == i);
  }
 
  /* Write new pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    REG32(i*PAGE_SIZE) = i;
    REG32(((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;
  }
 
  /* Set hi -> lo, lo -> hi translation */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    ta = RAM_START + (RAM_SIZE/2) + ((DTLB_SETS - i - 1)*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | TLB_PR_NOLIMIT);
  }
 
  /* Check the pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    ASSERT(REG32(ea) == (DTLB_SETS - i - 1));
    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
    ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1));
  }
 
  /* Write new pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;
    REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;
  }
 
  /* Disable DMMU */
  dmmu_disable();
 
  /* Check the pattern */
  for (i = 0; i < DTLB_SETS; i++) {
    ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
    ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1));
    ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
    ASSERT(REG32(ea) == (DTLB_SETS - i - 1));
  }
 
  return 0;
}
 
/* EA match register test
   Shifting one in DTLBMR and performing accesses to boundaries
   of the page, checking the triggering of exceptions */
int dtlb_match_test (int way, int set)
{
  int i, j, tmp;
  unsigned long add, t_add;
  unsigned long ea, ta;
 
  /* Disable DMMU */
  dmmu_disable();
 
  /* Invalidate all entries in DTLB */
  for (i = 0; i < DTLB_WAYS; i++) {
    for (j = 0; j < DTLB_SETS; j++) {
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
    }
  }
 
  /* Set one to one translation for the use of this program */
  for (i = 0; i < 2; i++) {
    ea = RAM_START + (i*PAGE_SIZE);
    ta = RAM_START + (i*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | TLB_PR_NOLIMIT);
  }
 
  /* Set dtlb permisions */
  dtlb_val = TLB_PR_NOLIMIT;
 
  /* Set pattern */
  REG32(RAM_START + (RAM_SIZE/2) + PAGE_SIZE - 4) = 0x00112233;
  REG32(RAM_START + (RAM_SIZE/2) + PAGE_SIZE) = 0x44556677;
  REG32(RAM_START + (RAM_SIZE/2) + 2*PAGE_SIZE - 4) = 0x8899aabb;
  REG32(RAM_START + (RAM_SIZE/2) + 2*PAGE_SIZE) = 0xccddeeff;
 
  /* Enable DMMU */
  dmmu_enable();
 
  /* Shifting one in DTLBMR */
  i = 0;
  add = (PAGE_SIZE*DTLB_SETS);
  t_add = add + (set*PAGE_SIZE);
  while (add != 0x00000000) {
    mtspr (SPR_DTLBMR_BASE(way) + set, t_add | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(way) + set, (RAM_START + (RAM_SIZE/2) + PAGE_SIZE) | TLB_PR_NOLIMIT);
 
    /* Reset DTLB miss counter and EA */
    dtlb_miss_count = 0;
    dtlb_miss_ea = 0;
 
    if (((t_add < RAM_START) || (add >= DATA_END_ADD)) && ((t_add < FLASH_START) || (add >= TEXT_END_ADD))) {
 
      /* Read last address of previous page */
      tmp = REG32(t_add - 4);
      ASSERT(dtlb_miss_count == 1);
 
      /* Read first address of the page */
      tmp = REG32(t_add);
      ASSERT(tmp == 0x44556677);
      ASSERT(dtlb_miss_count == 1);
 
      /* Read last address of the page */
      tmp = REG32(t_add + PAGE_SIZE - 4);
      ASSERT(tmp == 0x8899aabb);
      ASSERT(dtlb_miss_count == 1);
 
      /* Read first address of next page */
      tmp = REG32(t_add + PAGE_SIZE);
      ASSERT(dtlb_miss_count == 2);
    }
 
    i++;
    add = (PAGE_SIZE*DTLB_SETS) << i;
    t_add = add + (set*PAGE_SIZE);
 
    for (j = 0; j < DTLB_WAYS; j++) {
      mtspr (SPR_DTLBMR_BASE(j) + ((set - 1) & (DTLB_SETS - 1)), 0);
      mtspr (SPR_DTLBMR_BASE(j) + ((set + 1) & (DTLB_SETS - 1)), 0);
    }
  }
 
  /* Disable DMMU */
  dmmu_disable();
 
  return 0;
}
 
/* Valid bit test
   Set all ways of one set to be invalid, perform
   access so miss handler will set them to valid,
   try access again - there should be no miss exceptions */
int dtlb_valid_bit_test (int set)
{
  int i, j;
  unsigned long ea, ta;
 
  /* Disable DMMU */
  dmmu_disable();
 
  /* Invalidate all entries in DTLB */
  for (i = 0; i < DTLB_WAYS; i++) {
    for (j = 0; j < DTLB_SETS; j++) {
      mtspr (SPR_DTLBMR_BASE(i) + j, 0);
      mtspr (SPR_DTLBTR_BASE(i) + j, 0);
    }
  }
 
  /* Set one to one translation for the use of this program */
  for (i = 0; i < 2; i++) {
    ea = RAM_START + (i*PAGE_SIZE);
    ta = RAM_START + (i*PAGE_SIZE);
    mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
    mtspr (SPR_DTLBTR_BASE(0) + i, ta | TLB_PR_NOLIMIT);
  }
 
  /* Reset DTLB miss counter and EA */
  dtlb_miss_count = 0;
  dtlb_miss_ea = 0;
 
  /* Set dtlb permisions */
  dtlb_val = TLB_PR_NOLIMIT;
 
  /* Resetv DTLBMR for every way */
  for (i = 0; i < DTLB_WAYS; i++) {
    mtspr (SPR_DTLBMR_BASE(i) + set, 0);
  }
 
  /* Enable DMMU */
  dmmu_enable();
 
  /* Perform writes to address, that is not in DTLB */
  for (i = 0; i < DTLB_WAYS; i++) {
    REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) = i;
 
    /* Check if there was DTLB miss */
    ASSERT(dtlb_miss_count == (i + 1));
    ASSERT(dtlb_miss_ea == (RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
  }
 
  /* Reset DTLB miss counter and EA */
  dtlb_miss_count = 0;
  dtlb_miss_ea = 0;
 
  /* Perform reads to address, that is now in DTLB */
  for (i = 0; i < DTLB_WAYS; i++) {
    ASSERT(REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) == i);
 
    /* Check if there was DTLB miss */
    ASSERT(dtlb_miss_count == 0);
  }
 
  /* Reset valid bits */
  for (i = 0; i < DTLB_WAYS; i++) {
    mtspr (SPR_DTLBMR_BASE(i) + set, mfspr (SPR_DTLBMR_BASE(i) + set) & ~SPR_DTLBMR_V);
  }
 
  /* Perform reads to address, that is now in DTLB but is invalid */
  for (i = 0; i < DTLB_WAYS; i++) {
    ASSERT(REG32(RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)) == i);
 
    /* Check if there was DTLB miss */
    ASSERT(dtlb_miss_count == (i + 1));
    ASSERT(dtlb_miss_ea == (RAM_START + RAM_SIZE + (i*DTLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
  }
 
  /* Disable DMMU */
  dmmu_disable();
 
  return 0;
}
 
/* Valid bit test
   Set all ways of one set to be invalid, perform
   access so miss handler will set them to valid,
   try access again - there should be no miss exceptions */
int itlb_valid_bit_test (int set)
{
  int i;
 
  /* Reset ITLB miss counter and EA */
  itlb_miss_count = 0;
  itlb_miss_ea = 0;
 
  /* Set itlb permisions */
  itlb_val = TLB_PR_NOLIMIT;
 
  /* Resetv ITLBMR for every way */
  for (i = 0; i < ITLB_WAYS; i++) {
    mtspr (SPR_ITLBMR_BASE(i) + set, 0);
  }
 
  /* Perform jumps to address, that is not in ITLB */
  for (i = 0; i < ITLB_WAYS; i++) {
    TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
 
    /* Check if there was ITLB miss */
    ASSERT(itlb_miss_count == (i + 1));
    ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
  }
 
  /* Reset ITLB miss counter and EA */
  itlb_miss_count = 0;
  itlb_miss_ea = 0;
 
  /* Perform jumps to address, that is now in ITLB */
  for (i = 0; i < ITLB_WAYS; i++) {
    TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
 
    /* Check if there was ITLB miss */
    ASSERT(itlb_miss_count == 0);
  }
 
  /* Reset valid bits */
  for (i = 0; i < ITLB_WAYS; i++) {
    mtspr (SPR_ITLBMR_BASE(i) + set, mfspr (SPR_ITLBMR_BASE(i) + set) & ~SPR_ITLBMR_V);
  }
 
  /* Perform jumps to address, that is now in ITLB but is invalid */
  for (i = 0; i < ITLB_WAYS; i++) {
    TEST_JUMP(FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
 
    /* Check if there was ITLB miss */
    ASSERT(itlb_miss_count == (i + 1));
    ASSERT(itlb_miss_ea == (FLASH_START + FLASH_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
  }
 
  return 0;
}
 
int main (void)
{
  int i, j;
 
  /* Register bus error handler */
  excpt_buserr = (unsigned long)bus_err_handler;
 
  /* Register illegal insn handler */
  excpt_illinsn = (unsigned long)ill_insn_handler;
 
#if 0
  /* Translation test */
  dtlb_translation_test ();
 
  /* Virtual address match test */
  for (j = 0; j < DTLB_WAYS; j++) {
    for (i = 2; i < (DTLB_SETS - 1); i++)
      dtlb_match_test (j, DTLB_SETS - i);
  }
 
  /* Valid bit testing */
  for (i = 1; i < (DTLB_SETS - 1); i++)
    dtlb_valid_bit_test (DTLB_SETS - i);
#endif
 
  /* Enable IMMU */
  immu_enable();
 
  /* Translation test */
  itlb_valid_bit_test (DTLB_SETS - 2);
 
  report (0xdeaddead);
  exit (0);
  return 0;
}

Line No.	Rev	Author	Line
1	410	simons	`/* This is MMU test for OpenRISC 1200 */`
2
3			`#include "spr_defs.h"`
4			`#include "support.h"`
5
6			`/* Define RAM physical location and size`
7			`Bottom half will be used for this program, the rest`
8			`will be used for testing */`
9	413	markom	`#define FLASH_START 0x00000000`
10			`#define FLASH_SIZE 0x00200000`
11			`#define RAM_START 0x40000000`
12			`#define RAM_SIZE 0x00200000`
13	410	simons
14			`/* What is the last address in ram that is used by this program */`
15	413	markom	`#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))`
16			`#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))`
17	410	simons
18			`/* MMU page size */`
19			`#define PAGE_SIZE 4096`
20
21			`/* Number of DTLB sets used (power of 2, max is 256) */`
22			`#define DTLB_SETS 16`
23
24			`/* Number of DTLB ways (1, 2, 3 etc., max is 4). */`
25			`#define DTLB_WAYS 2`
26
27			`/* Number of ITLB sets used (power of 2, max is 256) */`
28			`#define ITLB_SETS 16`
29
30			`/* Number of ITLB ways (1, 2, 3 etc., max is 4). */`
31			`#define ITLB_WAYS 2`
32
33			`/* TLB mode codes */`
34			`#define TLB_CODE_ONE_TO_ONE 0x00000000`
35			`#define TLB_CODE_PLUS_ONE_PAGE 0x10000000`
36			`#define TLB_CODE_MINUS_ONE_PAGE 0x20000000`
37
38	412	simons	`#define TLB_CODE_MASK 0xfffff000`
39			`#define TLB_PR_MASK 0x00000fff`
40			`#define TLB_PR_NOLIMIT ( SPR_DTLBTR_CI \| \`
41			`SPR_DTLBTR_URE \| \`
42			`SPR_DTLBTR_UWE \| \`
43			`SPR_DTLBTR_SRE \| \`
44			`SPR_DTLBTR_SWE )`
45	410	simons
46	412	simons	`/* fails if x is false */`
47			`#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))`
48
49	415	simons	`#define TEST_JUMP(x) testjump( ((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD, (x))`
50	413	markom
51	410	simons	`/* Extern functions */`
52			`extern void lo_dmmu_en (void);`
53			`extern void lo_immu_en (void);`
54	415	simons	`extern void testjump(unsigned long phy_addr, unsigned long virt_addr);`
55	410	simons
56	415	simons	`/* Local functions prototypes */`
57			`void dmmu_disable (void);`
58			`void immu_disable (void);`
59
60	410	simons	`/* Global variables */`
61			`extern unsigned long ram_end;`
62
63			`/* DTLB mode status */`
64			`unsigned long dtlb_val;`
65
66			`/* ITLB mode status */`
67			`unsigned long itlb_val;`
68
69	412	simons	`/* DTLB miss counter */`
70	415	simons	`volatile int dtlb_miss_count;`
71	412	simons
72			`/* ITLB miss counter */`
73	415	simons	`volatile int itlb_miss_count;`
74	412	simons
75			`/* EA of last DTLB miss exception */`
76			`unsigned long dtlb_miss_ea;`
77
78			`/* EA of last ITLB miss exception */`
79			`unsigned long itlb_miss_ea;`
80
81			`void fail (char *func, int line)`
82			`{`
83			`#ifndef __FUNCTION__`
84			`#define __FUNCTION__ "?"`
85			`#endif`
86	415	simons	`immu_disable ();`
87			`dmmu_disable ();`
88	412	simons	`printf ("Test failed in %s:%i\n", func, line);`
89	415	simons	`report (0xeeeeeeee);`
90	412	simons	`exit (1);`
91			`}`
92
93	415	simons	`/* Bus error exception handler */`
94			`void bus_err_handler (void)`
95			`{`
96			`/* This shouldn't happend */`
97			`printf ("Test failed: Bus error\n");`
98			`report (0xeeeeeeee);`
99			`exit (1);`
100			`}`
101
102			`/* Illegal insn exception handler */`
103			`void ill_insn_handler (void)`
104			`{`
105			`/* This shouldn't happend */`
106			`printf ("Test failed: Illegal insn\n");`
107			`report (0xeeeeeeee);`
108			`exit (1);`
109			`}`
110
111	410	simons	`/* DTLB miss exception handler */`
112			`void dtlb_miss_handler (void)`
113			`{`
114			`unsigned long ea, ta, tlbtr;`
115			`int set, way = 0;`
116			`int i;`
117
118			`/* Get EA that cause the exception */`
119			`ea = mfspr (SPR_EEAR_BASE);`
120	412	simons
121	410	simons	`/* Find TLB set and LRU way */`
122			`set = (ea / PAGE_SIZE) % DTLB_SETS;`
123			`for (i = 0; i < DTLB_WAYS; i++) {`
124			`if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_LRU) == 0) {`
125			`way = i;`
126			`break;`
127			`}`
128			`}`
129
130	412	simons	`printf("ea = %.8lx set = %d way = %d\n", ea, set, way);`
131	410	simons
132	415	simons	`if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) \|\| ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {`
133	410	simons	`/* If this is acces to data of this program set one to one translation */`
134			`mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) \| SPR_DTLBMR_V);`
135	412	simons	`mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) \| TLB_PR_NOLIMIT);`
136	410	simons	`return;`
137			`}`
138
139	412	simons	`/* Update DTLB miss counter and EA */`
140			`dtlb_miss_count++;`
141			`dtlb_miss_ea = ea;`
142
143	410	simons	`/* Whatever access is in progress, translated address have to point to physical RAM */`
144	415	simons	`ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);`
145			`tlbtr = (ta & SPR_DTLBTR_PPN) \| (dtlb_val & TLB_PR_MASK);`
146	412	simons	`printf("ta = %.8lx\n", ta);`
147	410	simons
148			`/* Set DTLB entry */`
149			`mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) \| SPR_DTLBMR_V);`
150			`mtspr (SPR_DTLBTR_BASE(way) + set, tlbtr);`
151			`}`
152
153
154			`/* ITLB miss exception handler */`
155			`void itlb_miss_handler (void)`
156			`{`
157	413	markom	`unsigned long ea, ta, tlbtr;`
158			`int set, way = 0;`
159			`int i;`
160	410	simons
161	413	markom	`/* Get EA that cause the exception */`
162	415	simons	`ea = mfspr (SPR_EPCR_BASE);`
163	410	simons
164	413	markom	`/* Find TLB set and LRU way */`
165			`set = (ea / PAGE_SIZE) % ITLB_SETS;`
166			`for (i = 0; i < ITLB_WAYS; i++) {`
167			`if ((mfspr (SPR_ITLBMR_BASE(i) + set) & SPR_ITLBMR_LRU) == 0) {`
168			`way = i;`
169			`break;`
170			`}`
171			`}`
172
173			`printf("ea = %.8lx set = %d way = %d\n", ea, set, way);`
174
175			`if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {`
176			`/* If this is acces to data of this program set one to one translation */`
177			`mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) \| SPR_ITLBMR_V);`
178			`mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) \| TLB_PR_NOLIMIT);`
179			`return;`
180			`}`
181
182			`/* Update ITLB miss counter and EA */`
183			`itlb_miss_count++;`
184			`itlb_miss_ea = ea;`
185
186			`/* Whatever access is in progress, translated address have to point to physical RAM */`
187			`ta = (ea & ((FLASH_SIZE/2) - 1)) + TEXT_END_ADD;`
188	415	simons	`tlbtr = (ta & SPR_ITLBTR_PPN) \| (itlb_val & TLB_PR_MASK);`
189	413	markom	`printf("ta = %.8lx\n", ta);`
190
191			`/* Set ITLB entry */`
192			`mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) \| SPR_ITLBMR_V);`
193			`mtspr (SPR_ITLBTR_BASE(way) + set, tlbtr);`
194	410	simons	`}`
195
196			`/* Invalidate all entries in DTLB and enable DMMU */`
197			`void dmmu_enable (void)`
198			`{`
199			`/* Register DTLB miss handler */`
200			`excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;`
201
202			`/* Enable DMMU */`
203			`lo_dmmu_en ();`
204			`}`
205
206	415	simons	`/* Disable DMMU */`
207			`void dmmu_disable (void)`
208			`{`
209			`mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_DME);`
210			`}`
211
212	410	simons	`/* Invalidate all entries in ITLB and enable IMMU */`
213			`void immu_enable (void)`
214			`{`
215			`/* Register ITLB miss handler */`
216			`excpt_itlbmiss = (unsigned long)itlb_miss_handler;`
217
218			`/* Enable IMMU */`
219			`lo_immu_en ();`
220			`}`
221
222	415	simons	`/* Disable IMMU */`
223			`void immu_disable (void)`
224			`{`
225			`mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_IME);`
226			`}`
227
228	410	simons	`void write_pattern(unsigned long start, unsigned long end)`
229			`{`
230			`unsigned long add;`
231
232			`add = start;`
233			`while (add < end) {`
234			`REG32(add) = add;`
235			`add += PAGE_SIZE;`
236			`}`
237
238			`}`
239
240	415	simons	`/* Translation address register test`
241			`Set various translation and check the pattern */`
242			`int dtlb_translation_test (void)`
243			`{`
244			`int i, j;`
245			`unsigned long ea, ta;`
246
247			`/* Disable DMMU */`
248			`dmmu_disable();`
249
250			`/* Invalidate all entries in DTLB */`
251			`for (i = 0; i < DTLB_WAYS; i++) {`
252			`for (j = 0; j < DTLB_SETS; j++) {`
253			`mtspr (SPR_DTLBMR_BASE(i) + j, 0);`
254			`mtspr (SPR_DTLBTR_BASE(i) + j, 0);`
255			`}`
256			`}`
257
258			`/* Set one to one translation for the use of this program */`
259			`for (i = 0; i < 2; i++) {`
260			`ea = RAM_START + (i*PAGE_SIZE);`
261			`ta = RAM_START + (i*PAGE_SIZE);`
262			`mtspr (SPR_DTLBMR_BASE(0) + i, ea \| SPR_DTLBMR_V);`
263			`mtspr (SPR_DTLBTR_BASE(0) + i, ta \| TLB_PR_NOLIMIT);`
264			`}`
265
266			`/* Set dtlb permisions */`
267			`dtlb_val = TLB_PR_NOLIMIT;`
268
269			`/* Write test pattern */`
270			`for (i = 0; i < DTLB_SETS; i++) {`
271			`REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = i;`
272			`REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;`
273			`}`
274
275			`/* Set one to one translation of the last way of DTLB */`
276			`for (i = 0; i < DTLB_SETS; i++) {`
277			`ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
278			`ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
279			`mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea \| SPR_DTLBMR_V);`
280			`mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta \| TLB_PR_NOLIMIT);`
281			`}`
282
283			`/* Enable DMMU */`
284			`dmmu_enable();`
285
286			`/* Check the pattern */`
287			`for (i = 0; i < DTLB_SETS; i++) {`
288			`ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
289			`ASSERT(REG32(ea) == i);`
290			`ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;`
291			`ASSERT(REG32(ea) == (0xffffffff - i));`
292			`}`
293
294			`/* Write new pattern */`
295			`for (i = 0; i < DTLB_SETS; i++) {`
296			`REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;`
297			`REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;`
298			`}`
299
300			`/* Set 0 -> RAM_START + (RAM_SIZE/2) translation */`
301			`for (i = 0; i < DTLB_SETS; i++) {`
302			`ea = i*PAGE_SIZE;`
303			`ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
304			`mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea \| SPR_DTLBMR_V);`
305			`mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta \| TLB_PR_NOLIMIT);`
306			`}`
307
308			`/* Check the pattern */`
309			`for (i = 0; i < DTLB_SETS; i++) {`
310			`ea = i*PAGE_SIZE;`
311			`ASSERT(REG32(ea) == (0xffffffff - i));`
312			`ea = ((i + 1)*PAGE_SIZE) - 4;`
313			`ASSERT(REG32(ea) == i);`
314			`}`
315
316			`/* Write new pattern */`
317			`for (i = 0; i < DTLB_SETS; i++) {`
318			`REG32(i*PAGE_SIZE) = i;`
319			`REG32(((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;`
320			`}`
321
322			`/* Set hi -> lo, lo -> hi translation */`
323			`for (i = 0; i < DTLB_SETS; i++) {`
324			`ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
325			`ta = RAM_START + (RAM_SIZE/2) + ((DTLB_SETS - i - 1)*PAGE_SIZE);`
326			`mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea \| SPR_DTLBMR_V);`
327			`mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta \| TLB_PR_NOLIMIT);`
328			`}`
329
330			`/* Check the pattern */`
331			`for (i = 0; i < DTLB_SETS; i++) {`
332			`ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
333			`ASSERT(REG32(ea) == (DTLB_SETS - i - 1));`
334			`ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;`
335			`ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1));`
336			`}`
337
338			`/* Write new pattern */`
339			`for (i = 0; i < DTLB_SETS; i++) {`
340			`REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;`
341			`REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;`
342			`}`
343
344			`/* Disable DMMU */`
345			`dmmu_disable();`
346
347			`/* Check the pattern */`
348			`for (i = 0; i < DTLB_SETS; i++) {`
349			`ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);`
350			`ASSERT(REG32(ea) == (0xffffffff - DTLB_SETS + i + 1));`
351			`ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;`
352			`ASSERT(REG32(ea) == (DTLB_SETS - i - 1));`
353			`}`
354
355			`return 0;`
356			`}`
357
358			`/* EA match register test`
359			`Shifting one in DTLBMR and performing accesses to boundaries`
360			`of the page, checking the triggering of exceptions */`
361			`int dtlb_match_test (int way, int set)`
362			`{`
363			`int i, j, tmp;`
364			`unsigned long add, t_add;`
365			`unsigned long ea, ta;`
366
367			`/* Disable DMMU */`
368			`dmmu_disable();`
369
370			`/* Invalidate all entries in DTLB */`
371			`for (i = 0; i < DTLB_WAYS; i++) {`
372			`for (j = 0; j < DTLB_SETS; j++) {`
373			`mtspr (SPR_DTLBMR_BASE(i) + j, 0);`
374			`mtspr (SPR_DTLBTR_BASE(i) + j, 0);`
375			`}`
376			`}`
377
378			`/* Set one to one translation for the use of this program */`
379			`for (i = 0; i < 2; i++) {`
380			`ea = RAM_START + (i*PAGE_SIZE);`
381			`ta = RAM_START + (i*PAGE_SIZE);`
382			`mtspr (SPR_DTLBMR_BASE(0) + i, ea \| SPR_DTLBMR_V);`
383			`mtspr (SPR_DTLBTR_BASE(0) + i, ta \| TLB_PR_NOLIMIT);`
384			`}`
385
386			`/* Set dtlb permisions */`
387			`dtlb_val = TLB_PR_NOLIMIT;`
388
389			`/* Set pattern */`
390			`REG32(RAM_START + (RAM_SIZE/2) + PAGE_SIZE - 4) = 0x00112233;`
391			`REG32(RAM_START + (RAM_SIZE/2) + PAGE_SIZE) = 0x44556677;`
392			`REG32(RAM_START + (RAM_SIZE/2) + 2*PAGE_SIZE - 4) = 0x8899aabb;`
393			`REG32(RAM_START + (RAM_SIZE/2) + 2*PAGE_SIZE) = 0xccddeeff;`
394
395			`/* Enable DMMU */`
396			`dmmu_enable();`
397
398			`/* Shifting one in DTLBMR */`
399			`i = 0;`
400			`add = (PAGE_SIZE*DTLB_SETS);`
401			`t_add = add + (set*PAGE_SIZE);`
402			`while (add != 0x00000000) {`
403			`mtspr (SPR_DTLBMR_BASE(way) + set, t_add \| SPR_DTLBMR_V);`
404			`mtspr (SPR_DTLBTR_BASE(way) + set, (RAM_START + (RAM_SIZE/2) + PAGE_SIZE) \| TLB_PR_NOLIMIT);`
405
406			`/* Reset DTLB miss counter and EA */`
407			`dtlb_miss_count = 0;`
408			`dtlb_miss_ea = 0;`
409
410			`if (((t_add < RAM_START) \|\| (add >= DATA_END_ADD)) && ((t_add < FLASH_START) \|\| (add >= TEXT_END_ADD))) {`
411
412			`/* Read last address of previous page */`
413			`tmp = REG32(t_add - 4);`
414			`ASSERT(dtlb_miss_count == 1);`
415
416			`/* Read first address of the page */`
417			`tmp = REG32(t_add);`
418			`ASSERT(tmp == 0x44556677);`
419			`ASSERT(dtlb_miss_count == 1);`
420
421			`/* Read last address of the page */`
422			`tmp = REG32(t_add + PAGE_SIZE - 4);`
423			`ASSERT(tmp == 0x8899aabb);`
424			`ASSERT(dtlb_miss_count == 1);`
425
426			`/* Read first address of next page */`
427			`tmp = REG32(t_add + PAGE_SIZE);`
428			`ASSERT(dtlb_miss_count == 2);`
429			`}`
430
431			`i++;`
432			`add = (PAGE_SIZE*DTLB_SETS) << i;`
433			`t_add = add + (set*PAGE_SIZE);`
434
435			`for (j = 0; j < DTLB_WAYS; j++) {`
436			`mtspr (SPR_DTLBMR_BASE(j) + ((set - 1) & (DTLB_SETS - 1)), 0);`
437			`mtspr (SPR_DTLBMR_BASE(j) + ((set + 1) & (DTLB_SETS - 1)), 0);`
438			`}`
439			`}`
440
441			`/* Disable DMMU */`
442			`dmmu_disable();`
443
444			`return 0;`
445			`}`
446
447	412	simons	`/* Valid bit test`
448			`Set all ways of one set to be invalid, perform`
449			`access so miss handler will set them to valid,`
450			`try access again - there should be no miss exceptions */`
451			`int dtlb_valid_bit_test (int set)`
452			`{`
453	415	simons	`int i, j;`
454			`unsigned long ea, ta;`
455	412	simons
456	415	simons	`/* Disable DMMU */`
457			`dmmu_disable();`
458
459			`/* Invalidate all entries in DTLB */`
460			`for (i = 0; i < DTLB_WAYS; i++) {`
461			`for (j = 0; j < DTLB_SETS; j++) {`
462			`mtspr (SPR_DTLBMR_BASE(i) + j, 0);`
463			`mtspr (SPR_DTLBTR_BASE(i) + j, 0);`
464			`}`
465			`}`
466
467			`/* Set one to one translation for the use of this program */`
468			`for (i = 0; i < 2; i++) {`
469			`ea = RAM_START + (i*PAGE_SIZE);`
470			`ta = RAM_START + (i*PAGE_SIZE);`
471			`mtspr (SPR_DTLBMR_BASE(0) + i, ea \| SPR_DTLBMR_V);`
472			`mtspr (SPR_DTLBTR_BASE(0) + i, ta \| TLB_PR_NOLIMIT);`
473			`}`
474
475	412	simons	`/* Reset DTLB miss counter and EA */`
476			`dtlb_miss_count = 0;`
477			`dtlb_miss_ea = 0;`
478
479			`/* Set dtlb permisions */`
480			`dtlb_val = TLB_PR_NOLIMIT;`
481
482			`/* Resetv DTLBMR for every way */`
483			`for (i = 0; i < DTLB_WAYS; i++) {`
484			`mtspr (SPR_DTLBMR_BASE(i) + set, 0);`
485			`}`
486
487	415	simons	`/* Enable DMMU */`
488			`dmmu_enable();`
489
490	412	simons	`/* Perform writes to address, that is not in DTLB */`
491			`for (i = 0; i < DTLB_WAYS; i++) {`
492			`REG32(RAM_START + RAM_SIZE + (iDTLB_SETSPAGE_SIZE) + (set*PAGE_SIZE)) = i;`
493
494			`/* Check if there was DTLB miss */`
495			`ASSERT(dtlb_miss_count == (i + 1));`
496			`ASSERT(dtlb_miss_ea == (RAM_START + RAM_SIZE + (iDTLB_SETSPAGE_SIZE) + (set*PAGE_SIZE)));`
497			`}`
498
499			`/* Reset DTLB miss counter and EA */`
500			`dtlb_miss_count = 0;`

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