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/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
   The or1ksim have various parameters, which can be set in configuration
   files.  Multiple configurations may be used and switched between at
   or1ksim startup.
   By default, or1ksim loads condfiguration file from './sim.cfg' and if not
   found it checks '~/.or1k/sim.cfg'. If even this file is not found or
   all parameters are not defined, default configuration is used.
   Users should not rely on default configuration, but rather redefine all
   critical settings, since default configuration may differ in newer
   versions of the or1ksim.
   If multiple configurations are used, user can switch between them by
   supplying -f  option when starting simulator.
 
   This file may contain (standard C) only comments - no // support.
 
   Like normal configuration file, this file is divided in sections,
   where each section is described in detail also.
 
   Some section also have subsections. One example of such subsection is
   block:
 
   device 
     instance specific parameters...
   enddevice
 
   which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
   This section specifies how is initial memory generated and which blocks
   it consist of.
 
   type = random/unknown/pattern
      specifies the initial memory values. 'random' parameter generate
      random memory using seed 'random_seed' parameter. 'pattern' parameter
      fills memory with 'pattern' parameter and 'unknown' does not specify
      how memory should be generated - the fastest option.
 
   random_seed = 
      random seed for randomizer, used if type = random
 
   pattern = 
      pattern to fill memory, used if type = pattern
 
   nmemories = 
      number of memory instances connected
 
   instance specific:
     baseaddr = 
        memory start address
 
     size = 
        memory size
 
     name = ""
        memory block name
 
     ce = 
        chip enable index of the memory instance
 
     delayr = 
        cycles, required for read access, -1 if instance does not support reading
 
     delayw = 
        cycles, required for write access, -1 if instance does not support writing
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     log = ""
        filename, where to log memory accesses to, no log, if log command is not specified
*/
 
section memory
  /*random_seed = 12345
  type = random*/
  pattern = 0x00
  type = unknown /* Fastest */
 
  nmemories = 2
  device 0
    name = "RAM"
    ce = 0
    baseaddr = 0x40000000
    size = 0x00200000
    delayr = 1
    delayw = 2
  enddevice
 
  device 1
    name = "FLASH"
    ce = 1
    baseaddr = 0x00000000
    size = 0x00200000
    delayr = 10
    delayw = -1
  enddevice
end
 
/* IMMU SECTION
 
    This section configures Instruction Memory Menangement Unit
 
    enabled = 0/1
       whether IMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of ITLB sets; must be power of two
 
    nways = 
       number of ITLB ways
 
    pagesize = 
       instruction page size; must be power of two
 
    entrysize = 
       instruction entry size in bytes
 
    ustates = 
       number of ITLB usage states (2, 3, 4 etc., max is 4)
*/
 
section immu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
/* DMMU SECTION
 
    This section configures Data Memory Menangement Unit
 
    enabled = 0/1
       whether DMMU is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DTLB sets; must be power of two
 
    nways = 
       number of DTLB ways
 
    pagesize = 
       data page size; must be power of two
 
    entrysize = 
       data entry size in bytes
 
    ustates = 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
*/
 
section dmmu
  enabled = 1
  nsets = 32
  nways = 1
  pagesize = 8192
end
 
 
/* IC SECTION
 
    This section configures Instruction Cache
 
    enabled = 0/1
       whether IC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of IC sets; must be power of two
 
    nways = 
       number of IC ways
 
    blocksize = 
       IC block size in bytes; must be power of two
 
    ustates = 
       number of IC usage states (2, 3, 4 etc., max is 4)
*/
 
section ic
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
/* DC SECTION
 
    This section configures Data Cache
 
    enabled = 0/1
       whether DC is enabled
       (NOTE: UPR bit is set)
 
    nsets = 
       number of DC sets; must be power of two
 
    nways = 
       number of DC ways
 
    blocksize = 
       DC block size in bytes; must be power of two
 
    ustates = 
       number of DC usage states (2, 3, 4 etc., max is 4)
*/
 
section dc
  enabled = 0
  nsets = 512
  nways = 1
  blocksize = 16
end
 
/* SIM SECTION
 
  This section specifies how should sim behave.
 
  verbose = 0/1
      whether to print out extra messages
 
  debug = 0-9
      = 0 disabled debug messages
      1-9 level of sim debug information, greater the number more verbose is
          the output
 
  profile = 0/1
      whether to generate profiling file 'sim.profile'
 
  prof_fn = ""
      filename, where to generate profiling info, used
      only if 'profile' is set
 
  history = 0/1
      whether instruction execution flow is tracked for
      display by simulator hist command. Useful for
      back-trace debugging.
 
  iprompt = 0/1
      whether we strart in interactive prompt
 
  exe_log = 0/1
      whether execution log should be generated
 
  exe_log_fn = ""
      where to put execution log in, used only if 'exe_log'
      is set
 
  clkcycle = [ps|ns|us|ms]
      specifies time measurement for one cycle
*/
 
section sim
  /* verbose = 1 */
  debug = 0
  profile = 0
  prof_fn = "sim.profile"
 
  history = 1
  /* iprompt = 0 */
  exe_log = 0
  exe_log_fn = "executed.log"
end
 
 
/* SECTION VAPI
 
    This section configures Verification API, used for Advanced
    Core Verification.
 
    enabled = 0/1
        whether to start VAPI server
 
    server_port = 
        TCP/IP port to start VAPI server on
 
    log_enabled = 0/1
       whether logging of VAPI requests is enabled
 
    vapi_fn = 
       specifies filename where to log into, if log_enabled is selected
*/
 
section VAPI
  enabled = 0
  server_port = 9998
  log_enabled = 0
  vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
   This section specifies various CPU parameters.
 
   ver = 
   rev = 
      specifies version and revision of the CPU used
 
   upr = 
      changes the upr register
 
   superscalar = 0/1
      whether CPU is scalar or superscalar
      (modify cpu/or32/execute.c to tune superscalar model)
 
   hazards = 0/1
      whether data hazards are tracked in superscalar CPU
      and displayed by the simulator r command
 
   dependstats = 0/1
      whether inter-instruction dependencies are calculated
      and displayed by simulator stats command.
*/
 
section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  dependstats = 0
end
 
section bpb
  enabled = 0
  btic = 0
end
 
 
/* DEBUG SECTION
 
   This sections specifies how debug unit should behave.
 
   enabled = 0/1
      whether debug unit is enabled
 
   gdb_enabled = 0/1
      whether to start gdb server at 'server_port' port
 
   server_port = 
      TCP/IP port to start gdb server on, used only if gdb_enabled
      is set
 
section debug
  enabled = 0
  gdb_enabled = 0
  server_port = 9999
end
 
 
/* MC SECTION
 
   This section configures the memory controller
 
   enabled = 0/1
      whether memory controller is enabled
 
   baseaddr = 
      address of first MC register
 
   POC = 
      Power On Configuration register
*/
 
section mc
  enabled = 0
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
 
/* UART SECTION
 
   This section configures UARTs
 
   enabled = 0/1
      whether uarts are enabled
 
   nuarts = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first UART register for this device
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     irq = 
        irq number for this device
 
     16550 = 0/1
        0, if this device is uart 16450 and 1, if it is 16550
 
     jitter = 
        in msecs... time to block, -1 to disable it
 
     vapi_id = 
        VAPI id of this instance
*/
 
section uart
  enabled = 0
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    irq = 2
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
 
 
/* DMA SECTION
 
   This section configures DMAs
 
   enabled = 0/1
      whether DMAs are enabled
 
   ndmas = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first DMA register for this device
 
     irq = 
        irq number for this device
 
     vapi_id = 
        VAPI id of this instance
*/
 
section dma
  enabled = 0
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end
 
 
/* ETHERNET SECTION
 
   This section configures ethernets
 
   enabled = 0/1
      whether ethernets are enabled
 
   nethernets = 
      make specified number of instances, configure each
      instance within device - enddevice construct.
 
   instance specific:
     baseaddr = 
        address of first ethernet register for this device
 
     dma = 
        which controller is this ethernet "connected" to
 
     rx_channel = 
        DMA channel used for RX
 
     tx_channel = 
        DMA channel used for TX
 
     rx_file = ""
        filename, where to read data from
 
     tx_file = ""
        filename, where to write data to
 
     vapi_id = 
        VAPI id of this instance
*/
 
section ethernet
  enabled = 0
  nethernets = 1
 
  device 0
    baseaddr = 0x88000000
    dma = 0
    tx_channel = 0
    rx_channel = 1
    rxfile = "/tmp/eth0.rx"
    txfile = "/tmp/eth0.tx"
  enddevice
end
 
/* TICK TIMER SECTION
 
    This section configures tick timer
 
    enabled = 0/1
      whether tick timer is enabled
 
    irq = 
      irq number
*/
 
section tick
  enabled = 0
  irq = 3
end

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[/] [or1k/] [tags/] [nog_patch_47/] [or1ksim/] [testbench/] [mmu.cfg] - Blame information for rev 541

Line No.	Rev	Author	Line
1	449	simons	`/* sim.cfg -- Simulator configuration script file`
2			`Copyright (C) 2001, Marko Mlinar, markom@opencores.org`
3
4			`This file includes a lot of help about configurations and default one`
5
6			`This file is part of OpenRISC 1000 Architectural Simulator.`
7
8			`This program is free software; you can redistribute it and/or modify`
9			`it under the terms of the GNU General Public License as published by`
10			`the Free Software Foundation; either version 2 of the License, or`
11			`(at your option) any later version.`
12
13			`This program is distributed in the hope that it will be useful,`
14			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`GNU General Public License for more details.`
17
18			`You should have received a copy of the GNU General Public License`
19			`along with this program; if not, write to the Free Software`
20			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
21
22
23			`/* INTRODUCTION`
24
25			`The or1ksim have various parameters, which can be set in configuration`
26			`files. Multiple configurations may be used and switched between at`
27			`or1ksim startup.`
28			`By default, or1ksim loads condfiguration file from './sim.cfg' and if not`
29			`found it checks '~/.or1k/sim.cfg'. If even this file is not found or`
30			`all parameters are not defined, default configuration is used.`
31			`Users should not rely on default configuration, but rather redefine all`
32			`critical settings, since default configuration may differ in newer`
33			`versions of the or1ksim.`
34			`If multiple configurations are used, user can switch between them by`
35			`supplying -f option when starting simulator.`
36
37			`This file may contain (standard C) only comments - no // support.`
38
39			`Like normal configuration file, this file is divided in sections,`
40			`where each section is described in detail also.`
41
42			`Some section also have subsections. One example of such subsection is`
43			`block:`
44
45			`device`
46			`instance specific parameters...`
47			`enddevice`
48
49			`which creates a device instance.`
50			`*/`
51
52
53			`/* MEMORY SECTION`
54
55			`This section specifies how is initial memory generated and which blocks`
56			`it consist of.`
57
58			`type = random/unknown/pattern`
59			`specifies the initial memory values. 'random' parameter generate`
60			`random memory using seed 'random_seed' parameter. 'pattern' parameter`
61			`fills memory with 'pattern' parameter and 'unknown' does not specify`
62			`how memory should be generated - the fastest option.`
63
64			`random_seed =`
65			`random seed for randomizer, used if type = random`
66
67			`pattern =`
68			`pattern to fill memory, used if type = pattern`
69
70			`nmemories =`
71			`number of memory instances connected`
72
73			`instance specific:`
74			`baseaddr =`
75			`memory start address`
76
77			`size =`
78			`memory size`
79
80			`name = ""`
81			`memory block name`
82
83			`ce =`
84			`chip enable index of the memory instance`
85
86			`delayr =`
87			`cycles, required for read access, -1 if instance does not support reading`
88
89			`delayw =`
90			`cycles, required for write access, -1 if instance does not support writing`
91
92			`16550 = 0/1`
93			`0, if this device is uart 16450 and 1, if it is 16550`
94
95			`log = ""`
96			`filename, where to log memory accesses to, no log, if log command is not specified`
97			`*/`
98
99			`section memory`
100			`/*random_seed = 12345`
101			`type = random*/`
102			`pattern = 0x00`
103			`type = unknown /* Fastest */`
104
105			`nmemories = 2`
106			`device 0`
107			`name = "RAM"`
108			`ce = 0`
109			`baseaddr = 0x40000000`
110			`size = 0x00200000`
111			`delayr = 1`
112			`delayw = 2`
113			`enddevice`
114
115			`device 1`
116			`name = "FLASH"`
117			`ce = 1`
118			`baseaddr = 0x00000000`
119			`size = 0x00200000`
120			`delayr = 10`
121			`delayw = -1`
122			`enddevice`
123			`end`
124
125			`/* IMMU SECTION`
126
127			`This section configures Instruction Memory Menangement Unit`
128
129			`enabled = 0/1`
130			`whether IMMU is enabled`
131			`(NOTE: UPR bit is set)`
132
133			`nsets =`
134			`number of ITLB sets; must be power of two`
135
136			`nways =`
137			`number of ITLB ways`
138
139			`pagesize =`
140			`instruction page size; must be power of two`
141
142			`entrysize =`
143			`instruction entry size in bytes`
144
145			`ustates =`
146			`number of ITLB usage states (2, 3, 4 etc., max is 4)`
147			`*/`
148
149			`section immu`
150			`enabled = 1`
151			`nsets = 32`
152			`nways = 1`
153	457	simons	`pagesize = 8192`
154	449	simons	`end`
155
156			`/* DMMU SECTION`
157
158			`This section configures Data Memory Menangement Unit`
159
160			`enabled = 0/1`
161			`whether DMMU is enabled`
162			`(NOTE: UPR bit is set)`
163
164			`nsets =`
165			`number of DTLB sets; must be power of two`
166
167			`nways =`
168			`number of DTLB ways`
169
170			`pagesize =`
171			`data page size; must be power of two`
172
173			`entrysize =`
174			`data entry size in bytes`
175
176			`ustates =`
177			`number of DTLB usage states (2, 3, 4 etc., max is 4)`
178			`*/`
179
180			`section dmmu`
181			`enabled = 1`
182			`nsets = 32`
183			`nways = 1`
184	457	simons	`pagesize = 8192`
185	449	simons	`end`
186
187
188			`/* IC SECTION`
189
190			`This section configures Instruction Cache`
191
192			`enabled = 0/1`
193			`whether IC is enabled`
194			`(NOTE: UPR bit is set)`
195
196			`nsets =`
197			`number of IC sets; must be power of two`
198
199			`nways =`
200			`number of IC ways`
201
202			`blocksize =`
203			`IC block size in bytes; must be power of two`
204
205			`ustates =`
206			`number of IC usage states (2, 3, 4 etc., max is 4)`
207			`*/`
208
209			`section ic`
210			`enabled = 0`
211			`nsets = 512`
212			`nways = 1`
213			`blocksize = 16`
214			`end`
215
216			`/* DC SECTION`
217
218			`This section configures Data Cache`
219
220			`enabled = 0/1`
221			`whether DC is enabled`
222			`(NOTE: UPR bit is set)`
223
224			`nsets =`
225			`number of DC sets; must be power of two`
226
227			`nways =`
228			`number of DC ways`
229
230			`blocksize =`
231			`DC block size in bytes; must be power of two`
232
233			`ustates =`
234			`number of DC usage states (2, 3, 4 etc., max is 4)`
235			`*/`
236
237			`section dc`
238			`enabled = 0`
239			`nsets = 512`
240			`nways = 1`
241			`blocksize = 16`
242			`end`
243
244			`/* SIM SECTION`
245
246			`This section specifies how should sim behave.`
247
248			`verbose = 0/1`
249			`whether to print out extra messages`
250
251			`debug = 0-9`
252			`= 0 disabled debug messages`
253			`1-9 level of sim debug information, greater the number more verbose is`
254			`the output`
255
256			`profile = 0/1`
257			`whether to generate profiling file 'sim.profile'`
258
259			`prof_fn = ""`
260			`filename, where to generate profiling info, used`
261			`only if 'profile' is set`
262
263			`history = 0/1`
264			`whether instruction execution flow is tracked for`
265			`display by simulator hist command. Useful for`
266			`back-trace debugging.`
267
268			`iprompt = 0/1`
269			`whether we strart in interactive prompt`
270
271			`exe_log = 0/1`
272			`whether execution log should be generated`
273
274			`exe_log_fn = ""`
275			`where to put execution log in, used only if 'exe_log'`
276			`is set`
277
278			`clkcycle = [ps\|ns\|us\|ms]`
279			`specifies time measurement for one cycle`
280			`*/`
281
282			`section sim`
283			`/* verbose = 1 */`
284			`debug = 0`
285			`profile = 0`
286			`prof_fn = "sim.profile"`
287
288			`history = 1`
289			`/* iprompt = 0 */`
290			`exe_log = 0`
291			`exe_log_fn = "executed.log"`
292			`end`
293
294
295			`/* SECTION VAPI`
296
297			`This section configures Verification API, used for Advanced`
298			`Core Verification.`
299
300			`enabled = 0/1`
301			`whether to start VAPI server`
302
303			`server_port =`
304			`TCP/IP port to start VAPI server on`
305
306			`log_enabled = 0/1`
307			`whether logging of VAPI requests is enabled`
308
309			`vapi_fn =`
310			`specifies filename where to log into, if log_enabled is selected`
311			`*/`
312
313			`section VAPI`
314			`enabled = 0`
315			`server_port = 9998`
316			`log_enabled = 0`
317			`vapi_log_fn = "vapi.log"`
318			`end`
319
320
321			`/* CPU SECTION`
322
323			`This section specifies various CPU parameters.`
324
325			`ver =`
326			`rev =`
327			`specifies version and revision of the CPU used`
328
329			`upr =`
330			`changes the upr register`
331
332			`superscalar = 0/1`
333			`whether CPU is scalar or superscalar`
334			`(modify cpu/or32/execute.c to tune superscalar model)`
335
336			`hazards = 0/1`
337			`whether data hazards are tracked in superscalar CPU`
338			`and displayed by the simulator r command`
339
340			`dependstats = 0/1`
341			`whether inter-instruction dependencies are calculated`
342			`and displayed by simulator stats command.`
343			`*/`
344
345			`section cpu`
346			`ver = 0x1200`
347			`rev = 0x0001`
348			`/* upr = */`
349			`superscalar = 0`
350			`hazards = 0`
351			`dependstats = 0`
352	541	markom	`end`
353
354			`section bpb`
355			`enabled = 0`
356	449	simons	`btic = 0`
357			`end`
358
359
360			`/* DEBUG SECTION`
361
362			`This sections specifies how debug unit should behave.`
363
364			`enabled = 0/1`
365			`whether debug unit is enabled`
366
367			`gdb_enabled = 0/1`
368			`whether to start gdb server at 'server_port' port`
369
370			`server_port =`
371			`TCP/IP port to start gdb server on, used only if gdb_enabled`
372			`is set`
373
374			`section debug`
375			`enabled = 0`
376			`gdb_enabled = 0`
377			`server_port = 9999`
378			`end`
379
380
381			`/* MC SECTION`
382
383			`This section configures the memory controller`
384
385			`enabled = 0/1`
386			`whether memory controller is enabled`
387
388			`baseaddr =`
389			`address of first MC register`
390
391			`POC =`
392			`Power On Configuration register`
393			`*/`
394
395			`section mc`
396			`enabled = 0`
397			`baseaddr = 0xa0000000`
398			`POC = 0x00000008 /* Power on configuration register */`
399			`end`
400
401
402			`/* UART SECTION`
403
404			`This section configures UARTs`
405
406			`enabled = 0/1`
407			`whether uarts are enabled`
408
409			`nuarts =`
410			`make specified number of instances, configure each`
411			`instance within device - enddevice construct.`
412
413			`instance specific:`
414			`baseaddr =`
415			`address of first UART register for this device`
416
417			`rx_file = ""`
418			`filename, where to read data from`
419
420			`tx_file = ""`
421			`filename, where to write data to`
422
423			`irq =`
424			`irq number for this device`
425
426			`16550 = 0/1`
427			`0, if this device is uart 16450 and 1, if it is 16550`
428
429			`jitter =`
430			`in msecs... time to block, -1 to disable it`
431
432			`vapi_id =`
433			`VAPI id of this instance`
434			`*/`
435
436			`section uart`
437			`enabled = 0`
438			`nuarts = 1`
439
440			`device 0`
441			`baseaddr = 0x80000000`
442			`irq = 2`
443			`rxfile = "/tmp/uart0.rx"`
444			`txfile = "/tmp/uart0.tx"`
445			`jitter = -1 /* async behaviour */`
446			`enddevice`
447			`end`
448
449
450			`/* DMA SECTION`
451
452			`This section configures DMAs`
453
454			`enabled = 0/1`
455			`whether DMAs are enabled`
456
457			`ndmas =`
458			`make specified number of instances, configure each`
459			`instance within device - enddevice construct.`
460
461			`instance specific:`
462			`baseaddr =`
463			`address of first DMA register for this device`
464
465			`irq =`
466			`irq number for this device`
467
468			`vapi_id =`
469			`VAPI id of this instance`
470			`*/`
471
472			`section dma`
473			`enabled = 0`
474			`ndmas = 1`
475
476			`device 0`
477			`baseaddr = 0x90000000`
478			`irq = 4`
479			`enddevice`
480			`end`
481
482
483			`/* ETHERNET SECTION`
484
485			`This section configures ethernets`
486
487			`enabled = 0/1`
488			`whether ethernets are enabled`
489
490			`nethernets =`
491			`make specified number of instances, configure each`
492			`instance within device - enddevice construct.`
493
494			`instance specific:`
495			`baseaddr =`
496			`address of first ethernet register for this device`
497
498			`dma =`
499			`which controller is this ethernet "connected" to`
500
501			`rx_channel =`
502			`DMA channel used for RX`
503
504			`tx_channel =`
505			`DMA channel used for TX`
506
507			`rx_file = ""`
508			`filename, where to read data from`
509
510			`tx_file = ""`
511			`filename, where to write data to`
512
513			`vapi_id =`
514			`VAPI id of this instance`
515			`*/`
516
517			`section ethernet`
518			`enabled = 0`
519			`nethernets = 1`
520
521			`device 0`
522			`baseaddr = 0x88000000`
523			`dma = 0`
524			`tx_channel = 0`
525			`rx_channel = 1`
526			`rxfile = "/tmp/eth0.rx"`
527			`txfile = "/tmp/eth0.tx"`
528			`enddevice`
529			`end`
530
531			`/* TICK TIMER SECTION`
532
533			`This section configures tick timer`
534
535			`enabled = 0/1`
536			`whether tick timer is enabled`
537
538			`irq =`
539			`irq number`
540			`*/`
541
542			`section tick`
543			`enabled = 0`
544			`irq = 3`
545			`end`