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/* icache_model.c -- instruction cache simulation
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Cache functions.
   At the moment this functions only simulate functionality of instruction
   caches and do not influence on fetche/decode/execute stages and timings.
   They are here only to verify performance of various cache configurations.
 */
 
#include <stdio.h>
#include <string.h>
#include <errno.h>
#include <stdarg.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "abstract.h"
#include "icache_model.h"
#include "except.h"
#include "opcode/or32.h"
#include "stats.h"
#include "sim-config.h"
#include "spr_defs.h"
#include "sprs.h"
#include "sim-config.h"
 
extern struct dev_memarea *cur_area;
struct ic_set {
  struct {
    uint32_t line[MAX_IC_BLOCK_SIZE];
    oraddr_t tagaddr;  /* tag address */
    int lru;    /* least recently used */
  } way[MAX_IC_WAYS];
} ic[MAX_IC_SETS];
 
void ic_info()
{
  if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {
    PRINTF("ICache not implemented. Set UPR[ICP].\n");
    return;
  }
 
  PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);
  PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);
}
 
/* First check if instruction is already in the cache and if it is:
    - increment IC read hit stats,
    - set 'lru' at this way to config.ic.ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
    - read insn from the cache line
   and if not:
    - increment IC read miss stats
    - find lru way and entry and replace old tag with tag of the 'fetchaddr'
    - set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
    - refill cache line
*/
 
uint32_t ic_simulate_fetch(oraddr_t fetchaddr)
{
  int set, way = -1;
  int i;
  oraddr_t tagaddr;
  uint32_t tmp;
 
  /* ICache simulation enabled/disabled. */
  if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) || (!testsprbits(SPR_SR, SPR_SR_ICE)) || insn_ci) {
    tmp = evalsim_mem32(fetchaddr);
    if(!cur_area) {
      printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             fetchaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      return 0;
    } else if (cur_area->log)
      fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,
               tmp);
    return tmp;
  }
 
  /* Which set to check out? */
  set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;
  tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;
 
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.ic.nways; i++)
    if (ic[set].way[i].tagaddr == tagaddr)
      way = i;
 
  /* Did we find our cached instruction? */
  if (way >= 0) { /* Yes, we did. */
    ic_stats.readhit++;
 
    for (i = 0; i < config.ic.nways; i++)
      if (ic[set].way[i].lru > ic[set].way[way].lru)
        ic[set].way[i].lru--;
    ic[set].way[way].lru = config.ic.ustates - 1;
    runtime.sim.mem_cycles += config.ic.hitdelay;
    return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
  }
  else {  /* No, we didn't. */
    int minlru = config.ic.ustates - 1;
    int minway = 0;
 
    ic_stats.readmiss++;
 
    for (i = 0; i < config.ic.nways; i++) {
      if (ic[set].way[i].lru < minlru) {
        minway = i;
        minlru = ic[set].way[i].lru;
      }
    }
 
    for (i = 0; i < (config.ic.blocksize); i += 4) {
      tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =
        evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));
      if(!cur_area) {
        ic[set].way[minway].tagaddr = -1;
        ic[set].way[minway].lru = 0;
        printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
               fetchaddr);
        except_handle(EXCEPT_BUSERR, cur_vadd);
        return 0;
      } else if (cur_area->log)
        fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",
                 fetchaddr, tmp);
    }
 
    ic[set].way[minway].tagaddr = tagaddr;
    for (i = 0; i < config.ic.nways; i++)
      if (ic[set].way[i].lru)
        ic[set].way[i].lru--;
    ic[set].way[minway].lru = config.ic.ustates - 1;
    runtime.sim.mem_cycles += config.ic.missdelay;
    return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);
  }
}
 
/* First check if data is already in the cache and if it is:
    - invalidate block if way isn't locked
   otherwise don't do anything.
*/
 
void ic_inv(oraddr_t dataaddr)
{
  int set, way = -1;
  int i;
  oraddr_t tagaddr;
 
  if (!testsprbits(SPR_UPR, SPR_UPR_ICP))
    return;
 
  /* Which set to check out? */
  set = (dataaddr / config.ic.blocksize) % config.ic.nsets;
  tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets;
 
  if (!testsprbits(SPR_SR, SPR_SR_ICE)) {
    for (i = 0; i < config.ic.nways; i++) {
      ic[set].way[i].tagaddr = -1;
      ic[set].way[i].lru = 0;
    }
    return;
  }
 
  /* Scan all ways and try to find a matching way. */
  for (i = 0; i < config.ic.nways; i++)
    if (ic[set].way[i].tagaddr == tagaddr)
      way = i;
 
  /* Did we find our cached data? */
  if (way >= 0) { /* Yes, we did. */
    ic[set].way[way].tagaddr = -1;
    ic[set].way[way].lru = 0;
  }
}
 
/*-----------------------------------------------------[ IC configuration ]---*/
void ic_enabled(union param_val val, void *dat)
{
  config.ic.enabled = val.int_val;
  setsprbits (SPR_UPR, SPR_UPR_ICP, val.int_val ? 1 : 0);
}
 
void ic_nsets(union param_val val, void *dat)
{
  if (is_power2(val.int_val) && val.int_val <= MAX_IC_SETS){
    config.ic.nsets = val.int_val;
    setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCS,log2(val.int_val));
  }
  else {
    char tmp[200];
    sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_IC_SETS);
    CONFIG_ERROR(tmp);
  }
}
 
void ic_nways(union param_val val, void *dat)
{
  if (is_power2(val.int_val) && val.int_val <= MAX_IC_WAYS) {
    config.ic.nways = val.int_val;
    setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCW, log2(val.int_val));
  }
  else {
    char tmp[200];
    sprintf (tmp, "value of power of two and lower or equal than %i expected.",
    MAX_IC_WAYS);
    CONFIG_ERROR(tmp);
  }
}
 
void ic_blocksize(union param_val val, void *dat)
{
  if (is_power2(val.int_val)){
    config.ic.blocksize = val.int_val;
    setsprbits (SPR_ICCFGR, SPR_ICCFGR_CBS,log2(val.int_val));
  } else
    CONFIG_ERROR("value of power of two expected.");
}
 
void ic_ustates(union param_val val, void *dat)
{
  if (val.int_val >= 2 && val.int_val <= 4)
    config.ic.ustates = val.int_val;
  else
    CONFIG_ERROR("invalid USTATE.");
}
 
void ic_missdelay(union param_val val, void *dat)
{
  config.ic.missdelay = val.int_val;
}
 
void ic_hitdelay(union param_val val, void *dat)
{
  config.ic.hitdelay = val.int_val;
}
 
void reg_ic_sec(void)
{
  struct config_section *sec = reg_config_sec("ic", NULL, NULL);
 
  reg_config_param(sec, "enabled", paramt_int, ic_enabled);
  reg_config_param(sec, "nsets", paramt_int, ic_nsets);
  reg_config_param(sec, "nways", paramt_int, ic_nways);
  reg_config_param(sec, "blocksize", paramt_int, ic_blocksize);
  reg_config_param(sec, "ustates", paramt_int, ic_ustates);
  reg_config_param(sec, "missdelay", paramt_int, ic_missdelay);
  reg_config_param(sec, "hitdelay", paramt_int, ic_hitdelay);
}

Line No.	Rev	Author	Line
1	5	lampret	`/* icache_model.c -- instruction cache simulation`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20			`/* Cache functions.`
21			`At the moment this functions only simulate functionality of instruction`
22			`caches and do not influence on fetche/decode/execute stages and timings.`
23			`They are here only to verify performance of various cache configurations.`
24			`*/`
25
26			`#include <stdio.h>`
27			`#include <string.h>`
28			`#include <errno.h>`
29			`#include <stdarg.h>`
30
31	1350	nogj	`#include "config.h"`
32
33			`#ifdef HAVE_INTTYPES_H`
34			`#include <inttypes.h>`
35			`#endif`
36
37			`#include "port.h"`
38			`#include "arch.h"`
39			`#include "abstract.h"`
40	5	lampret	`#include "icache_model.h"`
41	992	simons	`#include "except.h"`
42	1344	nogj	`#include "opcode/or32.h"`
43	5	lampret	`#include "stats.h"`
44	102	lampret	`#include "sim-config.h"`
45			`#include "spr_defs.h"`
46	167	markom	`#include "sprs.h"`
47	428	markom	`#include "sim-config.h"`
48	5	lampret
49	631	simons	`extern struct dev_memarea *cur_area;`
50	5	lampret	`struct ic_set {`
51	428	markom	`struct {`
52	1350	nogj	`uint32_t line[MAX_IC_BLOCK_SIZE];`
53			`oraddr_t tagaddr; /* tag address */`
54	428	markom	`int lru; /* least recently used */`
55			`} way[MAX_IC_WAYS];`
56			`} ic[MAX_IC_SETS];`
57	5	lampret
58			`void ic_info()`
59			`{`
60	428	markom	`if (!testsprbits(SPR_UPR, SPR_UPR_ICP)) {`
61	997	markom	`PRINTF("ICache not implemented. Set UPR[ICP].\n");`
62	428	markom	`return;`
63			`}`
64	102	lampret
65	997	markom	`PRINTF("Instruction cache %dKB: ", config.ic.nsets * config.ic.blocksize * config.ic.nways / 1024);`
66			`PRINTF("%d ways, %d sets, block size %d bytes\n", config.ic.nways, config.ic.nsets, config.ic.blocksize);`
67	5	lampret	`}`
68
69			`/* First check if instruction is already in the cache and if it is:`
70			`- increment IC read hit stats,`
71	428	markom	`- set 'lru' at this way to config.ic.ustates - 1 and`
72	5	lampret	`decrement 'lru' of other ways unless they have reached 0,`
73	631	simons	`- read insn from the cache line`
74	5	lampret	`and if not:`
75			`- increment IC read miss stats`
76			`- find lru way and entry and replace old tag with tag of the 'fetchaddr'`
77	428	markom	`- set 'lru' with config.ic.ustates - 1 and decrement 'lru' of other`
78	5	lampret	`ways unless they have reached 0`
79	631	simons	`- refill cache line`
80	5	lampret	`*/`
81
82	1350	nogj	`uint32_t ic_simulate_fetch(oraddr_t fetchaddr)`
83	5	lampret	`{`
84	428	markom	`int set, way = -1;`
85			`int i;`
86	1350	nogj	`oraddr_t tagaddr;`
87			`uint32_t tmp;`
88	102	lampret
89	428	markom	`/* ICache simulation enabled/disabled. */`
90	992	simons	`if ((!testsprbits(SPR_UPR, SPR_UPR_ICP)) \|\| (!testsprbits(SPR_SR, SPR_SR_ICE)) \|\| insn_ci) {`
91			`tmp = evalsim_mem32(fetchaddr);`
92			`if(!cur_area) {`
93	1350	nogj	`printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
94			`fetchaddr);`
95	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
96			`return 0;`
97	1386	nogj	`} else if (cur_area->log)`
98	1350	nogj	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", fetchaddr,`
99			`tmp);`
100	992	simons	`return tmp;`
101			`}`
102	428	markom
103			`/* Which set to check out? */`
104			`set = (fetchaddr / config.ic.blocksize) % config.ic.nsets;`
105			`tagaddr = (fetchaddr / config.ic.blocksize) / config.ic.nsets;`
106
107			`/* Scan all ways and try to find a matching way. */`
108			`for (i = 0; i < config.ic.nways; i++)`
109			`if (ic[set].way[i].tagaddr == tagaddr)`
110			`way = i;`
111
112			`/* Did we find our cached instruction? */`
113			`if (way >= 0) { /* Yes, we did. */`
114			`ic_stats.readhit++;`
115
116			`for (i = 0; i < config.ic.nways; i++)`
117	631	simons	`if (ic[set].way[i].lru > ic[set].way[way].lru)`
118	428	markom	`ic[set].way[i].lru--;`
119			`ic[set].way[way].lru = config.ic.ustates - 1;`
120	884	markom	`runtime.sim.mem_cycles += config.ic.hitdelay;`
121	631	simons	`return (ic[set].way[way].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);`
122	428	markom	`}`
123			`else { /* No, we didn't. */`
124			`int minlru = config.ic.ustates - 1;`
125			`int minway = 0;`
126	5	lampret
127	631	simons	`ic_stats.readmiss++;`
128	5	lampret
129	1085	simons	`for (i = 0; i < config.ic.nways; i++) {`
130			`if (ic[set].way[i].lru < minlru) {`
131	428	markom	`minway = i;`
132	1085	simons	`minlru = ic[set].way[i].lru;`
133			`}`
134			`}`
135	428	markom
136	631	simons	`for (i = 0; i < (config.ic.blocksize); i += 4) {`
137	992	simons	`tmp = ic[set].way[minway].line[((fetchaddr + i) & (config.ic.blocksize - 1)) >> 2] =`
138	631	simons	`evalsim_mem32((fetchaddr & ~(config.ic.blocksize - 1)) + ((fetchaddr + i) & (config.ic.blocksize - 1)));`
139	638	simons	`if(!cur_area) {`
140			`ic[set].way[minway].tagaddr = -1;`
141			`ic[set].way[minway].lru = 0;`
142	1350	nogj	`printf("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
143			`fetchaddr);`
144	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
145	631	simons	`return 0;`
146	1386	nogj	`} else if (cur_area->log)`
147	1350	nogj	`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n",`
148			`fetchaddr, tmp);`
149	631	simons	`}`
150
151	428	markom	`ic[set].way[minway].tagaddr = tagaddr;`
152			`for (i = 0; i < config.ic.nways; i++)`
153	631	simons	`if (ic[set].way[i].lru)`
154	428	markom	`ic[set].way[i].lru--;`
155			`ic[set].way[minway].lru = config.ic.ustates - 1;`
156	884	markom	`runtime.sim.mem_cycles += config.ic.missdelay;`
157	631	simons	`return (ic[set].way[minway].line[(fetchaddr & (config.ic.blocksize - 1)) >> 2]);`
158	428	markom	`}`
159	5	lampret	`}`
160	102	lampret
161			`/* First check if data is already in the cache and if it is:`
162			`- invalidate block if way isn't locked`
163			`otherwise don't do anything.`
164			`*/`
165
166	1350	nogj	`void ic_inv(oraddr_t dataaddr)`
167	102	lampret	`{`
168	428	markom	`int set, way = -1;`
169			`int i;`
170	1350	nogj	`oraddr_t tagaddr;`
171	102	lampret
172	428	markom	`if (!testsprbits(SPR_UPR, SPR_UPR_ICP))`
173			`return;`
174	102	lampret
175	428	markom	`/* Which set to check out? */`
176			`set = (dataaddr / config.ic.blocksize) % config.ic.nsets;`
177			`tagaddr = (dataaddr / config.ic.blocksize) / config.ic.nsets;`
178	631	simons
179			`if (!testsprbits(SPR_SR, SPR_SR_ICE)) {`
180			`for (i = 0; i < config.ic.nways; i++) {`
181			`ic[set].way[i].tagaddr = -1;`
182			`ic[set].way[i].lru = 0;`
183			`}`
184			`return;`
185			`}`
186	428	markom
187			`/* Scan all ways and try to find a matching way. */`
188			`for (i = 0; i < config.ic.nways; i++)`
189			`if (ic[set].way[i].tagaddr == tagaddr)`
190			`way = i;`
191
192			`/* Did we find our cached data? */`
193	631	simons	`if (way >= 0) { /* Yes, we did. */`
194	428	markom	`ic[set].way[way].tagaddr = -1;`
195	631	simons	`ic[set].way[way].lru = 0;`
196	428	markom	`}`
197	102	lampret	`}`
198
199	1358	nogj	`/-----------------------------------------------------[ IC configuration ]---/`
200			`void ic_enabled(union param_val val, void *dat)`
201			`{`
202			`config.ic.enabled = val.int_val;`
203			`setsprbits (SPR_UPR, SPR_UPR_ICP, val.int_val ? 1 : 0);`
204			`}`
205
206			`void ic_nsets(union param_val val, void *dat)`
207			`{`
208	1382	nogj	`if (is_power2(val.int_val) && val.int_val <= MAX_IC_SETS){`
209	1358	nogj	`config.ic.nsets = val.int_val;`
210	1382	nogj	`setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCS,log2(val.int_val));`
211			`}`
212	1358	nogj	`else {`
213			`char tmp[200];`
214			`sprintf (tmp, "value of power of two and lower or equal than %i expected.", MAX_IC_SETS);`
215			`CONFIG_ERROR(tmp);`
216			`}`
217			`}`
218
219			`void ic_nways(union param_val val, void *dat)`
220			`{`
221	1382	nogj	`if (is_power2(val.int_val) && val.int_val <= MAX_IC_WAYS) {`
222	1358	nogj	`config.ic.nways = val.int_val;`
223	1382	nogj	`setsprbits (SPR_ICCFGR, SPR_ICCFGR_NCW, log2(val.int_val));`
224			`}`
225			`else {`
226			`char tmp[200];`
227			`sprintf (tmp, "value of power of two and lower or equal than %i expected.",`
228			`MAX_IC_WAYS);`
229			`CONFIG_ERROR(tmp);`
230			`}`
231	1358	nogj	`}`
232
233			`void ic_blocksize(union param_val val, void *dat)`
234			`{`
235	1382	nogj	`if (is_power2(val.int_val)){`
236	1358	nogj	`config.ic.blocksize = val.int_val;`
237	1382	nogj	`setsprbits (SPR_ICCFGR, SPR_ICCFGR_CBS,log2(val.int_val));`
238			`} else`
239	1358	nogj	`CONFIG_ERROR("value of power of two expected.");`
240			`}`
241
242			`void ic_ustates(union param_val val, void *dat)`
243			`{`
244			`if (val.int_val >= 2 && val.int_val <= 4)`
245			`config.ic.ustates = val.int_val;`
246			`else`
247			`CONFIG_ERROR("invalid USTATE.");`
248			`}`
249
250			`void ic_missdelay(union param_val val, void *dat)`
251			`{`
252			`config.ic.missdelay = val.int_val;`
253			`}`
254
255			`void ic_hitdelay(union param_val val, void *dat)`
256			`{`
257			`config.ic.hitdelay = val.int_val;`
258			`}`
259
260			`void reg_ic_sec(void)`
261			`{`
262	1406	nogj	`struct config_section *sec = reg_config_sec("ic", NULL, NULL);`
263	1358	nogj
264			`reg_config_param(sec, "enabled", paramt_int, ic_enabled);`
265			`reg_config_param(sec, "nsets", paramt_int, ic_nsets);`
266			`reg_config_param(sec, "nways", paramt_int, ic_nways);`
267			`reg_config_param(sec, "blocksize", paramt_int, ic_blocksize);`
268			`reg_config_param(sec, "ustates", paramt_int, ic_ustates);`
269			`reg_config_param(sec, "missdelay", paramt_int, ic_missdelay);`
270			`reg_config_param(sec, "hitdelay", paramt_int, ic_hitdelay);`
271			`}`

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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [cache/] [icache_model.c] - Blame information for rev 1765