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/* dmmu.c -- Data MMU simulation

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* DMMU model (not functional yet, currently just copy of data cache). */

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "dmmu.h"

#include "abstract.h"

#include "opcode/or32.h"

#include "stats.h"

#include "sprs.h"

#include "except.h"

#include "sim-config.h"

#include "debug.h"

DEFAULT_DEBUG_CHANNEL(dmmu);

extern int cont_run;

/* Data MMU */

inline oraddr_t dmmu_simulate_tlb(oraddr_t virtaddr, int write_access)

{

  int set, way = -1;

  int i;

  oraddr_t tagaddr;

  oraddr_t vpn, ppn;

  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {

    data_ci = (virtaddr >= 0x80000000);

    return virtaddr;

  }

  /* Which set to check out? */

  set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;

  tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;

  vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);

  /* Scan all ways and try to find a matching way. */

  for (i = 0; i < config.dmmu.nways; i++)

    if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&

        testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))

      way = i;

   /* Did we find our tlb entry? */

  if (way >= 0) { /* Yes, we did. */

    dmmu_stats.loads_tlbhit++;

    TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,

          runtime.sim.cycles);

    /* Set LRUs */

    for (i = 0; i < config.dmmu.nways; i++)

      if (testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))

        setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);

    setsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU, config.dmmu.nsets - 1);

    /* Check if page is cache inhibited */

    data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;

    runtime.sim.mem_cycles += config.dmmu.hitdelay;

    ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;

    /* Test for page fault */

    if (mfspr (SPR_SR) & SPR_SR_SM) {

      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)

       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))

        except_handle(EXCEPT_DPF, virtaddr);

    } else {

      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)

       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))

        except_handle(EXCEPT_DPF, virtaddr);

    }

    return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);

  }

  else {  /* No, we didn't. */

    dmmu_stats.loads_tlbmiss++;

#if 0

    for (i = 0; i < config.dmmu.nways; i++)

      if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) < minlru)

        minway = i;

    setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_VPN, vpn);

    for (i = 0; i < config.dmmu.nways; i++)

      if (getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU))

        setsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU, getsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_LRU) - 1);

    setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_LRU, config.dmmu.ustates - 1);

    setsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN, vpn); /* 1 to 1 */

    setsprbits(SPR_DTLBMR_BASE(minway) + set, SPR_DTLBMR_V, 1);

#endif

    TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,

          runtime.sim.cycles);

    runtime.sim.mem_cycles += config.dmmu.missdelay;

    /* if tlb refill implemented in HW */

    /* return getsprbits(SPR_DTLBTR_BASE(minway) + set, SPR_DTLBTR_PPN) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */

    except_handle(EXCEPT_DTLBMISS, virtaddr);

    return 0;

  }

}

/* DESC: try to find EA -> PA transaltion without changing

 *       any of precessor states. if this is not passible gives up

 *       (without triggering exceptions)

 *

 * PRMS: virtaddr     - EA for which to find translation

 *

 *       write_access - 0 ignore testing for write access

 *                      1 test for write access, if fails

 *                        do not return translation

 *

 *       through_dc   - 1 go through data cache

 *                      0 ignore data cache

 *

 * RTRN: 0            - no DMMU, DMMU disabled or ITLB miss

 *       else         - appropriate PA (note it DMMU is not present

 *                      PA === EA)

 */

oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)

{

  int set, way = -1;

  int i;

  oraddr_t tagaddr;

  oraddr_t vpn, ppn;

  if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) {

    if (through_dc)

      data_ci = (virtaddr >= 0x80000000);

    return virtaddr;

  }

  /* Which set to check out? */

  set = (virtaddr / config.dmmu.pagesize) % config.dmmu.nsets;

  tagaddr = (virtaddr / config.dmmu.pagesize) / config.dmmu.nsets;

  vpn = virtaddr / (config.dmmu.pagesize * config.dmmu.nsets);

  /* Scan all ways and try to find a matching way. */

  for (i = 0; i < config.dmmu.nways; i++)

    if (((mfspr(SPR_DTLBMR_BASE(i) + set) / (config.dmmu.pagesize * config.dmmu.nsets)) == vpn) &&

        testsprbits(SPR_DTLBMR_BASE(i) + set, SPR_DTLBMR_V))

      way = i;

   /* Did we find our tlb entry? */

  if (way >= 0) { /* Yes, we did. */

    dmmu_stats.loads_tlbhit++;

    TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,

          runtime.sim.cycles);

    /* Test for page fault */

    if (mfspr (SPR_SR) & SPR_SR_SM) {

      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SWE)

       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_SRE))

        /* otherwise exception DPF would be raised */

        return(0);

    } else {

      if ( write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_UWE)

       || !write_access && !(mfspr (SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_URE))

        /* otherwise exception DPF would be raised */

        return(0);

    }

    if (through_dc) {

      /* Check if page is cache inhibited */

      data_ci = (mfspr(SPR_DTLBTR_BASE(way) + set) & SPR_DTLBTR_CI) == SPR_DTLBTR_CI;

    }

    ppn = mfspr(SPR_DTLBTR_BASE(way) + set) / config.dmmu.pagesize;

    return (ppn * config.dmmu.pagesize) + (virtaddr % config.dmmu.pagesize);

  }

  else {  /* No, we didn't. */

    return(0);

  }

  ERR("ERR, should never have happened\n");

  return(0);

}

oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)

{

  oraddr_t phyaddr = dmmu_simulate_tlb(virtaddr, write_access);

/*  PRINTF("DMMU translate(%"PRIxADDR") = %"PRIxADDR"\n", virtaddr, phyaddr);*/

  return phyaddr;

}

void dtlb_info()

{

  if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {

    PRINTF("DMMU not implemented. Set UPR[DMP].\n");

    return;

  }

  PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);

  PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);

}

/* First check if virtual address is covered by DTLB and if it is:

    - increment DTLB read hit stats,

    - set 'lru' at this way to config.dmmu.ustates - 1 and

      decrement 'lru' of other ways unless they have reached 0,

    - check page access attributes and invoke DMMU page fault exception

      handler if necessary

   and if not:

    - increment DTLB read miss stats

    - find lru way and entry and invoke DTLB miss exception handler

    - set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other

      ways unless they have reached 0

*/

void dtlb_status(int start_set)

{

  int set;

  int way;

  int end_set = config.dmmu.nsets;

  if (!testsprbits(SPR_UPR, SPR_UPR_DMP)) {

    PRINTF("DMMU not implemented. Set UPR[DMP].\n");

    return;

  }

  if ((start_set >= 0) && (start_set < end_set))

    end_set = start_set + 1;

  else

    start_set = 0;

  if (start_set < end_set) PRINTF("\nDMMU: ");

  /* Scan set(s) and way(s). */

  for (set = start_set; set < end_set; set++) {

    PRINTF("\nSet %x: ", set);

    for (way = 0; way < config.dmmu.nways; way++) {

      PRINTF("  way %d: ", way);

      PRINTF("vpn=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_VPN));

      PRINTF("lru=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_LRU));

      PRINTF("pl1=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_PL1));

      PRINTF("v=%lx ", getsprbits(SPR_DTLBMR_BASE(way) + set, SPR_DTLBMR_V));

      PRINTF("a=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_A));

      PRINTF("d=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_D));

      PRINTF("ure=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_URE));

      PRINTF("uwe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_UWE));

      PRINTF("sre=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SRE));

      PRINTF("swe=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_SWE));

      PRINTF("ppn=%lx ", getsprbits(SPR_DTLBTR_BASE(way) + set, SPR_DTLBTR_PPN));

    }

  }

  if (start_set < end_set) PRINTF("\n");

}

/*---------------------------------------------------[ DMMU configuration ]---*/

void dmmu_enabled(union param_val val, void *dat)

{

  setsprbits (SPR_UPR, SPR_UPR_DMP, val.int_val ? 1 : 0);

  config.dmmu.enabled = val.int_val;

}

void dmmu_nsets(union param_val val, void *dat)

{

  if (is_power2(val.int_val) && val.int_val <= 256) {

    config.dmmu.nsets = val.int_val;

    setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTS, log2(val.int_val));

  }

  else

    CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");

}

void dmmu_nways(union param_val val, void *dat)

{

  if (val.int_val >= 1 && val.int_val <= 4) {

    config.dmmu.nways = val.int_val;

    setsprbits (SPR_DMMUCFGR, SPR_DMMUCFGR_NTW, val.int_val-1);

  }

  else

    CONFIG_ERROR("value 1, 2, 3 or 4 expected.");

}

void dmmu_pagesize(union param_val val, void *dat)

{

  if (is_power2(val.int_val))

    config.dmmu.pagesize = val.int_val;

  else

    CONFIG_ERROR("value of power of two expected.");

}

void dmmu_entrysize(union param_val val, void *dat)

{

  if (is_power2(val.int_val))

    config.dmmu.entrysize = val.int_val;

  else

    CONFIG_ERROR("value of power of two expected.");

}

void dmmu_ustates(union param_val val, void *dat)

{

  if (val.int_val >= 2 && val.int_val <= 4)

    config.dmmu.ustates = val.int_val;

  else

    CONFIG_ERROR("invalid USTATE.");

}

void dmmu_missdelay(union param_val val, void *dat)

{

  config.dmmu.missdelay = val.int_val;

}

void dmmu_hitdelay(union param_val val, void *dat)

{

  config.immu.hitdelay = val.int_val;

}

void reg_dmmu_sec(void)

{

  struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);

  reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);

  reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);

  reg_config_param(sec, "nways", paramt_int, dmmu_nways);

  reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);

  reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);

  reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);

  reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);

  reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);

}