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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 849

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 
 
33 
#include "abstract.h"
34 
#include "ethernet_i.h"
35 
#include "dma.h"
36 
#include "sim-config.h"
37 
#include "fields.h"
38 
#include "crc32.h"
39 
 
40 
static struct eth_device eths[MAX_ETHERNETS];
41 
 
42 702 ivang 
/* simulator interface */
43 
static void eth_reset_controller( struct eth_device *eth);
44 696 ivang 
/* register interface */
45 
static void eth_write32( unsigned long addr, unsigned long value );
46 
static unsigned long eth_read32( unsigned long addr );
47 
/* clock */
48 
static void eth_controller_tx_clock( struct eth_device * );
49 
static void eth_controller_rx_clock( struct eth_device * );
50 
/* utility functions */
51 
static int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr );
52 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
53 
static void eth_skip_rx_file( struct eth_device *, off_t );
54 
static void eth_rewind_rx_file( struct eth_device *, off_t );
55 
static void eth_rx_next_packet( struct eth_device * );
56 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
57 696 ivang 
/* ========================================================================= */
58 702 ivang 
/*  TX LOGIC                                                                 */
59 696 ivang 
/*---------------------------------------------------------------------------*/
60 
 
61 
/*
62 
 * TX clock
63 
 * Responsible for starting and finishing TX
64 
 */
65 
void eth_controller_tx_clock( struct eth_device *eth )
66 
{
67 702 ivang 
    int breakpoint = 0;
68 
    int bAdvance   = 1;
69 849 markom 
#ifdef HAVE_ETH_PHY
70 702 ivang 
    struct sockaddr_ll sll;
71 849 markom 
#endif /* HAVE_ETH_PHY */
72 702 ivang 
    long nwritten;
73 
    unsigned long read_word;
74 696 ivang 
 
75 
    switch (eth->tx.state) {
76 702 ivang 
        case ETH_TXSTATE_IDLE:
77 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
78 
 
79 
            /* wait for TxBuffer to be ready */
80 705 ivang 
                debug (3, "TX - entering state WAIT4BD (%d)\n", eth->tx.bd_index);
81 702 ivang 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
82 
        }
83 
        break;
84 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
85 702 ivang 
        /* Read buffer descriptor */
86 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
87 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
88 
 
89 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
90 
            /*****************/
91 
            /* initialize TX */
92 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
93 
            eth->tx.bytes_sent = 0;
94 
 
95 
            /*   Initialize error status bits */
96 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
97 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
98 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
99 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
100 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
101 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
102 
 
103 
            /* Find out minimum length */
104 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
105 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
106 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
107 
            else
108 
                eth->tx.minimum_length = eth->tx.packet_length;
109 
 
110 
            /* Find out maximum length */
111 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
112 
                eth->tx.maximum_length = eth->tx.packet_length;
113 
            else
114 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
115 
 
116 
            /* Do we need CRC on this packet? */
117 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
118 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
119 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
120 
                eth->tx.add_crc = 1;
121 
            else
122 
                eth->tx.add_crc = 0;
123 
 
124 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
125 
                eth->tx.crc_dly = 1;
126 
            else
127 
                eth->tx.crc_dly = 0;
128 
            /* XXX - For now we skip CRC calculation */
129 
 
130 
            debug( 3, "Ethernet: Starting TX of %u bytes (min. %u, max. %u)\n", eth->tx.packet_length,
131 
                   eth->tx.minimum_length, eth->tx.maximum_length );
132 
 
133 
            if (eth->rtx_type == ETH_RTX_FILE) {
134 
                /* write packet length to file */
135 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
136 
            }
137 
 
138 
            /************************************************/
139 
            /* start transmit with reading packet into FIFO */
140 
                debug (3, "TX - entering state READFIFO\n");
141 
            eth->tx.state = ETH_TXSTATE_READFIFO;
142 
        }
143 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
144 
            /* stop TX logic */
145 
                debug (3, "TX - entering state IDLE\n");
146 
            eth->tx.state = ETH_TXSTATE_IDLE;
147 
        }
148 
 
149 
        /* stay in this state if (TXEN && !READY) */
150 
        break;
151 696 ivang 
    case ETH_TXSTATE_READFIFO:
152 744 simons 
#if 1
153 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
154 
            read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
155 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
156 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
157 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
158 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
159 
            eth->tx.bytes_sent += 4;
160 
        }
161 744 simons 
#else
162 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
163 
            eth->tx_buff[eth->tx.bytes_sent] = eval_mem8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
164 
            eth->tx.bytes_sent += 1;
165 
        }
166 
#endif
167 702 ivang 
        else {
168 
            debug (3, "TX - entering state TRANSMIT\n");
169 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
170 
        }
171 
        break;
172 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
173 702 ivang 
        /* send packet */
174 
        switch (eth->rtx_type) {
175 
        case ETH_RTX_FILE:
176 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
177 
            break;
178 849 markom 
#ifdef HAVE_ETH_PHY
179 702 ivang 
        case ETH_RTX_SOCK:
180 
            memset(&sll, 0, sizeof(sll));
181 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
182 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
183 849 markom 
#endif /* HAVE_ETH_PHY */
184 702 ivang 
        }
185 
 
186 
        /* set BD status */
187 
        if (nwritten == eth->tx.packet_length) {
188 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
189 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
190 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
191 702 ivang 
 
192 705 ivang 
            debug (3, "TX - entering state IDLE\n");
193 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
194 
            debug (3, "send (%d)bytes OK\n", nwritten);
195 
        }
196 
        else {
197 
            /* XXX - implement retry mechanism here! */
198 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
199 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
200 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
201 
 
202 
                debug (3, "TX - entering state IDLE\n");
203 
            eth->tx.state = ETH_TXSTATE_IDLE;
204 
            debug (3, "send FAILED!\n");
205 
        }
206 
 
207 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
208 
 
209 
        /* advance to next BD */
210 
        if (bAdvance) {
211 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
212 
                            eth->tx.bd_index >= ETH_BD_COUNT )
213 
                eth->tx.bd_index = 0;
214 
            else
215 
                eth->tx.bd_index += 2;
216 
        }
217 
 
218 
        /* generate OK interrupt */
219 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
220 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
221 
        {
222 
            report_interrupt( eth->mac_int );
223 
        }
224 
 
225 
        break;
226 696 ivang 
    }
227 
}
228 
/* ========================================================================= */
229 
 
230 
 
231 
/* ========================================================================= */
232 702 ivang 
/*  RX LOGIC                                                                 */
233 696 ivang 
/*---------------------------------------------------------------------------*/
234 
 
235 
/*
236 
 * RX clock
237 
 * Responsible for starting and finishing RX
238 
 */
239 
void eth_controller_rx_clock( struct eth_device *eth )
240 
{
241 702 ivang 
    int i;
242 
    int breakpoint = 0;
243 
    long nread;
244 
    unsigned long send_word;
245 
 
246 
    fd_set rfds;
247 
 
248 696 ivang 
    switch (eth->rx.state) {
249 
    case ETH_RXSTATE_IDLE:
250 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
251 705 ivang 
                debug (3, "RX - entering state WAIT4BD (%d)\n", eth->rx.bd_index);
252 702 ivang 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
253 
        }
254 
        break;
255 
 
256 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
257 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
258 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
259 
 
260 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
261 
            /*****************/
262 
            /* Initialize RX */
263 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
264 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
265 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
266 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
267 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
268 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
269 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
270 
 
271 
            debug( 3,  "Ethernet: Starting RX\n" );
272 
 
273 
            /* Setup file to read from */
274 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
275 
                eth->rx.fd = eth->txfd;
276 
                eth->rx.offset = &(eth->loopback_offset);
277 
            } else {
278 
                eth->rx.fd = eth->rxfd;
279 
                eth->rx.offset = 0;
280 
            }
281 
                debug (3, "RX - entering state RECV\n");
282 
            eth->rx.state = ETH_RXSTATE_RECV;
283 
        }
284 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
285 
          debug (3, "RX - entering state IDLE\n");
286 
          eth->rx.state = ETH_RXSTATE_IDLE;
287 
        }
288 
        else {
289 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
290 705 ivang 
            if (nread > 0) {
291 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
292 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
293 
                  report_interrupt(eth->mac_int);
294 702 ivang 
            }
295 
        }
296 
        break;
297 
 
298 696 ivang 
    case ETH_RXSTATE_RECV:
299 702 ivang 
        switch (eth->rtx_type) {
300 
        case ETH_RTX_FILE:
301 
            /* Read packet length */
302 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
303 
                     < sizeof(eth->rx.packet_length) ) {
304 
                /* TODO: just do what real ethernet would do (some kind of error state) */
305 836 ivang 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %d)\n", eth->rx.packet_length );
306 702 ivang 
                cont_run = 0;
307 
                break;
308 
            }
309 
 
310 
            /* Packet must be big enough to hold a header */
311 
            if ( eth->rx.packet_length < ETH_HLEN ){
312 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
313 
                eth_rx_next_packet( eth );
314 
 
315 836 ivang 
                debug (3, "RX - entering state IDLE\n");
316 702 ivang 
                eth->rx.state = ETH_RXSTATE_IDLE;
317 
                break;
318 
            }
319 
 
320 
            eth->rx.bytes_read = 0;
321 
            eth->rx.bytes_left = eth->rx.packet_length;
322 
 
323 
            /* for now Read entire packet into memory */
324 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
325 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
326 702 ivang 
                debug (3, "Read %d from %d. Error!\n", nread, eth->rx.bytes_left);
327 844 ivang 
                eth->rx.error = 1;
328 
                break;
329 
            }
330 
 
331 
            eth->rx.packet_length = nread;
332 
            eth->rx.bytes_left = nread;
333 
            eth->rx.bytes_read = 0;
334 
 
335 
            debug (3, "RX - entering state WRITEFIFO\n");
336 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
337 
 
338 702 ivang 
            break;
339 
 
340 
        case ETH_RTX_SOCK:
341 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
342 744 simons 
 
343 
            if (nread == 0)
344 
                break;
345 
            else if (nread < 0) {
346 
                if ( errno != EAGAIN ) {
347 702 ivang 
                            debug (3, "recv() FAILED!\n");
348 
                            break;
349 
                        }
350 
                        else {
351 
                        break;
352 
                    }
353 744 simons 
            }
354 
            /* If not promiscouos mode, check the destination address */
355 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
356 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
357 
                /* Nothing for now */
358 
                }
359 
 
360 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
361 
                    eth->mac_address[4] != eth->rx_buff[1] ||
362 
                    eth->mac_address[3] != eth->rx_buff[2] ||
363 
                    eth->mac_address[2] != eth->rx_buff[3] ||
364 
                    eth->mac_address[1] != eth->rx_buff[4] ||
365 
                    eth->mac_address[0] != eth->rx_buff[5])
366 
                        break;
367 
            }
368 
 
369 841 simons 
            eth->rx.packet_length = nread;
370 
            eth->rx.bytes_left = nread;
371 
            eth->rx.bytes_read = 0;
372 
 
373 
            debug (3, "RX - entering state WRITEFIFO\n");
374 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
375 
 
376 702 ivang 
            break;
377 
        }
378 841 simons 
        break;
379 
 
380 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
381 744 simons 
#if 1
382 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
383 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
384 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
385 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
386 
        set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
387 
        /* update counters */
388 
        debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
389 
        eth->rx.bytes_left -= 4;
390 
        eth->rx.bytes_read += 4;
391 744 simons 
#else
392 
        set_mem8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint);
393 
        eth->rx.bytes_left -= 1;
394 
        eth->rx.bytes_read += 1;
395 
#endif
396 
 
397 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
398 
            /* Write result to bd */
399 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
400 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
401 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
402 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
403 702 ivang 
 
404 
            if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
405 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
406 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
407 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
408 
 
409 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
410 
 
411 
            /* advance to next BD */
412 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
413 705 ivang 
                eth->rx.bd_index = eth->regs.tx_bd_num;
414 702 ivang 
            else
415 705 ivang 
                eth->rx.bd_index += 2;
416 702 ivang 
 
417 705 ivang 
            if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXB_M) ) {
418 702 ivang 
                report_interrupt( eth->mac_int );
419 
            }
420 
 
421 
            /* ready to receive next packet */
422 
                debug (3, "RX - entering state IDLE\n");
423 
            eth->rx.state = ETH_RXSTATE_IDLE;
424 
        }
425 
        break;
426 696 ivang 
    }
427 
}
428 702 ivang 
 
429 696 ivang 
/* ========================================================================= */
430 702 ivang 
/* Move to next RX BD */
431 
void eth_rx_next_packet( struct eth_device *eth )
432 
{
433 
    /* Skip any possible leftovers */
434 
    if ( eth->rx.bytes_left )
435 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
436 
}
437 
/* "Skip" bytes in RX file */
438 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
439 
{
440 
    eth->rx.offset += count;
441 
}
442 696 ivang 
 
443 702 ivang 
/* Move RX file position back */
444 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
445 
{
446 
    eth->rx.offset -= count;
447 
}
448 
/*
449 
 * Utility function to read from the ethernet RX file
450 
 * This function moves the file pointer to the current place in the packet before reading
451 
 */
452 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
453 
{
454 
    ssize_t result;
455 
 
456 
    if ( eth->rx.fd <= 0 ) {
457 
        debug( 3,  "Ethernet: No RX file\n" );
458 
        return 0;
459 
    }
460 
 
461 
    if ( eth->rx.offset )
462 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
463 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
464 
            return 0;
465 
        }
466 696 ivang 
 
467 702 ivang 
    result = read( eth->rx.fd, buf, count );
468 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
469 702 ivang 
    if ( eth->rx.offset && result >= 0 )
470 
        *(eth->rx.offset) += result;
471 
 
472 
    return result;
473 
}
474 
 
475 
/* ========================================================================= */
476 
 
477 696 ivang 
/*
478 702 ivang 
  Reset. Initializes all registers to default and places devices in
479 
         memory address space.
480 696 ivang 
*/
481 
void eth_reset()
482 
{
483 
    static int first_time = 1;
484 
    unsigned i;
485 
 
486 
    if (!config.nethernets)
487 702 ivang 
        return;
488 696 ivang 
 
489 841 simons 
    if ( first_time )
490 702 ivang 
        memset( eths, 0, sizeof(eths) );
491 696 ivang 
 
492 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
493 702 ivang 
        struct eth_device *eth = &(eths[i]);
494 
 
495 849 markom 
        if (!HAVE_ETH_PHY && eth->rtx_type == ETH_RTX_SOCK) {
496 
          fprintf (stderr, "Ethernet phy not enabled in this configuration.  Configure with --enable-ethphy.\n");
497 
          exit (1);
498 
        }
499 702 ivang 
        eth->eth_number = i;
500 
        eth_reset_controller( eth );
501 841 simons 
        if ( eth->baseaddr && first_time )
502 
            register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
503 696 ivang 
    }
504 841 simons 
 
505 
    if ( first_time )
506 
        first_time = 0;
507 696 ivang 
}
508 841 simons 
 
509 696 ivang 
/* ========================================================================= */
510 
 
511 
 
512 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
513 
{
514 
    int i = eth->eth_number;
515 
    int j;
516 849 markom 
#ifdef HAVE_ETH_PHY
517 702 ivang 
    struct sockaddr_ll sll;
518 849 markom 
#endif /* HAVE_ETH_PHY */
519 702 ivang 
 
520 
    eth->baseaddr = config.ethernets[i].baseaddr;
521 
 
522 
    if ( eth->baseaddr != 0 ) {
523 
        /* Mark which DMA controller and channels */
524 
        eth->dma        = config.ethernets[i].dma;
525 725 ivang 
        eth->mac_int    = config.ethernets[i].irq;
526 702 ivang 
        eth->tx_channel = config.ethernets[i].tx_channel;
527 
        eth->rx_channel = config.ethernets[i].rx_channel;
528 725 ivang 
        eth->rtx_type   = config.ethernets[i].rtx_type;
529 702 ivang 
 
530 
        switch (eth->rtx_type) {
531 
        case ETH_RTX_FILE:
532 
            /* (Re-)open TX/RX files */
533 
            eth->rxfile = config.ethernets[i].rxfile;
534 
            eth->txfile = config.ethernets[i].txfile;
535 
 
536 
            if ( eth->rxfd > 0 )
537 
                close( eth->rxfd );
538 
            if ( eth->txfd > 0 )
539 
                close( eth->txfd );
540 
            eth->rxfd = eth->txfd = -1;
541 
 
542 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
543 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
544 
            if ( (eth->txfd = open( eth->txfile,
545 
                                    O_RDWR | O_CREAT | O_APPEND | O_SYNC,
546 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
547 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
548 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
549 
 
550 
            break;
551 849 markom 
#ifdef HAVE_ETH_PHY
552 702 ivang 
        case ETH_RTX_SOCK:
553 
            /* (Re-)open TX/RX sockets */
554 
            if (eth->rtx_sock != 0)
555 
                break;
556 
 
557 
            debug (3, "RTX oppening socket...\n");
558 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
559 
            if (eth->rtx_sock == -1) {
560 
                fprintf( stderr, "Cannot open rtx_sock.\n");
561 
                return;
562 
            }
563 
 
564 
            /* get interface index number */
565 
            debug (3, "RTX getting interface...\n");
566 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
567 725 ivang 
            strncpy(eth->ifr.ifr_name, config.ethernets[i].sockif, IFNAMSIZ);
568 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
569 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
570 
                return;
571 
            }
572 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
573 
 
574 
            /* Bind to interface... */
575 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
576 
            memset(&sll, 0xff, sizeof(sll));
577 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
578 
            sll.sll_protocol = htons(ETH_P_ALL);
579 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
580 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
581 
                fprintf( stderr, "Error bind().\n");
582 
                return;
583 
            }
584 
 
585 
            /* first, flush all received packets. */
586 
            debug (3, "Flush");
587 
            do {
588 
                fd_set fds;
589 
                struct timeval t;
590 
 
591 
                debug( 3, ".");
592 
                FD_ZERO(&fds);
593 
                FD_SET(eth->rtx_sock, &fds);
594 
                memset(&t, 0, sizeof(t));
595 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
596 
                if (j > 0)
597 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
598 
            } while (j);
599 
            debug (3, "\n");
600 
 
601 
            break;
602 849 markom 
#endif /* HAVE_ETH_PHY */
603 702 ivang 
        }
604 
 
605 
        /* Set registers to default values */
606 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
607 
        eth->regs.moder = 0x0000A000;
608 
        eth->regs.ipgt = 0x00000012;
609 
        eth->regs.ipgr1 = 0x0000000C;
610 
        eth->regs.ipgr2 = 0x00000012;
611 
        eth->regs.packetlen = 0x003C0600;
612 
        eth->regs.collconf = 0x000F003F;
613 
        eth->regs.miimoder = 0x00000064;
614 
        eth->regs.tx_bd_num = 0x00000080;
615 
 
616 
        /* Initialize TX/RX status */
617 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
618 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
619 
        eth->rx.bd_index = eth->regs.tx_bd_num;
620 
    }
621 
}
622 
/* ========================================================================= */
623 
 
624 
 
625 696 ivang 
/*
626 
  Print register values on stdout
627 
*/
628 
void eth_status( void )
629 
{
630 
    unsigned i;
631 
 
632 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
633 702 ivang 
        struct eth_device *eth = &(eths[i]);
634 
 
635 
        if ( eth->baseaddr == 0 )
636 
            continue;
637 
 
638 
        printf( "\nEthernet MAC %u at 0x%08X:\n", i, eth->baseaddr );
639 
        printf( "MODER        : 0x%08lX\n", eth->regs.moder );
640 
        printf( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
641 
        printf( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
642 
        printf( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
643 
        printf( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
644 
        printf( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
645 
        printf( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
646 
        printf( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
647 
        printf( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
648 
        printf( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
649 
        printf( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
650 
        printf( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
651 
        printf( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
652 
        printf( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
653 
        printf( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
654 
        printf( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
655 
        printf( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
656 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
657 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
658 744 simons 
        printf( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
659 
        printf( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
660 696 ivang 
    }
661 
}
662 
/* ========================================================================= */
663 
 
664 
 
665 
/*
666 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
667 
*/
668 
void eth_clock()
669 
{
670 
    unsigned i;
671 
 
672 
    for ( i = 0; i < config.nethernets; ++ i ) {
673 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
674 
        eth_controller_rx_clock( &(eths[i]) );
675 696 ivang 
    }
676 
}
677 
/* ========================================================================= */
678 
 
679 
 
680 
/*
681 
  Read a register
682 
*/
683 
unsigned long eth_read32( unsigned long addr )
684 
{
685 
    struct eth_device *eth;
686 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
687 
        printf( "eth_read32( 0x%08lX ): Not in registered range(s)\n", addr );
688 
        return 0;
689 696 ivang 
    }
690 
 
691 
    switch( addr ) {
692 
    case ETH_MODER: return eth->regs.moder;
693 
    case ETH_INT_SOURCE: return eth->regs.int_source;
694 
    case ETH_INT_MASK: return eth->regs.int_mask;
695 
    case ETH_IPGT: return eth->regs.ipgt;
696 
    case ETH_IPGR1: return eth->regs.ipgr1;
697 
    case ETH_IPGR2: return eth->regs.ipgr2;
698 
    case ETH_PACKETLEN: return eth->regs.packetlen;
699 
    case ETH_COLLCONF: return eth->regs.collconf;
700 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
701 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
702 
    case ETH_MIIMODER: return eth->regs.miimoder;
703 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
704 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
705 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
706 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
707 
    case ETH_MIISTATUS: return eth->regs.miistatus;
708 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
709 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
710 
                               (((unsigned long)eth->mac_address[1]) << 8) |
711 
                                 (unsigned long)eth->mac_address[0];
712 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
713 702 ivang 
                                 (unsigned long)eth->mac_address[4];
714 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
715 
    case ETH_HASH1: return eth->regs.hash1;
716 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
717 696 ivang 
    }
718 
 
719 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
720 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
721 696 ivang 
 
722 
    printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
723 
    cont_run = 0;
724 
    return 0;
725 
}
726 
/* ========================================================================= */
727 
 
728 
 
729 
/*
730 
  Write a register
731 
*/
732 
void eth_write32( unsigned long addr, unsigned long value )
733 
{
734 
    struct eth_device *eth;
735 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
736 
        printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
737 
    return;
738 696 ivang 
    }
739 
 
740 
    switch( addr ) {
741 841 simons 
    case ETH_MODER: eth->regs.moder = value; if (TEST_FLAG(value, ETH_MODER, RST)) eth_reset(); return;
742 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
743 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
744 
    case ETH_IPGT: eth->regs.ipgt = value; return;
745 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
746 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
747 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
748 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
749 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
750 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
751 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
752 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
753 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
754 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
755 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
756 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
757 
    case ETH_MAC_ADDR0:
758 702 ivang 
        eth->mac_address[0] = value & 0xFF;
759 
        eth->mac_address[1] = (value >> 8) & 0xFF;
760 
        eth->mac_address[2] = (value >> 16) & 0xFF;
761 
        eth->mac_address[3] = (value >> 24) & 0xFF;
762 
        return;
763 696 ivang 
    case ETH_MAC_ADDR1:
764 702 ivang 
        eth->mac_address[4] = value & 0xFF;
765 
        eth->mac_address[5] = (value >> 8) & 0xFF;
766 
        return;
767 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
768 
    case ETH_HASH1: eth->regs.hash1 = value; return;
769 702 ivang 
 
770 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
771 696 ivang 
    }
772 
 
773 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
774 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
775 
        return;
776 696 ivang 
    }
777 
 
778 
    printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
779 
    cont_run = 0;
780 
    return;
781 
}
782 
/* ========================================================================= */
783 
 
784 
 
785 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
786 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
787 
{
788 
    eth->rx.bd_index = eth->regs.tx_bd_num = value & 0xFF;
789 
}
790 
/* ========================================================================= */
791 
 
792 
 
793 696 ivang 
/*
794 
  Convert a memory address to a oontroller struct and relative address.
795 
  Return nonzero on success
796 
*/
797 
int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr )
798 
{
799 
    unsigned i;
800 
    *eth = NULL;
801 
 
802 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
803 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
804 
            *eth = &(eths[i]);
805 
        }
806 696 ivang 
 
807 
    /* verify we found a controller */
808 
    if ( *eth == NULL )
809 702 ivang 
        return 0;
810 696 ivang 
 
811 
    /* Verify legal address */
812 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
813 702 ivang 
        return 0;
814 696 ivang 
 
815 
    *reladdr = addr - (*eth)->baseaddr;
816 
    return 1;
817 
}

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