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/* mc.c -- Simulation of Memory Controller
         Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
 
         This file is part of OpenRISC 1000 Architectural Simulator.
 
         This program is free software; you can redistribute it and/or modify
         it under the terms of the GNU General Public License as published by
         the Free Software Foundation; either version 2 of the License, or
         (at your option) any later version.
 
         This program is distributed in the hope that it will be useful,
         but WITHOUT ANY WARRANTY; without even the implied warranty of
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
         GNU General Public License for more details.
 
         You should have received a copy of the GNU General Public License
         along with this program; if not, write to the Free Software
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
 
/* Enable memory controller, via:
  section mc
    enable = 1
    POC = 0x13243545
  end
 
   Limitations:
    - memory refresh is not simulated
 */
 
#include "mc.h"
#include "abstract.h"
#include "sim-config.h"
 
static struct mc mc;
 
void set_csc_tms (int i, unsigned long csc, unsigned long tms) {
  if (1);
}
 
/* Set a specific MC register with value. */
void mc_write_word(unsigned long addr, unsigned long value)
{
        int chipsel;
 
        debug("mc_write_word(%x,%08x)\n", addr, (unsigned)value);
 
  addr -= config.mc.baseaddr;
 
        switch (addr) {
          case MC_CSR:
            mc.csr = value;
            break;
          case MC_POC:
            fprintf (stderr, "warning: write to MC's POC register!");
            break;
          case MC_BA_MASK:
            mc.ba_mask = value;
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      mc.tms[addr >> 3] = value;
                    else
                      mc.csc[addr >> 3] = value;
 
                    set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
                    break;
                  } else
                        debug("write out of range (addr %x)\n", addr + config.mc.baseaddr);
        }
}
 
/* Read a specific MC register. */
unsigned long mc_read_word(unsigned long addr)
{
        unsigned char value = 0;
        int chipsel;
 
        debug("mc_read_word(%x)\n", addr);
 
  addr -= config.mc.baseaddr;
 
        switch (addr) {
          case MC_CSR:
            value = mc.csr;
            break;
          case MC_POC:
            value = mc.poc;
            break;
          case MC_BA_MASK:
            value = mc.ba_mask;
            break;
                default:
                  if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {
                    addr -= MC_CSC(0);
                    if ((addr >> 2) & 1)
                      value = mc.tms[addr >> 3];
                    else
                      value = mc.csc[addr >> 3];
                  } else
                        debug("read out of range (addr %x)\n", addr + config.mc.baseaddr);
            break;
        }
        return value;
}
 
/* Read POC register and init memory controler regs. */
void mc_reset()
{
  if (config.mc.enabled) {
        printf("Resetting memory controller.\n");
        memset(&mc, 0, sizeof(struct mc));
 
    mc.poc = config.mc.POC;
        register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);
  }
}
 
inline void mc_clock()
{
}

Line No.	Rev	Author	Line
1	239	markom	`/* mc.c -- Simulation of Memory Controller`
2			`Copyright (C) 2001 by Marko Mlinar, markom@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.`
19			`*/`
20
21			`/* Enable memory controller, via:`
22			`section mc`
23			`enable = 1`
24			`POC = 0x13243545`
25			`end`
26
27	261	markom	`Limitations:`
28			`- memory refresh is not simulated`
29	239	markom	`*/`
30
31			`#include "mc.h"`
32			`#include "abstract.h"`
33	261	markom	`#include "sim-config.h"`
34
35			`static struct mc mc;`
36
37			`void set_csc_tms (int i, unsigned long csc, unsigned long tms) {`
38			`if (1);`
39			`}`
40
41			`/* Set a specific MC register with value. */`
42			`void mc_write_word(unsigned long addr, unsigned long value)`
43			`{`
44			`int chipsel;`
45
46			`debug("mc_write_word(%x,%08x)\n", addr, (unsigned)value);`
47
48			`addr -= config.mc.baseaddr;`
49
50			`switch (addr) {`
51			`case MC_CSR:`
52			`mc.csr = value;`
53			`break;`
54			`case MC_POC:`
55			`fprintf (stderr, "warning: write to MC's POC register!");`
56			`break;`
57			`case MC_BA_MASK:`
58			`mc.ba_mask = value;`
59			`break;`
60			`default:`
61			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
62			`addr -= MC_CSC(0);`
63			`if ((addr >> 2) & 1)`
64			`mc.tms[addr >> 3] = value;`
65			`else`
66			`mc.csc[addr >> 3] = value;`
67
68			`set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);`
69			`break;`
70			`} else`
71			`debug("write out of range (addr %x)\n", addr + config.mc.baseaddr);`
72			`}`
73			`}`
74
75			`/* Read a specific MC register. */`
76			`unsigned long mc_read_word(unsigned long addr)`
77			`{`
78			`unsigned char value = 0;`
79			`int chipsel;`
80
81			`debug("mc_read_word(%x)\n", addr);`
82
83			`addr -= config.mc.baseaddr;`
84
85			`switch (addr) {`
86			`case MC_CSR:`
87			`value = mc.csr;`
88			`break;`
89			`case MC_POC:`
90			`value = mc.poc;`
91			`break;`
92			`case MC_BA_MASK:`
93			`value = mc.ba_mask;`
94			`break;`
95			`default:`
96			`if (addr >= MC_CSC(0) && addr <= MC_TMS(N_CE - 1)) {`
97			`addr -= MC_CSC(0);`
98			`if ((addr >> 2) & 1)`
99			`value = mc.tms[addr >> 3];`
100			`else`
101			`value = mc.csc[addr >> 3];`
102			`} else`
103			`debug("read out of range (addr %x)\n", addr + config.mc.baseaddr);`
104			`break;`
105			`}`
106			`return value;`
107			`}`
108
109			`/* Read POC register and init memory controler regs. */`
110			`void mc_reset()`
111			`{`
112			`if (config.mc.enabled) {`
113			`printf("Resetting memory controller.\n");`
114			`memset(&mc, 0, sizeof(struct mc));`
115
116			`mc.poc = config.mc.POC;`
117			`register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, mc_read_word, mc_write_word);`
118			`}`
119			`}`
120
121			`inline void mc_clock()`
122			`{`
123			`}`

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[/] [or1k/] [tags/] [nog_patch_52/] [or1ksim/] [peripheral/] [mc.c] - Blame information for rev 261