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/* config.h -- Simulator configuration header file
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
   This file is part of OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 2 of the License, or
   (at your option) any later version.
 
   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.
 
   You should have received a copy of the GNU General Public License
   along with this program; if not, write to the Free Software
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
#ifndef _CONFIG_H_
#define _CONFIG_H_
 
#include <stdio.h>
 
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
 
#define MAX_UARTS        4            /* Max. number of UARTs simulated */   
#define MAX_DMAS         4            /* Max. number of DMA controllers */
#define MAX_ETHERNETS    4            /* Max. number of Ethernet MACs   */
#define MAX_GPIOS        4            /* Max. number of GPIO modules    */
#define MAX_MEMORIES     16           /* Max. number of memory devices attached */
#define MAX_VGAS         4            /* Max. number of VGAs */
#define MAX_ATAS         4            /* Max. number of ATAS */
#define MAX_SBUF_LEN     256          /* Max. length of store buffer */
 
#define EXE_LOG_HARDWARE 0            /* Print out RTL states */
#define EXE_LOG_SIMPLE   1            /* Executed log prints out dissasembly */
#define EXE_LOG_SOFTWARE 2            /* Simple with some register output*/
 
#define STR_SIZE        (256)
 
struct config {
  struct {
    int enabled;                      /* Is tick timer enabled?  */
  } tick;
 
  int nuarts;
  struct {
    char rxfile[STR_SIZE];            /* Filename for RX */
    char txfile[STR_SIZE];            /* Filename for TX (required) */
    int jitter;                       /* CZ 250801 - in msecs...time to block */
    unsigned long baseaddr;           /* Naturally aligned base address */
    int irq;                          /* IRQ of this device */
    unsigned long vapi_id;            /* VAPI id for this instance */
    int uart16550;                    /* Whether this device is uart 16450 or 16550 */
  } uarts[MAX_UARTS];
 
  int ndmas;
  struct {
    unsigned long baseaddr;
    int irq;                          /* IRQ of this device */
    unsigned long vapi_id;            /* VAPI id for this instance */
  } dmas[MAX_DMAS];
 
  int nethernets;
  struct {
    unsigned long baseaddr;
    int irq;                          /* IRQ of this device */
    unsigned dma;                     /* Which controller is this ethernet "connected" to */
    unsigned rtx_type;                /* use file or socket interface */
    unsigned tx_channel;              /* DMA channel used for TX */
    unsigned rx_channel;              /* DMA channel used for RX */
    char rxfile[STR_SIZE];            /* Filename for RX */
    char txfile[STR_SIZE];            /* File for TX */
    char sockif[STR_SIZE];            /* Socket Interface name ('lo', 'eth1',...) */
    unsigned long base_vapi_id;       /* VAPI id for this instance */
  } ethernets[MAX_ETHERNETS];
 
  int ngpios;
  struct {
    unsigned long baseaddr;           /* Base address */
    int irq;                          /* IRQ of this device */
    unsigned long base_vapi_id;       /* First VAPI ID.  GPIO uses 8 consecutive IDs */
  } gpios[MAX_GPIOS];
 
  int nvgas;
  struct {
    unsigned long baseaddr;           /* Base address */
    int irq;                          /* IRQ of this device */
    int refresh_rate;                 /* Number of clocks per refresh */
    char filename[STR_SIZE];          /* Base file name; suffix of ####.bmp is added */
  } vgas[MAX_VGAS];
 
  struct {
    int enabled;                      /* Whether frame buffer is enabled */
    unsigned long baseaddr;           /* Base address of frame buffer register */
    int refresh_rate;                 /* Number of clocks per refresh */
    char filename[STR_SIZE];          /* Base file name; suffix of ####.bmp is added */
  } fb;
 
  struct {
    int enabled;                      /* Is keyboard enabled?  */
    unsigned long baseaddr;           /* Base address of frame buffer register */
    int irq;                          /* Irq number of this device */
    char rxfile[STR_SIZE];            /* Filename for RX */
  } kbd;
 
  struct {
    int enabled;                      /* is MC enabled? */
    unsigned long baseaddr;           /* Naturally aligned base address */
    unsigned POC;                     /* power on reset configuration register */
  } mc;
 
  int natas;
  struct {
    unsigned long baseaddr;           /* Naturally aligned base address */
    int  irq;                         /* Irq number of this device */
 
    int  dev_type0;                   /* ATA-device0 type: 0=none, 1=simulated hd, 2=local system hd */
    char dev_file0[STR_SIZE];         /* Filename for simulating HardDisk (device 0) */
    unsigned long dev_size0;          /* Size of simulated harddisk (device 0), in MBytes */
    int  dev_packet0;                 /* Device0 implements PACKET command set */
 
    int  dev_type1;                   /* ATA-device1 type: 0=none, 1=simulated hd, 2=local system hd */
    char dev_file1[STR_SIZE];         /* Filename for simulating HardDisk (device 1) */
    unsigned long dev_size1;          /* Size of simulated harddisk (device 1), in MBytes */
    int  dev_packet1;                 /* Device1 implements PACKET command set */
  } atas[MAX_ATAS];
 
  struct {
    int pattern;                      /* A user specified memory initialization pattern */
    int random_seed;                  /* Initialize the memory with random values, starting with seed */
    enum {
      MT_UNKNOWN,
      MT_PATTERN,
      MT_RANDOM
    } type;
    int nmemories;                    /* Number of attached memories */
    struct {
      int ce;                         /* Which ce this memory is associated with */
      unsigned long baseaddr;         /* Start address of the memory */
      unsigned long size;             /* Memory size */
      char name[STR_SIZE];            /* Memory type string */
      char log[STR_SIZE];             /* Memory log filename */
      int delayr;                     /* Read cycles */
      int delayw;                     /* Write cycles */
    } table[MAX_MEMORIES];
  } memory;
 
  struct {
    int enabled;                      /* Whether IMMU is enabled */
    int nways;                        /* Number of ITLB ways */
    int nsets;                        /* Number of ITLB sets */
    int pagesize;                     /* ITLB page size */
    int entrysize;                    /* ITLB entry size */
    int ustates;                      /* number of ITLB usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } immu;
 
  struct {
    int enabled;                      /* Whether DMMU is enabled */
    int nways;                        /* Number of DTLB ways */
    int nsets;                        /* Number of DTLB sets */
    int pagesize;                     /* DTLB page size */
    int entrysize;                    /* DTLB entry size */
    int ustates;                      /* number of DTLB usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } dmmu;
 
  struct {
    int enabled;                      /* Whether instruction cache is enabled */
    int nways;                        /* Number of IC ways */
    int nsets;                        /* Number of IC sets */
    int blocksize;                    /* IC entry size */
    int ustates;                      /* number of IC usage states */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
  } ic;
 
  struct {
    int enabled;                      /* Whether data cache is enabled */
    int nways;                        /* Number of DC ways */
    int nsets;                        /* Number of DC sets */
    int blocksize;                    /* DC entry size */
    int ustates;                      /* number of DC usage states */
    int store_missdelay;              /* How much cycles does the store miss cost */
    int store_hitdelay;               /* How much cycles does the store hit cost */
    int load_missdelay;               /* How much cycles does the load miss cost */
    int load_hitdelay;                /* How much cycles does the load hit cost */
  } dc;
 
  struct {
    int enabled;                      /* branch prediction buffer analysis */
    int sbp_bnf_fwd;                  /* Static branch prediction for l.bnf uses forward prediction */
    int sbp_bf_fwd;                   /* Static branch prediction for l.bf uses forward prediction */
    int btic;                         /* branch prediction target insn cache analysis */
    int missdelay;                    /* How much cycles does the miss cost */
    int hitdelay;                     /* How much cycles does the hit cost */
#if 0                                 
    int nways;                        /* Number of BP ways */
    int nsets;                        /* Number of BP sets */
    int blocksize;                    /* BP entry size */
    int ustates;                      /* number of BP usage states */
    int pstates;                      /* number of BP predict states */
#endif                                
  } bpb;
 
  struct {
    unsigned long upr;                /* Unit present register */
    unsigned long ver, rev;           /* Version register */
    int sr;                           /* Supervision register */
    int superscalar;                  /* superscalara analysis */
    int hazards;                      /* dependency hazards analysis */
    int dependstats;                  /* dependency statistics */
    int sbuf_len;                     /* length of store buffer, zero if disabled */
  } cpu;
 
  struct {
    int debug;                        /* Simulator debugging */
    int verbose;                      /* Force verbose output */
 
    int profile;                      /* Is profiler running */
    char prof_fn[STR_SIZE];           /* Profiler filename */
 
    int mprofile;                     /* Is memory profiler running */
    char mprof_fn[STR_SIZE];          /* Memory profiler filename */
 
    int history;                      /* instruction stream history analysis */
    int exe_log;                      /* Print out RTL states? */
    int exe_log_type;                 /* Type of log */
    int exe_log_start;                /* First instruction to log */
    int exe_log_end;                  /* Last instruction to log, -1 if continuous */
    int exe_log_marker;               /* If nonzero, place markers before each exe_log_marker instructions */
    char exe_log_fn[STR_SIZE];        /* RTL state comparison filename */
    int spr_log;                      /* Print out SPR states */
    char spr_log_fn[STR_SIZE];        /* SPR state log filename */
    char fstdout[STR_SIZE];           /* stdout filename */
    long clkcycle_ps;                 /* Clock duration in ps */
    long system_kfreq;                /* System frequency in kHz*/
  } sim;
 
  struct {
    int enabled;                      /* Whether is debug module enabled */
    int gdb_enabled;                  /* Whether is debugging with gdb possible */
    int server_port;                  /* A user specified port number for services */
    unsigned long vapi_id;            /* "Fake" vapi device id for JTAG proxy */
  } debug;
 
  struct {                            /* Verification API, part of Advanced Core Verification */
    int enabled;                      /* Whether is VAPI module enabled */
    int server_port;                  /* A user specified port number for services */
    int log_enabled;                  /* Whether to log the vapi requests */
    int hide_device_id;               /* Whether to log device ID for each request */
    char vapi_fn[STR_SIZE];           /* vapi log filename */
  } vapi;
 
  struct {
    int enabled;                      /* Whether power menagement is operational */
  } pm;
 
  struct {
    char timings_fn[STR_SIZE];        /* Filename of the timing table */
    int memory_order;                 /* Memory access stricness */
    int calling_convention;           /* Whether functions follow standard calling convention */
    int enable_bursts;                /* Whether burst are enabled */
    int no_multicycle;                /* When enabled no multicycle paths are generated */
  } cuc;
};
 
struct runtime {
  struct {
    FILE *fprof;                      /* Profiler file */
    FILE *fmprof;                     /* Memory profiler file */
    FILE *fexe_log;                   /* RTL state comparison file */
    FILE *fspr_log;                   /* SPR state log file */
    int init;                         /* Whether we are still initilizing sim */
    int script_file_specified;        /* Whether script file was already loaded */
    char *filename;                   /* Original Command Simulator file (CZ) */
    int output_cfg;                   /* Whether sim is to output cfg files */
    char script_fn[STR_SIZE];         /* Script file read */
    int iprompt;                      /* Interactive prompt */
    int cont_run;                     /* Continuos run versus single
                                         step tracing switch. */
    int cycles;                       /* Cycles counts fetch stages */
 
    int mem_cycles;                   /* Each cycle has counter of mem_cycles;
                                         this value is joined with cycles
                                         at the end of the cycle; no sim
                                         originated memory accesses should be
                                         performed inbetween. */
    int loadcycles;                   /* Load and store stalls */
    int storecycles;
  } sim;
 
  /* Command line parameters */
  struct {
    int profile;                      /* Whether profiling was enabled */
    int mprofile;                     /* Whether memory profiling was enabled */
  } simcmd;
 
  struct {
    unsigned long ifea;               /* Instruction fetch effective address */
    unsigned long lea;                /* Load effective address */
    unsigned long sea;                /* Store effective address */
    unsigned long ld;                 /* Load data */
    unsigned long sd;                 /* Store data */
    unsigned long lsea;               /* Load/Store effective address */
    int instructions;                 /* Instructions executed */
    int stalled;
    int hazardwait;                   /* how many cycles were wasted because of hazards */
    int supercycles;                  /* Superscalar cycles */
  } cpu;
 
  struct {
    int random_seed;                  /* Initialize the memory with random values, starting with seed */
  } memory;
 
  struct {                            /* Verification API, part of Advanced Core Verification */
    int enabled;                      /* Whether is VAPI module enabled */
    FILE *vapi_file;                  /* vapi file */
    int server_port;                  /* A user specified port number for services */
  } vapi;
 
/* CUC configuration parameters */
  struct {
    int mdelay[4];                  /* average memory delays in cycles
                                     {read single, read burst, write single, write burst} */
    double cycle_duration;          /* in ns */
  } cuc;
};
 
#if FAST_SIM
#include "fast_config.c"
#define IFF(x) if (x)
#else
extern struct config config;
#define IFF(x) if (1)
#endif
 
extern struct runtime runtime;
 
/* Read environment from a script file. Does not fail - assumes defaukt configuration instead. */
void read_script_file (char *filename);
 
/* Executes set sim command.  Returns nonzero if error.  */
void set_config_command (char *s);
 
/* Outputs C structure of current config to file */
void output_cfg (FILE *f);
 
#endif

Line No.	Rev	Author	Line
1	7	jrydberg	`/* config.h -- Simulator configuration header file`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19	428	markom
20			`#ifndef _CONFIG_H_`
21			`#define _CONFIG_H_`
22
23	173	markom	`#include <stdio.h>`
24
25	7	jrydberg	`/* Simulator configuration macros. Eventually this one will be a lot bigger. */`
26	30	lampret
27	672	markom	`#define MAX_UARTS 4 /* Max. number of UARTs simulated */`
28			`#define MAX_DMAS 4 /* Max. number of DMA controllers */`
29			`#define MAX_ETHERNETS 4 /* Max. number of Ethernet MACs */`
30			`#define MAX_GPIOS 4 /* Max. number of GPIO modules */`
31			`#define MAX_MEMORIES 16 /* Max. number of memory devices attached */`
32			`#define MAX_VGAS 4 /* Max. number of VGAs */`
33	876	rherveille	`#define MAX_ATAS 4 /* Max. number of ATAS */`
34	672	markom	`#define MAX_SBUF_LEN 256 /* Max. length of store buffer */`
35	424	markom
36	672	markom	`#define EXE_LOG_HARDWARE 0 /* Print out RTL states */`
37	675	markom	`#define EXE_LOG_SIMPLE 1 /* Executed log prints out dissasembly */`
38			`#define EXE_LOG_SOFTWARE 2 /* Simple with some register output*/`
39	672	markom
40	239	markom	`#define STR_SIZE (256)`
41
42	7	jrydberg	`struct config {`
43	239	markom	`struct {`
44	332	markom	`int enabled; /* Is tick timer enabled? */`
45			`} tick;`
46
47	261	markom	`int nuarts;`
48	239	markom	`struct {`
49	310	markom	`char rxfile[STR_SIZE]; /* Filename for RX */`
50			`char txfile[STR_SIZE]; /* Filename for TX (required) */`
51			`int jitter; /* CZ 250801 - in msecs...time to block */`
52			`unsigned long baseaddr; /* Naturally aligned base address */`
53	332	markom	`int irq; /* IRQ of this device */`
54	313	markom	`unsigned long vapi_id; /* VAPI id for this instance */`
55	341	markom	`int uart16550; /* Whether this device is uart 16450 or 16550 */`
56	424	markom	`} uarts[MAX_UARTS];`
57	239	markom
58	261	markom	`int ndmas;`
59	239	markom	`struct {`
60			`unsigned long baseaddr;`
61	332	markom	`int irq; /* IRQ of this device */`
62	313	markom	`unsigned long vapi_id; /* VAPI id for this instance */`
63	424	markom	`} dmas[MAX_DMAS];`
64	239	markom
65	304	markom	`int nethernets;`
66	361	markom	`struct {`
67			`unsigned long baseaddr;`
68	723	ivang	`int irq; /* IRQ of this device */`
69	361	markom	`unsigned dma; /* Which controller is this ethernet "connected" to */`
70	725	ivang	`unsigned rtx_type; /* use file or socket interface */`
71	361	markom	`unsigned tx_channel; /* DMA channel used for TX */`
72			`unsigned rx_channel; /* DMA channel used for RX */`
73			`char rxfile[STR_SIZE]; /* Filename for RX */`
74			`char txfile[STR_SIZE]; /* File for TX */`
75	723	ivang	`char sockif[STR_SIZE]; /* Socket Interface name ('lo', 'eth1',...) */`
76	889	ivang	`unsigned long base_vapi_id; /* VAPI id for this instance */`
77	424	markom	`} ethernets[MAX_ETHERNETS];`
78	444	erez
79			`int ngpios;`
80	261	markom	`struct {`
81	444	erez	`unsigned long baseaddr; /* Base address */`
82			`int irq; /* IRQ of this device */`
83	477	erez	`unsigned long base_vapi_id; /* First VAPI ID. GPIO uses 8 consecutive IDs */`
84	444	erez	`} gpios[MAX_GPIOS];`
85	645	markom
86			`int nvgas;`
87			`struct {`
88			`unsigned long baseaddr; /* Base address */`
89			`int irq; /* IRQ of this device */`
90			`int refresh_rate; /* Number of clocks per refresh */`
91			`char filename[STR_SIZE]; /* Base file name; suffix of ####.bmp is added */`
92			`} vgas[MAX_VGAS];`
93	444	erez
94			`struct {`
95	645	markom	`int enabled; /* Whether frame buffer is enabled */`
96	647	markom	`unsigned long baseaddr; /* Base address of frame buffer register */`
97	645	markom	`int refresh_rate; /* Number of clocks per refresh */`
98			`char filename[STR_SIZE]; /* Base file name; suffix of ####.bmp is added */`
99			`} fb;`
100	664	markom
101			`struct {`
102			`int enabled; /* Is keyboard enabled? */`
103			`unsigned long baseaddr; /* Base address of frame buffer register */`
104			`int irq; /* Irq number of this device */`
105			`char rxfile[STR_SIZE]; /* Filename for RX */`
106			`} kbd;`
107	645	markom
108			`struct {`
109	261	markom	`int enabled; /* is MC enabled? */`
110			`unsigned long baseaddr; /* Naturally aligned base address */`
111	239	markom	`unsigned POC; /* power on reset configuration register */`
112			`} mc;`
113	645	markom
114	876	rherveille	`int natas;`
115	262	markom	`struct {`
116	876	rherveille	`unsigned long baseaddr; /* Naturally aligned base address */`
117			`int irq; /* Irq number of this device */`
118
119			`int dev_type0; /* ATA-device0 type: 0=none, 1=simulated hd, 2=local system hd */`
120			`char dev_file0[STR_SIZE]; /* Filename for simulating HardDisk (device 0) */`
121			`unsigned long dev_size0; /* Size of simulated harddisk (device 0), in MBytes */`
122			`int dev_packet0; /* Device0 implements PACKET command set */`
123
124			`int dev_type1; /* ATA-device1 type: 0=none, 1=simulated hd, 2=local system hd */`
125			`char dev_file1[STR_SIZE]; /* Filename for simulating HardDisk (device 1) */`
126			`unsigned long dev_size1; /* Size of simulated harddisk (device 1), in MBytes */`
127			`int dev_packet1; /* Device1 implements PACKET command set */`
128			`} atas[MAX_ATAS];`
129
130			`struct {`
131	394	markom	`int pattern; /* A user specified memory initialization pattern */`
132			`int random_seed; /* Initialize the memory with random values, starting with seed */`
133	262	markom	`enum {`
134	269	markom	`MT_UNKNOWN,`
135	262	markom	`MT_PATTERN,`
136			`MT_RANDOM`
137			`} type;`
138	424	markom	`int nmemories; /* Number of attached memories */`
139			`struct {`
140			`int ce; /* Which ce this memory is associated with */`
141			`unsigned long baseaddr; /* Start address of the memory */`
142			`unsigned long size; /* Memory size */`
143			`char name[STR_SIZE]; /* Memory type string */`
144			`char log[STR_SIZE]; /* Memory log filename */`
145			`int delayr; /* Read cycles */`
146			`int delayw; /* Write cycles */`
147			`} table[MAX_MEMORIES];`
148	262	markom	`} memory;`
149	425	markom
150			`struct {`
151			`int enabled; /* Whether IMMU is enabled */`
152			`int nways; /* Number of ITLB ways */`
153			`int nsets; /* Number of ITLB sets */`
154			`int pagesize; /* ITLB page size */`
155			`int entrysize; /* ITLB entry size */`
156			`int ustates; /* number of ITLB usage states */`
157	541	markom	`int missdelay; /* How much cycles does the miss cost */`
158			`int hitdelay; /* How much cycles does the hit cost */`
159	425	markom	`} immu;`
160
161			`struct {`
162			`int enabled; /* Whether DMMU is enabled */`
163			`int nways; /* Number of DTLB ways */`
164			`int nsets; /* Number of DTLB sets */`
165			`int pagesize; /* DTLB page size */`
166			`int entrysize; /* DTLB entry size */`
167			`int ustates; /* number of DTLB usage states */`
168	541	markom	`int missdelay; /* How much cycles does the miss cost */`
169			`int hitdelay; /* How much cycles does the hit cost */`
170	425	markom	`} dmmu;`
171	428	markom
172			`struct {`
173			`int enabled; /* Whether instruction cache is enabled */`
174			`int nways; /* Number of IC ways */`
175			`int nsets; /* Number of IC sets */`
176			`int blocksize; /* IC entry size */`
177			`int ustates; /* number of IC usage states */`
178	541	markom	`int missdelay; /* How much cycles does the miss cost */`
179			`int hitdelay; /* How much cycles does the hit cost */`
180	428	markom	`} ic;`
181	424	markom
182	263	markom	`struct {`
183	541	markom	`int enabled; /* Whether data cache is enabled */`
184	428	markom	`int nways; /* Number of DC ways */`
185			`int nsets; /* Number of DC sets */`
186			`int blocksize; /* DC entry size */`
187			`int ustates; /* number of DC usage states */`
188	541	markom	`int store_missdelay; /* How much cycles does the store miss cost */`
189			`int store_hitdelay; /* How much cycles does the store hit cost */`
190			`int load_missdelay; /* How much cycles does the load miss cost */`
191			`int load_hitdelay; /* How much cycles does the load hit cost */`
192	428	markom	`} dc;`
193
194			`struct {`
195	672	markom	`int enabled; /* branch prediction buffer analysis */`
196			`int sbp_bnf_fwd; /* Static branch prediction for l.bnf uses forward prediction */`
197			`int sbp_bf_fwd; /* Static branch prediction for l.bf uses forward prediction */`
198			`int btic; /* branch prediction target insn cache analysis */`
199			`int missdelay; /* How much cycles does the miss cost */`
200			`int hitdelay; /* How much cycles does the hit cost */`
201			`#if 0`
202			`int nways; /* Number of BP ways */`
203			`int nsets; /* Number of BP sets */`
204			`int blocksize; /* BP entry size */`
205			`int ustates; /* number of BP usage states */`
206			`int pstates; /* number of BP predict states */`
207			`#endif`
208			`} bpb;`
209
210			`struct {`
211			`unsigned long upr; /* Unit present register */`
212			`unsigned long ver, rev; /* Version register */`
213			`int sr; /* Supervision register */`
214			`int superscalar; /* superscalara analysis */`
215			`int hazards; /* dependency hazards analysis */`
216			`int dependstats; /* dependency statistics */`
217			`int sbuf_len; /* length of store buffer, zero if disabled */`
218			`} cpu;`
219
220			`struct {`
221			`int debug; /* Simulator debugging */`
222			`int verbose; /* Force verbose output */`
223
224			`int profile; /* Is profiler running */`
225			`char prof_fn[STR_SIZE]; /* Profiler filename */`
226
227			`int mprofile; /* Is memory profiler running */`
228			`char mprof_fn[STR_SIZE]; /* Memory profiler filename */`
229
230			`int history; /* instruction stream history analysis */`
231			`int exe_log; /* Print out RTL states? */`
232			`int exe_log_type; /* Type of log */`
233			`int exe_log_start; /* First instruction to log */`
234			`int exe_log_end; /* Last instruction to log, -1 if continuous */`
235			`int exe_log_marker; /* If nonzero, place markers before each exe_log_marker instructions */`
236			`char exe_log_fn[STR_SIZE]; /* RTL state comparison filename */`
237			`int spr_log; /* Print out SPR states */`
238			`char spr_log_fn[STR_SIZE]; /* SPR state log filename */`
239	823	ivang	`char fstdout[STR_SIZE]; /* stdout filename */`
240	672	markom	`long clkcycle_ps; /* Clock duration in ps */`
241	805	markom	`long system_kfreq; /* System frequency in kHz*/`
242	672	markom	`} sim;`
243
244			`struct {`
245			`int enabled; /* Whether is debug module enabled */`
246			`int gdb_enabled; /* Whether is debugging with gdb possible */`
247			`int server_port; /* A user specified port number for services */`
248			`unsigned long vapi_id; /* "Fake" vapi device id for JTAG proxy */`
249			`} debug;`
250
251			`struct { /* Verification API, part of Advanced Core Verification */`
252			`int enabled; /* Whether is VAPI module enabled */`
253			`int server_port; /* A user specified port number for services */`
254			`int log_enabled; /* Whether to log the vapi requests */`
255			`int hide_device_id; /* Whether to log device ID for each request */`
256			`char vapi_fn[STR_SIZE]; /* vapi log filename */`
257			`} vapi;`
258
259			`struct {`
260			`int enabled; /* Whether power menagement is operational */`
261			`} pm;`
262	897	markom
263			`struct {`
264			`char timings_fn[STR_SIZE]; /* Filename of the timing table */`
265			`int memory_order; /* Memory access stricness */`
266			`int calling_convention; /* Whether functions follow standard calling convention */`
267			`int enable_bursts; /* Whether burst are enabled */`
268			`int no_multicycle; /* When enabled no multicycle paths are generated */`
269			`} cuc;`
270	672	markom	`};`
271
272			`struct runtime {`
273			`struct {`
274			`FILE fprof; / Profiler file */`
275			`FILE fmprof; / Memory profiler file */`
276			`FILE fexe_log; / RTL state comparison file */`
277			`FILE fspr_log; / SPR state log file */`
278			`int init; /* Whether we are still initilizing sim */`
279			`int script_file_specified; /* Whether script file was already loaded */`
280			`char filename; / Original Command Simulator file (CZ) */`
281			`int output_cfg; /* Whether sim is to output cfg files */`
282			`char script_fn[STR_SIZE]; /* Script file read */`
283			`int iprompt; /* Interactive prompt */`
284	884	markom	`int cont_run; /* Continuos run versus single`
285			`step tracing switch. */`
286			`int cycles; /* Cycles counts fetch stages */`
287
288			`int mem_cycles; /* Each cycle has counter of mem_cycles;`
289			`this value is joined with cycles`
290			`at the end of the cycle; no sim`
291			`originated memory accesses should be`
292			`performed inbetween. */`
293			`int loadcycles; /* Load and store stalls */`
294			`int storecycles;`
295	264	markom	`} sim;`
296	883	markom
297			`/* Command line parameters */`
298			`struct {`
299			`int profile; /* Whether profiling was enabled */`
300			`int mprofile; /* Whether memory profiling was enabled */`
301			`} simcmd;`
302	557	markom
303			`struct {`
304	672	markom	`unsigned long ifea; /* Instruction fetch effective address */`
305			`unsigned long lea; /* Load effective address */`
306			`unsigned long sea; /* Store effective address */`
307			`unsigned long ld; /* Load data */`
308			`unsigned long sd; /* Store data */`
309			`unsigned long lsea; /* Load/Store effective address */`
310	884	markom	`int instructions; /* Instructions executed */`
311			`int stalled;`
312			`int hazardwait; /* how many cycles were wasted because of hazards */`
313			`int supercycles; /* Superscalar cycles */`
314	672	markom	`} cpu;`
315
316			`struct {`
317	551	markom	`int random_seed; /* Initialize the memory with random values, starting with seed */`
318	672	markom	`} memory;`
319
320			`struct { /* Verification API, part of Advanced Core Verification */`
321			`int enabled; /* Whether is VAPI module enabled */`
322			`FILE vapi_file; / vapi file */`
323			`int server_port; /* A user specified port number for services */`
324	293	markom	`} vapi;`
325	897	markom
326			`/* CUC configuration parameters */`
327			`struct {`
328			`int mdelay[4]; /* average memory delays in cycles`
329			`{read single, read burst, write single, write burst} */`
330			`double cycle_duration; /* in ns */`
331			`} cuc;`
332	7	jrydberg	`};`
333	239	markom
334	551	markom	`#if FAST_SIM`
335			`#include "fast_config.c"`
336	557	markom	`#define IFF(x) if (x)`
337	551	markom	`#else`
338	7	jrydberg	`extern struct config config;`
339	557	markom	`#define IFF(x) if (1)`
340	551	markom	`#endif`
341
342	361	markom	`extern struct runtime runtime;`
343	239	markom
344			`/* Read environment from a script file. Does not fail - assumes defaukt configuration instead. */`
345			`void read_script_file (char *filename);`
346	361	markom
347			`/* Executes set sim command. Returns nonzero if error. */`
348			`void set_config_command (char *s);`
349	428	markom
350	549	markom	`/* Outputs C structure of current config to file */`
351			`void output_cfg (FILE *f);`
352
353	428	markom	`#endif`

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