Subversion Repositories or1k

/* dumpverilog.c -- Dumps memory region as Verilog representation

   Copyright (C) 2000 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */

#include <stdio.h>

#include <ctype.h>

#include <string.h>

#include "config.h"

#include "sim-config.h"

#include "parse.h"

#include "abstract.h"

#include "arch.h"

#include "trace.h"

#include "execute.h"

#include "sprs.h"

#include "stats.h"

#include "except.h"

#include "dumpverilog.h"

extern struct mem_entry mem[MEMORY_LEN];

extern char rcsrev[];

void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)

{

        unsigned int i, done = 0;

        struct label_entry *tmp;

        printf("// This file was generated by or1ksim %s\n", rcsrev);

        printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ));

        for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) {

                if (mem[i].insn) {

                        tmp = mem[i].label;

                        for(; tmp; tmp = tmp->next)

                                printf("\n//\t%s%s", tmp->name, LABELEND_CHAR);

                        printf("\n\tmem['h%x] = %d'h%.2x%.2x", i/DWQ, DW, mem[i].data, mem[i+1].data);

                        printf("%.2x%.2x;", mem[i+2].data, mem[i+3].data);

                        if (mem[i].insn)

                                printf("\n\tdis['h%x] = {\"%s\t%s\"", i/DWQ, mem[i].insn->insn, mem[i].insn->op1);

                        if (strlen(mem[i].insn->op2))

                                printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op2);

                        if (strlen(mem[i].insn->op3))

                                printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op3);

                        if (strlen(mem[i].insn->op4))

                                printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op4);

                        printf("};");

                        i += (insn_len(mem[i].insn->insn) - 1);

                } else

                {

                        if (i % 64 == 0)

                                printf("\n");

                        printf("\n\tmem['h%x] = 'h%.2x;", i/DWQ, (unsigned char)mem[i].data);

                }

                done = 1;

        }

        if (done) {

                printf(OR1K_MEM_VERILOG_FOOTER);

                return;

        }

        /* this needs to be fixed */

        for(i = from; i < to; i++) {

                if (i % 8 == 0)

                        printf("\n%.8x:  ", i);

                /* don't print ascii chars below 0x20. */

                if (eval_mem32(i) < 0x20)

                        printf("0x%.2x     ", (unsigned char)eval_mem32(i));

                else

                        printf("0x%.2x'%c'  ", (unsigned char)eval_mem32(i), (unsigned char)eval_mem32(i));

        }

        printf(OR1K_MEM_VERILOG_FOOTER);

}