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[/] [or1k/] [tags/] [nog_patch_53/] [or1ksim/] [testbench/] [cache_asm.S] - Blame information for rev 621

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Line No. Rev Author Line
1 621 simons 
#include "spr_defs.h"
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#define IC_ENABLE 0
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#define DC_ENABLE 0
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        .global _ic_enable
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        .global _ic_disable
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        .global _dc_enable
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        .global _dc_disable
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        .global _dc_inv
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        .global _ic_inv_test
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        .global _dc_inv_test
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_ic_enable:
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        /* Disable IC */
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        l.mfspr r13,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_ICE
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        l.and   r11,r13,r11
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        l.mtspr r0,r11,SPR_SR
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        /* Invalidate IC */
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        l.addi  r13,r0,0
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        l.addi  r11,r0,8192
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1:
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        l.mtspr r0,r13,SPR_ICBIR
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        l.sfne  r13,r11
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        l.bf    1b
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        l.addi  r13,r13,16
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        /* Enable IC */
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        l.mfspr r13,r0,SPR_SR
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        l.ori   r13,r13,SPR_SR_ICE
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        l.mtspr r0,r13,SPR_SR
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.nop
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        l.jr    r9
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        l.nop
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_ic_disable:
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        /* Disable IC */
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        l.mfspr r13,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_ICE
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        l.and   r11,r13,r11
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        l.mtspr r0,r11,SPR_SR
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        l.jr    r9
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        l.nop
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_dc_enable:
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        /* Disable DC */
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        l.mfspr r13,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_DCE
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        l.and   r11,r13,r11
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        l.mtspr r0,r11,SPR_SR
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        /* Flush DC */
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        l.addi  r13,r0,0
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        l.addi  r11,r0,8192
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1:
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        l.mtspr r0,r13,SPR_DCBIR
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        l.sfne  r13,r11
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        l.bf    1b
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        l.addi  r13,r13,16
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        /* Enable DC */
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        l.mfspr r13,r0,SPR_SR
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        l.ori   r13,r13,SPR_SR_DCE
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        l.mtspr r0,r13,SPR_SR
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        l.jr    r9
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        l.nop
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_dc_disable:
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        /* Disable DC */
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        l.mfspr r13,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_DCE
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        l.and   r11,r13,r11
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        l.mtspr r0,r11,SPR_SR
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        l.jr    r9
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        l.nop
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_dc_inv:
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        l.mfspr r4,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r4,r5
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        l.mtspr r0,r5,SPR_SR
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        l.mtspr r0,r3,SPR_DCBIR
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        l.mtspr r0,r4,SPR_SR
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        l.jr    r9
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        l.nop
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        .align  0x10
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_ic_inv_test:
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        l.movhi r7,hi(_ic_test_1)
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        l.ori   r7,r7,lo(_ic_test_1)
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        l.addi  r3,r0,0
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        l.addi  r4,r0,0
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        l.addi  r5,r0,0
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        l.nop
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        l.nop
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        l.nop
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_ic_test_1:
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3:      l.addi  r3,r3,1
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        l.sfeqi r4,0x01
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        l.bnf   1f
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        l.nop
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        l.mfspr r8,r0,SPR_SR
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        l.addi  r11,r0,-1
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        l.xori  r11,r11,SPR_SR_ICE
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        l.and   r11,r8,r11
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        l.mtspr r0,r11,SPR_SR
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        l.mtspr r0,r7,SPR_ICBIR
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        l.mtspr r0,r8,SPR_SR
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        l.bf    2f
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        l.nop
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1:      l.lwz   r6,0(r7)
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        l.addi  r6,r6,1
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        l.sw    0(r7),r6
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2:      l.addi  r5,r5,1
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        l.sfeqi r5,10
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        l.bnf   3b
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        l.xori  r4,r4,0x01
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        l.addi  r11,r3,0
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        l.jr    r9
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        l.nop
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_dc_inv_test:
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        l.movhi r4,hi(0x08040201)
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        l.ori   r4,r4,lo(0x08040201)
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        l.sw    0x00(r3),r4
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        l.slli  r4,r4,1
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        l.sw    0x14(r3),r4
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        l.slli  r4,r4,1
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        l.sw    0x28(r3),r4
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        l.addi  r8,r9,0
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        l.jal   _dc_enable
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        l.nop
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        l.addi  r9,r8,0
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        l.lbz   r4,0x03(r3)
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        l.lhz   r5,0x16(r3)
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        l.add   r4,r4,r5
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        l.lwz   r5,0x28(r3)
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        l.add   r4,r4,r5
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        l.mfspr r6,r0,SPR_SR
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        l.addi  r7,r3,0x10
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        l.mtspr r0,r7,SPR_DCBIR
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        l.lwz   r5,0(r3)
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        l.slli  r5,r5,3
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        l.sw    0x00(r3),r5
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        l.slli  r5,r5,1
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        l.sw    0x14(r3),r5
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        l.slli  r5,r5,1
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        l.sw    0x28(r3),r5
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        l.mtspr r0,r6,SPR_SR
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        l.lbz   r5,0x03(r3)
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        l.add   r4,r4,r5
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        l.lhz   r5,0x16(r3)
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        l.add   r4,r4,r5
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        l.lwz   r5,0x28(r3)
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        l.add   r4,r4,r5
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        l.addi  r5,r0,-1
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        l.xori  r5,r5,SPR_SR_DCE
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        l.and   r5,r6,r5
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        l.mtspr r0,r5,SPR_SR
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        l.addi  r11,r4,0x0
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1:
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        l.jr  r9
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        l.nop

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