OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_54/] [or1ksim/] [tick/] [tick.c] - Blame information for rev 1778

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 91 lampret
/* tick.c -- Simulation of OpenRISC 1000 tick timer
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* This is functional simulation of OpenRISC 1000 architectural
21
   tick timer.
22
*/
23
 
24
#include <stdlib.h>
25
#include <stdio.h>
26
#include <string.h>
27
 
28 1350 nogj
#include "config.h"
29
 
30
#ifdef HAVE_INTTYPES_H
31
#include <inttypes.h>
32
#endif
33
 
34
#include "port.h"
35
#include "arch.h"
36
#include "abstract.h"
37 561 simons
#include "except.h"
38 91 lampret
#include "tick.h"
39 1432 nogj
#include "opcode/or32.h"
40 728 markom
#include "spr_defs.h"
41 1432 nogj
#include "execute.h"
42 102 lampret
#include "pic.h"
43 189 chris
#include "sprs.h"
44 333 markom
#include "sim-config.h"
45 728 markom
#include "sched.h"
46 1408 nogj
#include "debug.h"
47 91 lampret
 
48 1408 nogj
DEFAULT_DEBUG_CHANNEL(tick);
49
 
50 728 markom
/* When did the timer start to count */
51
int cycles_start = 0;
52 133 markom
 
53 728 markom
/* TT Count Register */
54
unsigned long ttcr;
55
 
56
/* TT Mode Register */
57
unsigned long ttmr;
58
 
59 91 lampret
/* Reset. It initializes TTCR register. */
60
void tick_reset()
61
{
62 728 markom
  if (config.sim.verbose)
63 997 markom
    PRINTF("Resetting Tick Timer.\n");
64 728 markom
  mtspr(SPR_TTCR, 0);
65
  mtspr(SPR_TTMR, 0);
66 91 lampret
}
67
 
68 728 markom
/* Job handler for tick timer */
69 1365 nogj
void tick_job (void *param)
70 91 lampret
{
71 728 markom
  int mode = (ttmr & SPR_TTMR_M) >> 30;
72 1408 nogj
  TRACE("tick_job param: %i, mode: %i at %lli (%lli)\n", (int)param, mode,
73
        runtime.sim.cycles, runtime.cpu.instructions);
74 728 markom
  switch (mode) {
75
  case 1:
76 802 simons
    if (!param) {
77 1432 nogj
      cpu_state.sprs[SPR_TTCR] = ttcr = 0;
78 884 markom
      cycles_start = runtime.sim.cycles - ttcr;
79 1408 nogj
      TRACE("Scheduleing timer job for %li\n", (ttmr & SPR_TTMR_PERIOD) - ttcr);
80 1390 nogj
      SCHED_ADD(tick_job, (void *)0, (ttmr & SPR_TTMR_PERIOD) - ttcr);
81 802 simons
    }
82 728 markom
  case 2:
83
    if (ttmr & SPR_TTMR_IE) {
84 133 markom
      setsprbits(SPR_TTMR, SPR_TTMR_IP, 1);
85 1319 phoenix
      /* be sure not to issue timer exception if an exception occured before it */
86 1386 nogj
      if ((mfspr(SPR_SR) & SPR_SR_TEE) == SPR_SR_TEE)
87 728 markom
        except_handle(EXCEPT_TICK, mfspr(SPR_EEAR_BASE));
88 802 simons
      else
89
        /* If TEE is currently not set we have to pend tick exception
90
           by rescheduling. */
91 1390 nogj
        SCHED_ADD(tick_job, (void *)1, 1);
92 728 markom
    }
93
    break;
94
  }
95
}
96 189 chris
 
97 728 markom
/* Starts the tick timer.  This function is called by a write to ttcr spr register */
98 1410 nogj
void spr_write_ttcr (uorreg_t value)
99 728 markom
{
100
  unsigned mode = (ttmr & SPR_TTMR_M) >> 30;
101 1408 nogj
  TRACE("set ttcr = %"PRIxREG"\n", value);
102 728 markom
  ttcr = value;
103
  /* Remove previous if it exists */
104 1408 nogj
  TRACE("Removeing scheduled jobs\n");
105 1365 nogj
  SCHED_FIND_REMOVE(tick_job, (void *)0);
106
  SCHED_FIND_REMOVE(tick_job, (void *)1);
107 728 markom
  if (mode == 1 || mode == 2) {
108 1408 nogj
    TRACE("Scheduleing timer job for %li\n", (ttmr & SPR_TTMR_PERIOD) - ttcr);
109 1390 nogj
    SCHED_ADD(tick_job, (void *)0, (ttmr & SPR_TTMR_PERIOD) - ttcr);
110 884 markom
    cycles_start = runtime.sim.cycles - ttcr;
111 133 markom
  }
112 728 markom
}
113 611 simons
 
114 1410 nogj
void spr_write_ttmr (uorreg_t value)
115 728 markom
{
116 1408 nogj
  TRACE("set ttmr = %"PRIxREG"\n", value);
117 728 markom
  ttmr = value;
118
  /* Handle the modes properly. */
119
  switch((ttmr & SPR_TTMR_M) >> 30) {
120
    case 0:    /* Timer is disabled */
121 1408 nogj
      TRACE("Removeing scheduled jobs\n");
122 1365 nogj
      SCHED_FIND_REMOVE(tick_job, (void *)0);
123
      SCHED_FIND_REMOVE(tick_job, (void *)1);
124 728 markom
      break;
125
    case 1:    /* Timer should auto restart */
126 1432 nogj
      cpu_state.sprs[SPR_TTCR] = ttcr = 0;
127 884 markom
      cycles_start = runtime.sim.cycles;
128 1408 nogj
      TRACE("Removeing scheduled jobs\n");
129 1365 nogj
      SCHED_FIND_REMOVE(tick_job, (void *)0);
130
      SCHED_FIND_REMOVE(tick_job, (void *)1);
131 1408 nogj
      TRACE("Scheduleing timer job for %li\n", (ttmr & SPR_TTMR_PERIOD) - ttcr);
132 1390 nogj
      SCHED_ADD(tick_job, (void *)0, (ttmr & SPR_TTMR_PERIOD) - ttcr);
133 728 markom
      break;
134
    case 2:    /* Stop the timer when match */
135 1408 nogj
      TRACE("Removeing scheduled jobs\n");
136 1365 nogj
      SCHED_FIND_REMOVE(tick_job, (void *)0);
137
      SCHED_FIND_REMOVE(tick_job, (void *)1);
138 728 markom
      break;
139
    case 3:    /* Timer keeps running -- do nothing*/
140
      break;
141
  }
142
}
143 611 simons
 
144 1410 nogj
uorreg_t spr_read_ttcr (void)
145 728 markom
{
146 1408 nogj
  TRACE("read ttcr %lli\n", runtime.sim.cycles - cycles_start);
147 884 markom
  return runtime.sim.cycles - cycles_start;
148 91 lampret
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.