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[/] [or1k/] [tags/] [nog_patch_58/] [or1ksim/] [sim.cfg] - Blame information for rev 263

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section memory
  memory_table_file = "simmem.cfg"
  random_seed = 12345
  type = random
end
 
section cpu
  ver = 0x1200
  rev = 0x0001
  /* upr = */
  superscalar = 0
  hazards = 0
  history = 0
  dependstats = 0
  dependency = 0
  slp = 0
end
 
section mc
  enabled = 1
  baseaddr = 0xa0000000
  POC = 0x00000008                 /* Power on configuration register */
end
 
section uart
  enabled = 1
  nuarts = 1
 
  device 0
    baseaddr = 0x80000000
    rxfile = "/tmp/uart0.rx"
    txfile = "/tmp/uart0.tx"
    jitter = -1                     /* async behaviour */
  enddevice
end
 
section dma
  enabled = 1
  ndmas = 1
 
  device 0
    baseaddr = 0x90000000
    irq = 4
  enddevice
end

Line No.	Rev	Author	Line
1	262	markom	`section memory`
2			`memory_table_file = "simmem.cfg"`
3			`random_seed = 12345`
4			`type = random`
5			`end`
6
7	263	markom	`section cpu`
8			`ver = 0x1200`
9			`rev = 0x0001`
10			`/* upr = */`
11			`superscalar = 0`
12			`hazards = 0`
13			`history = 0`
14			`dependstats = 0`
15			`dependency = 0`
16			`slp = 0`
17			`end`
18
19	243	markom	`section mc`
20	261	markom	`enabled = 1`
21			`baseaddr = 0xa0000000`
22			`POC = 0x00000008 /* Power on configuration register */`
23	243	markom	`end`
24	261	markom
25			`section uart`
26			`enabled = 1`
27			`nuarts = 1`
28
29			`device 0`
30			`baseaddr = 0x80000000`
31			`rxfile = "/tmp/uart0.rx"`
32			`txfile = "/tmp/uart0.tx"`
33			`jitter = -1 /* async behaviour */`
34			`enddevice`
35			`end`
36
37			`section dma`
38			`enabled = 1`
39			`ndmas = 1`
40
41			`device 0`
42			`baseaddr = 0x90000000`
43			`irq = 4`
44			`enddevice`
45			`end`

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[/] [or1k/] [tags/] [nog_patch_58/] [or1ksim/] [sim.cfg] - Blame information for rev 263