OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [mmu/] [dmmu.c] - Blame information for rev 6

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 6 lampret
/* dmmu.c -- data mmu simulation
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
This program is free software; you can redistribute it and/or modify
7
it under the terms of the GNU General Public License as published by
8
the Free Software Foundation; either version 2 of the License, or
9
(at your option) any later version.
10
 
11
This program is distributed in the hope that it will be useful,
12
but WITHOUT ANY WARRANTY; without even the implied warranty of
13
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
GNU General Public License for more details.
15
 
16
You should have received a copy of the GNU General Public License
17
along with this program; if not, write to the Free Software
18
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20
/* DMMU model (not functional yet, currently just copy of data cache). */
21
 
22
 
23
#include "dmmu.h"
24
#include "abstract.h"
25
#include "stats.h"
26
 
27
/* Data MMU */
28
 
29
unsigned long dmmu_translate(unsigned long virtaddr)
30
{
31
        return virtaddr;
32
}
33
 
34
/* Number of DC sets (power of 2) */
35
#define DC_SETS 256
36
 
37
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
38
#define DC_BLOCK_SIZE 4
39
 
40
/* Number of DC ways (1, 2, 3 etc.). */
41
#define DC_WAYS 1
42
 
43
/* Number of usage states (2, 3, 4 etc.). */
44
#define DC_USTATES 2
45
 
46
struct dc_set {
47
        struct {
48
                unsigned long tagaddr;  /* tag address */
49
                int lru;                /* least recently used */
50
        } way[DC_WAYS];
51
} dc[DC_SETS];
52
 
53
void xdc_info()
54
{
55
        printf("Data cache %dKB: ", DC_SETS * DC_BLOCK_SIZE * DC_WAYS / 1024);
56
        printf("%d ways, %d sets, block size %d bytes\n", DC_WAYS, DC_SETS, DC_BLOCK_SIZE);
57
}
58
 
59
/* First check if data is already in the cache and if it is:
60
    - increment DC read hit stats,
61
    - set 'lru' at this way to DC_USTATES - 1 and
62
      decrement 'lru' of other ways unless they have reached 0,
63
   and if not:
64
    - increment DC read miss stats
65
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
66
    - set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
67
      ways unless they have reached 0
68
*/
69
 
70
void xdc_simulate_read(unsigned long dataaddr)
71
{
72
        int set, way = -1;
73
        int i;
74
        unsigned long tagaddr;
75
 
76
        /* Which set to check out? */
77
        set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
78
        tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
79
 
80
        /* Scan all ways and try to find a matching way. */
81
        for (i = 0; i < DC_WAYS; i++)
82
                if (dc[set].way[i].tagaddr == tagaddr)
83
                        way = i;
84
 
85
        /* Did we find our cached data? */
86
        if (way >= 0) { /* Yes, we did. */
87
                dc_stats.readhit++;
88
 
89
                for (i = 0; i < DC_WAYS; i++)
90
                        if (dc[set].way[i].lru)
91
                                dc[set].way[i].lru--;
92
                dc[set].way[way].lru = DC_USTATES - 1;
93
        }
94
        else {  /* No, we didn't. */
95
                int minlru = DC_USTATES - 1;
96
                int minway = 0;
97
 
98
                dc_stats.readmiss++;
99
 
100
                for (i = 0; i < DC_WAYS; i++)
101
                        if (dc[set].way[i].lru < minlru)
102
                                minway = i;
103
 
104
                dc[set].way[minway].tagaddr = tagaddr;
105
                for (i = 0; i < DC_WAYS; i++)
106
                        if (dc[set].way[i].lru)
107
                                dc[set].way[i].lru--;
108
                dc[set].way[minway].lru = DC_USTATES - 1;
109
        }
110
}
111
 
112
/* First check if data is already in the cache and if it is:
113
    - increment DC write hit stats,
114
    - set 'lru' at this way to DC_USTATES - 1 and
115
      decrement 'lru' of other ways unless they have reached 0,
116
   and if not:
117
    - increment DC write miss stats
118
    - find lru way and entry and replace old tag with tag of the 'dataaddr'
119
    - set 'lru' with DC_USTATES - 1 and decrement 'lru' of other
120
      ways unless they have reached 0
121
*/
122
 
123
void xdc_simulate_write(unsigned long dataaddr)
124
{
125
        int set, way = -1;
126
        int i;
127
        unsigned long tagaddr;
128
 
129
        /* Which set to check out? */
130
        set = (dataaddr / DC_BLOCK_SIZE) % DC_SETS;
131
        tagaddr = (dataaddr / DC_BLOCK_SIZE) / DC_SETS;
132
 
133
        /* Scan all ways and try to find a matching way. */
134
        for (i = 0; i < DC_WAYS; i++)
135
                if (dc[set].way[i].tagaddr == tagaddr)
136
                        way = i;
137
 
138
        /* Did we find our cached data? */
139
        if (way >= 0) { /* Yes, we did. */
140
                dc_stats.writehit++;
141
 
142
                for (i = 0; i < DC_WAYS; i++)
143
                        if (dc[set].way[i].lru)
144
                                dc[set].way[i].lru--;
145
                dc[set].way[way].lru = DC_USTATES - 1;
146
        }
147
        else {  /* No, we didn't. */
148
                int minlru = DC_USTATES - 1;
149
                int minway = 0;
150
 
151
                dc_stats.writemiss++;
152
 
153
                for (i = 0; i < DC_WAYS; i++)
154
                        if (dc[set].way[i].lru < minlru)
155
                                minway = i;
156
 
157
                dc[set].way[minway].tagaddr = tagaddr;
158
                for (i = 0; i < DC_WAYS; i++)
159
                        if (dc[set].way[i].lru)
160
                                dc[set].way[i].lru--;
161
                dc[set].way[minway].lru = DC_USTATES - 1;
162
        }
163
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.