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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 702

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 
 
33 
#include "abstract.h"
34 
#include "ethernet_i.h"
35 
#include "dma.h"
36 
#include "sim-config.h"
37 
#include "fields.h"
38 
#include "crc32.h"
39 
 
40 
static struct eth_device eths[MAX_ETHERNETS];
41 
 
42 702 ivang 
/* simulator interface */
43 
static void eth_reset_controller( struct eth_device *eth);
44 696 ivang 
/* register interface */
45 
static void eth_write32( unsigned long addr, unsigned long value );
46 
static unsigned long eth_read32( unsigned long addr );
47 
/* clock */
48 
static void eth_controller_tx_clock( struct eth_device * );
49 
static void eth_controller_rx_clock( struct eth_device * );
50 
/* utility functions */
51 
static int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr );
52 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
53 
static void eth_skip_rx_file( struct eth_device *, off_t );
54 
static void eth_rewind_rx_file( struct eth_device *, off_t );
55 
static void eth_rx_next_packet( struct eth_device * );
56 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
57 696 ivang 
/* ========================================================================= */
58 702 ivang 
/*  TX LOGIC                                                                 */
59 696 ivang 
/*---------------------------------------------------------------------------*/
60 
 
61 
/*
62 
 * TX clock
63 
 * Responsible for starting and finishing TX
64 
 */
65 
void eth_controller_tx_clock( struct eth_device *eth )
66 
{
67 702 ivang 
    int breakpoint = 0;
68 
    int bAdvance   = 1;
69 
    struct sockaddr_ll sll;
70 
 
71 
    long nwritten;
72 
    unsigned long read_word;
73 696 ivang 
 
74 
    switch (eth->tx.state) {
75 702 ivang 
        case ETH_TXSTATE_IDLE:
76 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
77 
 
78 
            /* wait for TxBuffer to be ready */
79 
                debug (3, "TX - entering state WAIT4BD\n");
80 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
81 
        }
82 
        break;
83 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
84 702 ivang 
        /* Read buffer descriptor */
85 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
86 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
87 
 
88 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
89 
            /*****************/
90 
            /* initialize TX */
91 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
92 
            eth->tx.bytes_sent = 0;
93 
 
94 
            /*   Initialize error status bits */
95 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
96 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
97 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
98 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
99 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
100 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
101 
 
102 
            /* Find out minimum length */
103 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
104 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
105 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
106 
            else
107 
                eth->tx.minimum_length = eth->tx.packet_length;
108 
 
109 
            /* Find out maximum length */
110 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
111 
                eth->tx.maximum_length = eth->tx.packet_length;
112 
            else
113 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
114 
 
115 
            /* Do we need CRC on this packet? */
116 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
117 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
118 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
119 
                eth->tx.add_crc = 1;
120 
            else
121 
                eth->tx.add_crc = 0;
122 
 
123 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
124 
                eth->tx.crc_dly = 1;
125 
            else
126 
                eth->tx.crc_dly = 0;
127 
            /* XXX - For now we skip CRC calculation */
128 
 
129 
            debug( 3, "Ethernet: Starting TX of %u bytes (min. %u, max. %u)\n", eth->tx.packet_length,
130 
                   eth->tx.minimum_length, eth->tx.maximum_length );
131 
 
132 
            if (eth->rtx_type == ETH_RTX_FILE) {
133 
                /* write packet length to file */
134 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
135 
            }
136 
 
137 
            /************************************************/
138 
            /* start transmit with reading packet into FIFO */
139 
                debug (3, "TX - entering state READFIFO\n");
140 
            eth->tx.state = ETH_TXSTATE_READFIFO;
141 
        }
142 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
143 
            /* stop TX logic */
144 
                debug (3, "TX - entering state IDLE\n");
145 
            eth->tx.state = ETH_TXSTATE_IDLE;
146 
        }
147 
 
148 
        /* stay in this state if (TXEN && !READY) */
149 
        break;
150 696 ivang 
    case ETH_TXSTATE_READFIFO:
151 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
152 
            read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
153 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
154 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
155 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
156 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
157 
            eth->tx.bytes_sent += 4;
158 
        }
159 
        else {
160 
            debug (3, "TX - entering state TRANSMIT\n");
161 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
162 
        }
163 
        break;
164 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
165 702 ivang 
        /* send packet */
166 
        switch (eth->rtx_type) {
167 
        case ETH_RTX_FILE:
168 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
169 
            break;
170 
        case ETH_RTX_SOCK:
171 
            memset(&sll, 0, sizeof(sll));
172 
                sll.sll_ifindex = eth->ifr.ifr_ifindex;
173 
                nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
174 
                break;
175 
        }
176 
 
177 
        /* set BD status */
178 
        if (nwritten == eth->tx.packet_length) {
179 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
180 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
181 
 
182 
                debug (3, "TX - entering state IDLE\n");
183 
            eth->tx.state = ETH_TXSTATE_IDLE;
184 
            debug (3, "send (%d)bytes OK\n", nwritten);
185 
        }
186 
        else {
187 
            /* XXX - implement retry mechanism here! */
188 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
189 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
190 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
191 
 
192 
                debug (3, "TX - entering state IDLE\n");
193 
            eth->tx.state = ETH_TXSTATE_IDLE;
194 
            debug (3, "send FAILED!\n");
195 
        }
196 
 
197 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
198 
 
199 
        /* advance to next BD */
200 
        if (bAdvance) {
201 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
202 
                            eth->tx.bd_index >= ETH_BD_COUNT )
203 
                eth->tx.bd_index = 0;
204 
            else
205 
                eth->tx.bd_index += 2;
206 
        }
207 
 
208 
        /* generate OK interrupt */
209 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
210 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
211 
        {
212 
            report_interrupt( eth->mac_int );
213 
        }
214 
 
215 
        break;
216 696 ivang 
    }
217 
}
218 
/* ========================================================================= */
219 
 
220 
 
221 
/* ========================================================================= */
222 702 ivang 
/*  RX LOGIC                                                                 */
223 696 ivang 
/*---------------------------------------------------------------------------*/
224 
 
225 
/*
226 
 * RX clock
227 
 * Responsible for starting and finishing RX
228 
 */
229 
void eth_controller_rx_clock( struct eth_device *eth )
230 
{
231 702 ivang 
    int i;
232 
    int breakpoint = 0;
233 
    long nread;
234 
    unsigned long send_word;
235 
 
236 
    fd_set rfds;
237 
 
238 696 ivang 
    switch (eth->rx.state) {
239 
    case ETH_RXSTATE_IDLE:
240 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
241 
                debug (3, "RX - entering state WAIT4BD\n");
242 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
243 
        }
244 
        break;
245 
 
246 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
247 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
248 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
249 
 
250 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
251 
            /*****************/
252 
            /* Initialize RX */
253 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
254 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
255 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
256 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
257 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
258 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
259 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
260 
 
261 
            debug( 3,  "Ethernet: Starting RX\n" );
262 
 
263 
            /* Setup file to read from */
264 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
265 
                eth->rx.fd = eth->txfd;
266 
                eth->rx.offset = &(eth->loopback_offset);
267 
            } else {
268 
                eth->rx.fd = eth->rxfd;
269 
                eth->rx.offset = 0;
270 
            }
271 
                debug (3, "RX - entering state RECV\n");
272 
            eth->rx.state = ETH_RXSTATE_RECV;
273 
        }
274 
        else {
275 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_PEEK);
276 
            if (nread > 0) {
277 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
278 
            }
279 
        }
280 
        break;
281 
 
282 696 ivang 
    case ETH_RXSTATE_RECV:
283 702 ivang 
        switch (eth->rtx_type) {
284 
        case ETH_RTX_FILE:
285 
            /* Read packet length */
286 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
287 
                     < sizeof(eth->rx.packet_length) ) {
288 
                /* TODO: just do what real ethernet would do (some kind of error state) */
289 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX\n" );
290 
                cont_run = 0;
291 
                break;
292 
            }
293 
 
294 
            /* Packet must be big enough to hold a header */
295 
            if ( eth->rx.packet_length < ETH_HLEN ){
296 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
297 
                eth_rx_next_packet( eth );
298 
 
299 
                        debug (3, "RX - entering state IDLE\n");
300 
                eth->rx.state = ETH_RXSTATE_IDLE;
301 
                break;
302 
            }
303 
 
304 
            eth->rx.bytes_read = 0;
305 
            eth->rx.bytes_left = eth->rx.packet_length;
306 
 
307 
            /* for now Read entire packet into memory */
308 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
309 
            if ( nread < eth->rx.bytes_left )
310 
                debug (3, "Read %d from %d. Error!\n", nread, eth->rx.bytes_left);
311 
                eth->rx.error = 1;
312 
            break;
313 
 
314 
        case ETH_RTX_SOCK:
315 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
316 
            if (nread < 0) {
317 
                        if ( errno != EAGAIN ) {
318 
                            debug (3, "recv() FAILED!\n");
319 
                            break;
320 
                        }
321 
                        else {
322 
                        break;
323 
                    }
324 
                }
325 
            eth->rx.bytes_left = nread;
326 
            eth->rx.bytes_read = 0;
327 
 
328 
            debug (3, "RX - entering state WRITEFIFO\n");
329 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
330 
 
331 
            break;
332 
        }
333 
        break;
334 
 
335 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
336 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
337 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
338 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
339 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
340 
        set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
341 
 
342 
        /* update counters */
343 
        debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
344 
        eth->rx.bytes_left -= 4;
345 
        eth->rx.bytes_read += 4;
346 
        if ( eth->rx.bytes_left <= 0 ) {
347 
            /* Write result to bd */
348 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
349 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
350 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXF);
351 
 
352 
            if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
353 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
354 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
355 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
356 
 
357 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
358 
 
359 
            /* advance to next BD */
360 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
361 
                eth->tx.bd_index = eth->regs.tx_bd_num;
362 
            else
363 
                eth->tx.bd_index += 2;
364 
 
365 
            if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXF_M) ) {
366 
                report_interrupt( eth->mac_int );
367 
            }
368 
 
369 
            /* ready to receive next packet */
370 
                debug (3, "RX - entering state IDLE\n");
371 
            eth->rx.state = ETH_RXSTATE_IDLE;
372 
        }
373 
        break;
374 696 ivang 
    }
375 
}
376 702 ivang 
 
377 696 ivang 
/* ========================================================================= */
378 702 ivang 
/* Move to next RX BD */
379 
void eth_rx_next_packet( struct eth_device *eth )
380 
{
381 
    /* Skip any possible leftovers */
382 
    if ( eth->rx.bytes_left )
383 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
384 
}
385 
/* "Skip" bytes in RX file */
386 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
387 
{
388 
    eth->rx.offset += count;
389 
}
390 696 ivang 
 
391 702 ivang 
/* Move RX file position back */
392 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
393 
{
394 
    eth->rx.offset -= count;
395 
}
396 
/*
397 
 * Utility function to read from the ethernet RX file
398 
 * This function moves the file pointer to the current place in the packet before reading
399 
 */
400 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
401 
{
402 
    ssize_t result;
403 
 
404 
    if ( eth->rx.fd <= 0 ) {
405 
        debug( 3,  "Ethernet: No RX file\n" );
406 
        return 0;
407 
    }
408 
 
409 
    if ( eth->rx.offset )
410 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
411 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
412 
            return 0;
413 
        }
414 696 ivang 
 
415 702 ivang 
    result = read( eth->rx.fd, buf, count );
416 
 
417 
    if ( eth->rx.offset && result >= 0 )
418 
        *(eth->rx.offset) += result;
419 
 
420 
    return result;
421 
}
422 
 
423 
/* ========================================================================= */
424 
 
425 696 ivang 
/*
426 702 ivang 
  Reset. Initializes all registers to default and places devices in
427 
         memory address space.
428 696 ivang 
*/
429 
void eth_reset()
430 
{
431 
    static int first_time = 1;
432 
    unsigned i;
433 
 
434 
    if (!config.nethernets)
435 702 ivang 
        return;
436 696 ivang 
 
437 
    if ( first_time ) {
438 702 ivang 
        memset( eths, 0, sizeof(eths) );
439 
        first_time = 0;
440 696 ivang 
    }
441 
 
442 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
443 702 ivang 
        struct eth_device *eth = &(eths[i]);
444 
 
445 
        eth->eth_number = i;
446 
        eth_reset_controller( eth );
447 696 ivang 
    }
448 
}
449 
/* ========================================================================= */
450 
 
451 
 
452 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
453 
{
454 
    int i = eth->eth_number;
455 
    int j;
456 
    struct sockaddr_ll sll;
457 
 
458 
    eth->baseaddr = config.ethernets[i].baseaddr;
459 
 
460 
    if ( eth->baseaddr != 0 ) {
461 
        /* Mark which DMA controller and channels */
462 
        eth->dma        = config.ethernets[i].dma;
463 
        eth->tx_channel = config.ethernets[i].tx_channel;
464 
        eth->rx_channel = config.ethernets[i].rx_channel;
465 
        eth->rtx_type   = ETH_RTX_SOCK/*config.ethernets[i].rtx_type*/;
466 
 
467 
        switch (eth->rtx_type) {
468 
        case ETH_RTX_FILE:
469 
            /* (Re-)open TX/RX files */
470 
            eth->rxfile = config.ethernets[i].rxfile;
471 
            eth->txfile = config.ethernets[i].txfile;
472 
 
473 
            if ( eth->rxfd > 0 )
474 
                close( eth->rxfd );
475 
            if ( eth->txfd > 0 )
476 
                close( eth->txfd );
477 
            eth->rxfd = eth->txfd = -1;
478 
 
479 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
480 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
481 
            if ( (eth->txfd = open( eth->txfile,
482 
                                    O_RDWR | O_CREAT | O_APPEND | O_SYNC,
483 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
484 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
485 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
486 
 
487 
            break;
488 
        case ETH_RTX_SOCK:
489 
            /* (Re-)open TX/RX sockets */
490 
            if (eth->rtx_sock != 0)
491 
                break;
492 
 
493 
            debug (3, "RTX oppening socket...\n");
494 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
495 
            if (eth->rtx_sock == -1) {
496 
                fprintf( stderr, "Cannot open rtx_sock.\n");
497 
                return;
498 
            }
499 
 
500 
            /* get interface index number */
501 
            debug (3, "RTX getting interface...\n");
502 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
503 
            strncpy(eth->ifr.ifr_name, "lo"/*config.ethernets[i].sock_interface*/, IFNAMSIZ);
504 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
505 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
506 
                return;
507 
            }
508 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
509 
 
510 
            /* Bind to interface... */
511 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
512 
            memset(&sll, 0xff, sizeof(sll));
513 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
514 
            sll.sll_protocol = htons(ETH_P_ALL);
515 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
516 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
517 
                fprintf( stderr, "Error bind().\n");
518 
                return;
519 
            }
520 
 
521 
            /* first, flush all received packets. */
522 
            debug (3, "Flush");
523 
            do {
524 
                fd_set fds;
525 
                struct timeval t;
526 
 
527 
                debug( 3, ".");
528 
                FD_ZERO(&fds);
529 
                FD_SET(eth->rtx_sock, &fds);
530 
                memset(&t, 0, sizeof(t));
531 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
532 
                if (j > 0)
533 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
534 
            } while (j);
535 
            debug (3, "\n");
536 
 
537 
            break;
538 
        }
539 
 
540 
        /* Set registers to default values */
541 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
542 
        eth->regs.moder = 0x0000A000;
543 
        eth->regs.ipgt = 0x00000012;
544 
        eth->regs.ipgr1 = 0x0000000C;
545 
        eth->regs.ipgr2 = 0x00000012;
546 
        eth->regs.packetlen = 0x003C0600;
547 
        eth->regs.collconf = 0x000F003F;
548 
        eth->regs.miimoder = 0x00000064;
549 
        eth->regs.tx_bd_num = 0x00000080;
550 
 
551 
        /* Initialize TX/RX status */
552 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
553 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
554 
        eth->rx.bd_index = eth->regs.tx_bd_num;
555 
 
556 
        /* Register memory range */
557 
        register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
558 
    }
559 
}
560 
/* ========================================================================= */
561 
 
562 
 
563 696 ivang 
/*
564 
  Print register values on stdout
565 
*/
566 
void eth_status( void )
567 
{
568 
    unsigned i;
569 
 
570 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
571 702 ivang 
        struct eth_device *eth = &(eths[i]);
572 
 
573 
        if ( eth->baseaddr == 0 )
574 
            continue;
575 
 
576 
        printf( "\nEthernet MAC %u at 0x%08X:\n", i, eth->baseaddr );
577 
        printf( "MODER        : 0x%08lX\n", eth->regs.moder );
578 
        printf( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
579 
        printf( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
580 
        printf( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
581 
        printf( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
582 
        printf( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
583 
        printf( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
584 
        printf( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
585 
        printf( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
586 
        printf( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
587 
        printf( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
588 
        printf( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
589 
        printf( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
590 
        printf( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
591 
        printf( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
592 
        printf( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
593 
        printf( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
594 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
595 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
596 696 ivang 
    }
597 
}
598 
/* ========================================================================= */
599 
 
600 
 
601 
/*
602 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
603 
*/
604 
void eth_clock()
605 
{
606 
    unsigned i;
607 
 
608 
    for ( i = 0; i < config.nethernets; ++ i ) {
609 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
610 
        eth_controller_rx_clock( &(eths[i]) );
611 696 ivang 
    }
612 
}
613 
/* ========================================================================= */
614 
 
615 
 
616 
/*
617 
  Read a register
618 
*/
619 
unsigned long eth_read32( unsigned long addr )
620 
{
621 
    struct eth_device *eth;
622 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
623 
        printf( "eth_read32( 0x%08lX ): Not in registered range(s)\n", addr );
624 
        return 0;
625 696 ivang 
    }
626 
 
627 
    switch( addr ) {
628 
    case ETH_MODER: return eth->regs.moder;
629 
    case ETH_INT_SOURCE: return eth->regs.int_source;
630 
    case ETH_INT_MASK: return eth->regs.int_mask;
631 
    case ETH_IPGT: return eth->regs.ipgt;
632 
    case ETH_IPGR1: return eth->regs.ipgr1;
633 
    case ETH_IPGR2: return eth->regs.ipgr2;
634 
    case ETH_PACKETLEN: return eth->regs.packetlen;
635 
    case ETH_COLLCONF: return eth->regs.collconf;
636 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
637 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
638 
    case ETH_MIIMODER: return eth->regs.miimoder;
639 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
640 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
641 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
642 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
643 
    case ETH_MIISTATUS: return eth->regs.miistatus;
644 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
645 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
646 
                               (((unsigned long)eth->mac_address[1]) << 8) |
647 
                                 (unsigned long)eth->mac_address[0];
648 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
649 702 ivang 
                                 (unsigned long)eth->mac_address[4];
650 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
651 696 ivang 
    }
652 
 
653 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
654 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
655 696 ivang 
 
656 
    printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
657 
    cont_run = 0;
658 
    return 0;
659 
}
660 
/* ========================================================================= */
661 
 
662 
 
663 
/*
664 
  Write a register
665 
*/
666 
void eth_write32( unsigned long addr, unsigned long value )
667 
{
668 
    struct eth_device *eth;
669 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
670 
        printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
671 
    return;
672 696 ivang 
    }
673 
 
674 
    switch( addr ) {
675 
    case ETH_MODER: eth->regs.moder = value; return;
676 
    case ETH_INT_SOURCE: eth->regs.int_source = value; return;
677 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
678 
    case ETH_IPGT: eth->regs.ipgt = value; return;
679 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
680 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
681 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
682 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
683 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
684 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
685 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
686 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
687 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
688 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
689 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
690 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
691 
    case ETH_MAC_ADDR0:
692 702 ivang 
        eth->mac_address[0] = value & 0xFF;
693 
        eth->mac_address[1] = (value >> 8) & 0xFF;
694 
        eth->mac_address[2] = (value >> 16) & 0xFF;
695 
        eth->mac_address[3] = (value >> 24) & 0xFF;
696 
        return;
697 696 ivang 
    case ETH_MAC_ADDR1:
698 702 ivang 
        eth->mac_address[4] = value & 0xFF;
699 
        eth->mac_address[5] = (value >> 8) & 0xFF;
700 
        return;
701 
 
702 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
703 696 ivang 
    }
704 
 
705 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
706 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
707 
        return;
708 696 ivang 
    }
709 
 
710 
    printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
711 
    cont_run = 0;
712 
    return;
713 
}
714 
/* ========================================================================= */
715 
 
716 
 
717 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
718 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
719 
{
720 
    eth->rx.bd_index = eth->regs.tx_bd_num = value & 0xFF;
721 
}
722 
/* ========================================================================= */
723 
 
724 
 
725 696 ivang 
/*
726 
  Convert a memory address to a oontroller struct and relative address.
727 
  Return nonzero on success
728 
*/
729 
int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr )
730 
{
731 
    unsigned i;
732 
    *eth = NULL;
733 
 
734 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
735 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
736 
            *eth = &(eths[i]);
737 
        }
738 696 ivang 
 
739 
    /* verify we found a controller */
740 
    if ( *eth == NULL )
741 702 ivang 
        return 0;
742 696 ivang 
 
743 
    /* Verify legal address */
744 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
745 702 ivang 
        return 0;
746 696 ivang 
 
747 
    *reladdr = addr - (*eth)->baseaddr;
748 
    return 1;
749 
}

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