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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 744

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 
 
33 
#include "abstract.h"
34 
#include "ethernet_i.h"
35 
#include "dma.h"
36 
#include "sim-config.h"
37 
#include "fields.h"
38 
#include "crc32.h"
39 
 
40 
static struct eth_device eths[MAX_ETHERNETS];
41 
 
42 702 ivang 
/* simulator interface */
43 
static void eth_reset_controller( struct eth_device *eth);
44 696 ivang 
/* register interface */
45 
static void eth_write32( unsigned long addr, unsigned long value );
46 
static unsigned long eth_read32( unsigned long addr );
47 
/* clock */
48 
static void eth_controller_tx_clock( struct eth_device * );
49 
static void eth_controller_rx_clock( struct eth_device * );
50 
/* utility functions */
51 
static int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr );
52 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
53 
static void eth_skip_rx_file( struct eth_device *, off_t );
54 
static void eth_rewind_rx_file( struct eth_device *, off_t );
55 
static void eth_rx_next_packet( struct eth_device * );
56 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
57 696 ivang 
/* ========================================================================= */
58 702 ivang 
/*  TX LOGIC                                                                 */
59 696 ivang 
/*---------------------------------------------------------------------------*/
60 
 
61 
/*
62 
 * TX clock
63 
 * Responsible for starting and finishing TX
64 
 */
65 
void eth_controller_tx_clock( struct eth_device *eth )
66 
{
67 702 ivang 
    int breakpoint = 0;
68 
    int bAdvance   = 1;
69 
    struct sockaddr_ll sll;
70 
 
71 
    long nwritten;
72 
    unsigned long read_word;
73 696 ivang 
 
74 
    switch (eth->tx.state) {
75 702 ivang 
        case ETH_TXSTATE_IDLE:
76 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
77 
 
78 
            /* wait for TxBuffer to be ready */
79 705 ivang 
                debug (3, "TX - entering state WAIT4BD (%d)\n", eth->tx.bd_index);
80 702 ivang 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
81 
        }
82 
        break;
83 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
84 702 ivang 
        /* Read buffer descriptor */
85 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
86 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
87 
 
88 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
89 
            /*****************/
90 
            /* initialize TX */
91 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
92 
            eth->tx.bytes_sent = 0;
93 
 
94 
            /*   Initialize error status bits */
95 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
96 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
97 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
98 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
99 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
100 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
101 
 
102 
            /* Find out minimum length */
103 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
104 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
105 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
106 
            else
107 
                eth->tx.minimum_length = eth->tx.packet_length;
108 
 
109 
            /* Find out maximum length */
110 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
111 
                eth->tx.maximum_length = eth->tx.packet_length;
112 
            else
113 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
114 
 
115 
            /* Do we need CRC on this packet? */
116 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
117 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
118 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
119 
                eth->tx.add_crc = 1;
120 
            else
121 
                eth->tx.add_crc = 0;
122 
 
123 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
124 
                eth->tx.crc_dly = 1;
125 
            else
126 
                eth->tx.crc_dly = 0;
127 
            /* XXX - For now we skip CRC calculation */
128 
 
129 
            debug( 3, "Ethernet: Starting TX of %u bytes (min. %u, max. %u)\n", eth->tx.packet_length,
130 
                   eth->tx.minimum_length, eth->tx.maximum_length );
131 
 
132 
            if (eth->rtx_type == ETH_RTX_FILE) {
133 
                /* write packet length to file */
134 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
135 
            }
136 
 
137 
            /************************************************/
138 
            /* start transmit with reading packet into FIFO */
139 
                debug (3, "TX - entering state READFIFO\n");
140 
            eth->tx.state = ETH_TXSTATE_READFIFO;
141 
        }
142 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
143 
            /* stop TX logic */
144 
                debug (3, "TX - entering state IDLE\n");
145 
            eth->tx.state = ETH_TXSTATE_IDLE;
146 
        }
147 
 
148 
        /* stay in this state if (TXEN && !READY) */
149 
        break;
150 696 ivang 
    case ETH_TXSTATE_READFIFO:
151 744 simons 
#if 1
152 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
153 
            read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
154 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
155 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
156 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
157 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
158 
            eth->tx.bytes_sent += 4;
159 
        }
160 744 simons 
#else
161 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
162 
            eth->tx_buff[eth->tx.bytes_sent] = eval_mem8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
163 
            eth->tx.bytes_sent += 1;
164 
        }
165 
#endif
166 702 ivang 
        else {
167 
            debug (3, "TX - entering state TRANSMIT\n");
168 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
169 
        }
170 
        break;
171 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
172 702 ivang 
        /* send packet */
173 
        switch (eth->rtx_type) {
174 
        case ETH_RTX_FILE:
175 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
176 
            break;
177 
        case ETH_RTX_SOCK:
178 
            memset(&sll, 0, sizeof(sll));
179 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
180 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
181 
            break;
182 702 ivang 
        }
183 
 
184 
        /* set BD status */
185 
        if (nwritten == eth->tx.packet_length) {
186 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
187 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
188 
 
189 705 ivang 
            debug (3, "TX - entering state IDLE\n");
190 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
191 
            debug (3, "send (%d)bytes OK\n", nwritten);
192 
        }
193 
        else {
194 
            /* XXX - implement retry mechanism here! */
195 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
196 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
197 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
198 
 
199 
                debug (3, "TX - entering state IDLE\n");
200 
            eth->tx.state = ETH_TXSTATE_IDLE;
201 
            debug (3, "send FAILED!\n");
202 
        }
203 
 
204 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
205 
 
206 
        /* advance to next BD */
207 
        if (bAdvance) {
208 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
209 
                            eth->tx.bd_index >= ETH_BD_COUNT )
210 
                eth->tx.bd_index = 0;
211 
            else
212 
                eth->tx.bd_index += 2;
213 
        }
214 
 
215 
        /* generate OK interrupt */
216 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
217 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
218 
        {
219 
            report_interrupt( eth->mac_int );
220 
        }
221 
 
222 
        break;
223 696 ivang 
    }
224 
}
225 
/* ========================================================================= */
226 
 
227 
 
228 
/* ========================================================================= */
229 702 ivang 
/*  RX LOGIC                                                                 */
230 696 ivang 
/*---------------------------------------------------------------------------*/
231 
 
232 
/*
233 
 * RX clock
234 
 * Responsible for starting and finishing RX
235 
 */
236 
void eth_controller_rx_clock( struct eth_device *eth )
237 
{
238 702 ivang 
    int i;
239 
    int breakpoint = 0;
240 
    long nread;
241 
    unsigned long send_word;
242 
 
243 
    fd_set rfds;
244 
 
245 696 ivang 
    switch (eth->rx.state) {
246 
    case ETH_RXSTATE_IDLE:
247 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
248 705 ivang 
                debug (3, "RX - entering state WAIT4BD (%d)\n", eth->rx.bd_index);
249 702 ivang 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
250 
        }
251 
        break;
252 
 
253 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
254 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
255 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
256 
 
257 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
258 
            /*****************/
259 
            /* Initialize RX */
260 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
261 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
262 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
263 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
264 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
265 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
266 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
267 
 
268 
            debug( 3,  "Ethernet: Starting RX\n" );
269 
 
270 
            /* Setup file to read from */
271 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
272 
                eth->rx.fd = eth->txfd;
273 
                eth->rx.offset = &(eth->loopback_offset);
274 
            } else {
275 
                eth->rx.fd = eth->rxfd;
276 
                eth->rx.offset = 0;
277 
            }
278 
                debug (3, "RX - entering state RECV\n");
279 
            eth->rx.state = ETH_RXSTATE_RECV;
280 
        }
281 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
282 
          debug (3, "RX - entering state IDLE\n");
283 
          eth->rx.state = ETH_RXSTATE_IDLE;
284 
        }
285 
        else {
286 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
287 705 ivang 
            if (nread > 0) {
288 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
289 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
290 
                  report_interrupt(eth->mac_int);
291 702 ivang 
            }
292 
        }
293 
        break;
294 
 
295 696 ivang 
    case ETH_RXSTATE_RECV:
296 702 ivang 
        switch (eth->rtx_type) {
297 
        case ETH_RTX_FILE:
298 
            /* Read packet length */
299 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
300 
                     < sizeof(eth->rx.packet_length) ) {
301 
                /* TODO: just do what real ethernet would do (some kind of error state) */
302 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX\n" );
303 
                cont_run = 0;
304 
                break;
305 
            }
306 
 
307 
            /* Packet must be big enough to hold a header */
308 
            if ( eth->rx.packet_length < ETH_HLEN ){
309 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
310 
                eth_rx_next_packet( eth );
311 
 
312 
                        debug (3, "RX - entering state IDLE\n");
313 
                eth->rx.state = ETH_RXSTATE_IDLE;
314 
                break;
315 
            }
316 
 
317 
            eth->rx.bytes_read = 0;
318 
            eth->rx.bytes_left = eth->rx.packet_length;
319 
 
320 
            /* for now Read entire packet into memory */
321 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
322 
            if ( nread < eth->rx.bytes_left )
323 
                debug (3, "Read %d from %d. Error!\n", nread, eth->rx.bytes_left);
324 
                eth->rx.error = 1;
325 
            break;
326 
 
327 
        case ETH_RTX_SOCK:
328 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
329 744 simons 
 
330 
            if (nread == 0)
331 
                break;
332 
            else if (nread < 0) {
333 
                if ( errno != EAGAIN ) {
334 702 ivang 
                            debug (3, "recv() FAILED!\n");
335 
                            break;
336 
                        }
337 
                        else {
338 
                        break;
339 
                    }
340 744 simons 
            }
341 
            /* If not promiscouos mode, check the destination address */
342 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
343 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
344 
                /* Nothing for now */
345 
                }
346 
 
347 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
348 
                    eth->mac_address[4] != eth->rx_buff[1] ||
349 
                    eth->mac_address[3] != eth->rx_buff[2] ||
350 
                    eth->mac_address[2] != eth->rx_buff[3] ||
351 
                    eth->mac_address[1] != eth->rx_buff[4] ||
352 
                    eth->mac_address[0] != eth->rx_buff[5])
353 
                        break;
354 
            }
355 
 
356 
            eth->rx.packet_length = nread;
357 702 ivang 
            eth->rx.bytes_left = nread;
358 
            eth->rx.bytes_read = 0;
359 
 
360 
            debug (3, "RX - entering state WRITEFIFO\n");
361 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
362 
 
363 
            break;
364 
        }
365 
        break;
366 
 
367 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
368 744 simons 
#if 1
369 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
370 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
371 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
372 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
373 
        set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
374 
        /* update counters */
375 
        debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
376 
        eth->rx.bytes_left -= 4;
377 
        eth->rx.bytes_read += 4;
378 744 simons 
#else
379 
        set_mem8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint);
380 
        eth->rx.bytes_left -= 1;
381 
        eth->rx.bytes_read += 1;
382 
#endif
383 
 
384 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
385 
            /* Write result to bd */
386 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
387 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
388 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
389 702 ivang 
 
390 
            if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
391 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
392 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
393 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
394 
 
395 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
396 
 
397 
            /* advance to next BD */
398 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
399 705 ivang 
                eth->rx.bd_index = eth->regs.tx_bd_num;
400 702 ivang 
            else
401 705 ivang 
                eth->rx.bd_index += 2;
402 702 ivang 
 
403 705 ivang 
            if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXB_M) ) {
404 702 ivang 
                report_interrupt( eth->mac_int );
405 
            }
406 
 
407 
            /* ready to receive next packet */
408 
                debug (3, "RX - entering state IDLE\n");
409 
            eth->rx.state = ETH_RXSTATE_IDLE;
410 
        }
411 
        break;
412 696 ivang 
    }
413 
}
414 702 ivang 
 
415 696 ivang 
/* ========================================================================= */
416 702 ivang 
/* Move to next RX BD */
417 
void eth_rx_next_packet( struct eth_device *eth )
418 
{
419 
    /* Skip any possible leftovers */
420 
    if ( eth->rx.bytes_left )
421 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
422 
}
423 
/* "Skip" bytes in RX file */
424 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
425 
{
426 
    eth->rx.offset += count;
427 
}
428 696 ivang 
 
429 702 ivang 
/* Move RX file position back */
430 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
431 
{
432 
    eth->rx.offset -= count;
433 
}
434 
/*
435 
 * Utility function to read from the ethernet RX file
436 
 * This function moves the file pointer to the current place in the packet before reading
437 
 */
438 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
439 
{
440 
    ssize_t result;
441 
 
442 
    if ( eth->rx.fd <= 0 ) {
443 
        debug( 3,  "Ethernet: No RX file\n" );
444 
        return 0;
445 
    }
446 
 
447 
    if ( eth->rx.offset )
448 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
449 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
450 
            return 0;
451 
        }
452 696 ivang 
 
453 702 ivang 
    result = read( eth->rx.fd, buf, count );
454 
 
455 
    if ( eth->rx.offset && result >= 0 )
456 
        *(eth->rx.offset) += result;
457 
 
458 
    return result;
459 
}
460 
 
461 
/* ========================================================================= */
462 
 
463 696 ivang 
/*
464 702 ivang 
  Reset. Initializes all registers to default and places devices in
465 
         memory address space.
466 696 ivang 
*/
467 
void eth_reset()
468 
{
469 
    static int first_time = 1;
470 
    unsigned i;
471 
 
472 
    if (!config.nethernets)
473 702 ivang 
        return;
474 696 ivang 
 
475 
    if ( first_time ) {
476 702 ivang 
        memset( eths, 0, sizeof(eths) );
477 
        first_time = 0;
478 696 ivang 
    }
479 
 
480 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
481 702 ivang 
        struct eth_device *eth = &(eths[i]);
482 
 
483 
        eth->eth_number = i;
484 
        eth_reset_controller( eth );
485 696 ivang 
    }
486 
}
487 
/* ========================================================================= */
488 
 
489 
 
490 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
491 
{
492 
    int i = eth->eth_number;
493 
    int j;
494 
    struct sockaddr_ll sll;
495 
 
496 
    eth->baseaddr = config.ethernets[i].baseaddr;
497 
 
498 
    if ( eth->baseaddr != 0 ) {
499 
        /* Mark which DMA controller and channels */
500 
        eth->dma        = config.ethernets[i].dma;
501 725 ivang 
        eth->mac_int    = config.ethernets[i].irq;
502 702 ivang 
        eth->tx_channel = config.ethernets[i].tx_channel;
503 
        eth->rx_channel = config.ethernets[i].rx_channel;
504 725 ivang 
        eth->rtx_type   = config.ethernets[i].rtx_type;
505 702 ivang 
 
506 
        switch (eth->rtx_type) {
507 
        case ETH_RTX_FILE:
508 
            /* (Re-)open TX/RX files */
509 
            eth->rxfile = config.ethernets[i].rxfile;
510 
            eth->txfile = config.ethernets[i].txfile;
511 
 
512 
            if ( eth->rxfd > 0 )
513 
                close( eth->rxfd );
514 
            if ( eth->txfd > 0 )
515 
                close( eth->txfd );
516 
            eth->rxfd = eth->txfd = -1;
517 
 
518 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
519 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
520 
            if ( (eth->txfd = open( eth->txfile,
521 
                                    O_RDWR | O_CREAT | O_APPEND | O_SYNC,
522 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
523 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
524 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
525 
 
526 
            break;
527 
        case ETH_RTX_SOCK:
528 
            /* (Re-)open TX/RX sockets */
529 
            if (eth->rtx_sock != 0)
530 
                break;
531 
 
532 
            debug (3, "RTX oppening socket...\n");
533 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
534 
            if (eth->rtx_sock == -1) {
535 
                fprintf( stderr, "Cannot open rtx_sock.\n");
536 
                return;
537 
            }
538 
 
539 
            /* get interface index number */
540 
            debug (3, "RTX getting interface...\n");
541 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
542 725 ivang 
            strncpy(eth->ifr.ifr_name, config.ethernets[i].sockif, IFNAMSIZ);
543 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
544 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
545 
                return;
546 
            }
547 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
548 
 
549 
            /* Bind to interface... */
550 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
551 
            memset(&sll, 0xff, sizeof(sll));
552 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
553 
            sll.sll_protocol = htons(ETH_P_ALL);
554 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
555 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
556 
                fprintf( stderr, "Error bind().\n");
557 
                return;
558 
            }
559 
 
560 
            /* first, flush all received packets. */
561 
            debug (3, "Flush");
562 
            do {
563 
                fd_set fds;
564 
                struct timeval t;
565 
 
566 
                debug( 3, ".");
567 
                FD_ZERO(&fds);
568 
                FD_SET(eth->rtx_sock, &fds);
569 
                memset(&t, 0, sizeof(t));
570 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
571 
                if (j > 0)
572 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
573 
            } while (j);
574 
            debug (3, "\n");
575 
 
576 
            break;
577 
        }
578 
 
579 
        /* Set registers to default values */
580 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
581 
        eth->regs.moder = 0x0000A000;
582 
        eth->regs.ipgt = 0x00000012;
583 
        eth->regs.ipgr1 = 0x0000000C;
584 
        eth->regs.ipgr2 = 0x00000012;
585 
        eth->regs.packetlen = 0x003C0600;
586 
        eth->regs.collconf = 0x000F003F;
587 
        eth->regs.miimoder = 0x00000064;
588 
        eth->regs.tx_bd_num = 0x00000080;
589 
 
590 
        /* Initialize TX/RX status */
591 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
592 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
593 
        eth->rx.bd_index = eth->regs.tx_bd_num;
594 
 
595 
        /* Register memory range */
596 
        register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
597 
    }
598 
}
599 
/* ========================================================================= */
600 
 
601 
 
602 696 ivang 
/*
603 
  Print register values on stdout
604 
*/
605 
void eth_status( void )
606 
{
607 
    unsigned i;
608 
 
609 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
610 702 ivang 
        struct eth_device *eth = &(eths[i]);
611 
 
612 
        if ( eth->baseaddr == 0 )
613 
            continue;
614 
 
615 
        printf( "\nEthernet MAC %u at 0x%08X:\n", i, eth->baseaddr );
616 
        printf( "MODER        : 0x%08lX\n", eth->regs.moder );
617 
        printf( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
618 
        printf( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
619 
        printf( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
620 
        printf( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
621 
        printf( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
622 
        printf( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
623 
        printf( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
624 
        printf( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
625 
        printf( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
626 
        printf( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
627 
        printf( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
628 
        printf( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
629 
        printf( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
630 
        printf( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
631 
        printf( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
632 
        printf( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
633 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
634 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
635 744 simons 
        printf( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
636 
        printf( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
637 696 ivang 
    }
638 
}
639 
/* ========================================================================= */
640 
 
641 
 
642 
/*
643 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
644 
*/
645 
void eth_clock()
646 
{
647 
    unsigned i;
648 
 
649 
    for ( i = 0; i < config.nethernets; ++ i ) {
650 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
651 
        eth_controller_rx_clock( &(eths[i]) );
652 696 ivang 
    }
653 
}
654 
/* ========================================================================= */
655 
 
656 
 
657 
/*
658 
  Read a register
659 
*/
660 
unsigned long eth_read32( unsigned long addr )
661 
{
662 
    struct eth_device *eth;
663 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
664 
        printf( "eth_read32( 0x%08lX ): Not in registered range(s)\n", addr );
665 
        return 0;
666 696 ivang 
    }
667 
 
668 
    switch( addr ) {
669 
    case ETH_MODER: return eth->regs.moder;
670 
    case ETH_INT_SOURCE: return eth->regs.int_source;
671 
    case ETH_INT_MASK: return eth->regs.int_mask;
672 
    case ETH_IPGT: return eth->regs.ipgt;
673 
    case ETH_IPGR1: return eth->regs.ipgr1;
674 
    case ETH_IPGR2: return eth->regs.ipgr2;
675 
    case ETH_PACKETLEN: return eth->regs.packetlen;
676 
    case ETH_COLLCONF: return eth->regs.collconf;
677 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
678 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
679 
    case ETH_MIIMODER: return eth->regs.miimoder;
680 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
681 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
682 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
683 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
684 
    case ETH_MIISTATUS: return eth->regs.miistatus;
685 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
686 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
687 
                               (((unsigned long)eth->mac_address[1]) << 8) |
688 
                                 (unsigned long)eth->mac_address[0];
689 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
690 702 ivang 
                                 (unsigned long)eth->mac_address[4];
691 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
692 
    case ETH_HASH1: return eth->regs.hash1;
693 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
694 696 ivang 
    }
695 
 
696 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
697 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
698 696 ivang 
 
699 
    printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
700 
    cont_run = 0;
701 
    return 0;
702 
}
703 
/* ========================================================================= */
704 
 
705 
 
706 
/*
707 
  Write a register
708 
*/
709 
void eth_write32( unsigned long addr, unsigned long value )
710 
{
711 
    struct eth_device *eth;
712 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
713 
        printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
714 
    return;
715 696 ivang 
    }
716 
 
717 
    switch( addr ) {
718 
    case ETH_MODER: eth->regs.moder = value; return;
719 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
720 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
721 
    case ETH_IPGT: eth->regs.ipgt = value; return;
722 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
723 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
724 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
725 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
726 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
727 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
728 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
729 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
730 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
731 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
732 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
733 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
734 
    case ETH_MAC_ADDR0:
735 702 ivang 
        eth->mac_address[0] = value & 0xFF;
736 
        eth->mac_address[1] = (value >> 8) & 0xFF;
737 
        eth->mac_address[2] = (value >> 16) & 0xFF;
738 
        eth->mac_address[3] = (value >> 24) & 0xFF;
739 
        return;
740 696 ivang 
    case ETH_MAC_ADDR1:
741 702 ivang 
        eth->mac_address[4] = value & 0xFF;
742 
        eth->mac_address[5] = (value >> 8) & 0xFF;
743 
        return;
744 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
745 
    case ETH_HASH1: eth->regs.hash1 = value; return;
746 702 ivang 
 
747 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
748 696 ivang 
    }
749 
 
750 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
751 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
752 
        return;
753 696 ivang 
    }
754 
 
755 
    printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
756 
    cont_run = 0;
757 
    return;
758 
}
759 
/* ========================================================================= */
760 
 
761 
 
762 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
763 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
764 
{
765 
    eth->rx.bd_index = eth->regs.tx_bd_num = value & 0xFF;
766 
}
767 
/* ========================================================================= */
768 
 
769 
 
770 696 ivang 
/*
771 
  Convert a memory address to a oontroller struct and relative address.
772 
  Return nonzero on success
773 
*/
774 
int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr )
775 
{
776 
    unsigned i;
777 
    *eth = NULL;
778 
 
779 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
780 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
781 
            *eth = &(eths[i]);
782 
        }
783 696 ivang 
 
784 
    /* verify we found a controller */
785 
    if ( *eth == NULL )
786 702 ivang 
        return 0;
787 696 ivang 
 
788 
    /* Verify legal address */
789 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
790 702 ivang 
        return 0;
791 696 ivang 
 
792 
    *reladdr = addr - (*eth)->baseaddr;
793 
    return 1;
794 
}

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