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[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [peripheral/] [eth.c] - Blame information for rev 844

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1 696 ivang 
/* ethernet.c -- Simulation of Ethernet MAC
2 
   Copyright (C) 2001 by Erez Volk, erez@opencores.org
3 
                         Ivan Guzvinec, ivang@opencores.org
4 
 
5 
   This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
   This program is free software; you can redistribute it and/or modify
8 
   it under the terms of the GNU General Public License as published by
9 
   the Free Software Foundation; either version 2 of the License, or
10 
   (at your option) any later version.
11 
 
12 
   This program is distributed in the hope that it will be useful,
13 
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
   GNU General Public License for more details.
16 
 
17 
   You should have received a copy of the GNU General Public License
18 
   along with this program; if not, write to the Free Software
19 
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 
*/
21 
 
22 
#include <stdlib.h>
23 
#include <stdio.h>
24 
#include <string.h>
25 
#include <sys/types.h>
26 
#include <sys/stat.h>
27 
#include <fcntl.h>
28 
#include <sys/poll.h>
29 
#include <sys/time.h>
30 
#include <unistd.h>
31 
#include <errno.h>
32 
 
33 
#include "abstract.h"
34 
#include "ethernet_i.h"
35 
#include "dma.h"
36 
#include "sim-config.h"
37 
#include "fields.h"
38 
#include "crc32.h"
39 
 
40 
static struct eth_device eths[MAX_ETHERNETS];
41 
 
42 702 ivang 
/* simulator interface */
43 
static void eth_reset_controller( struct eth_device *eth);
44 696 ivang 
/* register interface */
45 
static void eth_write32( unsigned long addr, unsigned long value );
46 
static unsigned long eth_read32( unsigned long addr );
47 
/* clock */
48 
static void eth_controller_tx_clock( struct eth_device * );
49 
static void eth_controller_rx_clock( struct eth_device * );
50 
/* utility functions */
51 
static int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr );
52 702 ivang 
static ssize_t eth_read_rx_file( struct eth_device *, void *, size_t );
53 
static void eth_skip_rx_file( struct eth_device *, off_t );
54 
static void eth_rewind_rx_file( struct eth_device *, off_t );
55 
static void eth_rx_next_packet( struct eth_device * );
56 
static void eth_write_tx_bd_num( struct eth_device *, unsigned long value );
57 696 ivang 
/* ========================================================================= */
58 702 ivang 
/*  TX LOGIC                                                                 */
59 696 ivang 
/*---------------------------------------------------------------------------*/
60 
 
61 
/*
62 
 * TX clock
63 
 * Responsible for starting and finishing TX
64 
 */
65 
void eth_controller_tx_clock( struct eth_device *eth )
66 
{
67 702 ivang 
    int breakpoint = 0;
68 
    int bAdvance   = 1;
69 
    struct sockaddr_ll sll;
70 
 
71 
    long nwritten;
72 
    unsigned long read_word;
73 696 ivang 
 
74 
    switch (eth->tx.state) {
75 702 ivang 
        case ETH_TXSTATE_IDLE:
76 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
77 
 
78 
            /* wait for TxBuffer to be ready */
79 705 ivang 
                debug (3, "TX - entering state WAIT4BD (%d)\n", eth->tx.bd_index);
80 702 ivang 
            eth->tx.state = ETH_TXSTATE_WAIT4BD;
81 
        }
82 
        break;
83 696 ivang 
    case ETH_TXSTATE_WAIT4BD:
84 702 ivang 
        /* Read buffer descriptor */
85 
        eth->tx.bd = eth->regs.bd_ram[eth->tx.bd_index];
86 
        eth->tx.bd_addr = eth->regs.bd_ram[eth->tx.bd_index + 1];
87 
 
88 
        if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, READY ) ) {
89 
            /*****************/
90 
            /* initialize TX */
91 
            eth->tx.bytes_left = eth->tx.packet_length = GET_FIELD( eth->tx.bd, ETH_TX_BD, LENGTH );
92 
            eth->tx.bytes_sent = 0;
93 
 
94 
            /*   Initialize error status bits */
95 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, DEFER );
96 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, COLLISION );
97 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, RETRANSMIT );
98 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, UNDERRUN );
99 
            CLEAR_FLAG( eth->tx.bd, ETH_TX_BD, NO_CARRIER );
100 
            SET_FIELD ( eth->tx.bd, ETH_TX_BD, RETRY, 0 );
101 
 
102 
            /* Find out minimum length */
103 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, PAD ) ||
104 
                 TEST_FLAG( eth->regs.moder, ETH_MODER, PAD ) )
105 
                eth->tx.minimum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL );
106 
            else
107 
                eth->tx.minimum_length = eth->tx.packet_length;
108 
 
109 
            /* Find out maximum length */
110 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, HUGEN ) )
111 
                eth->tx.maximum_length = eth->tx.packet_length;
112 
            else
113 
                eth->tx.maximum_length = GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL );
114 
 
115 
            /* Do we need CRC on this packet? */
116 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, CRCEN ) ||
117 
                 (TEST_FLAG( eth->tx.bd, ETH_TX_BD, CRC) &&
118 
                  TEST_FLAG( eth->tx.bd, ETH_TX_BD, LAST)) )
119 
                eth->tx.add_crc = 1;
120 
            else
121 
                eth->tx.add_crc = 0;
122 
 
123 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, DLYCRCEN ) )
124 
                eth->tx.crc_dly = 1;
125 
            else
126 
                eth->tx.crc_dly = 0;
127 
            /* XXX - For now we skip CRC calculation */
128 
 
129 
            debug( 3, "Ethernet: Starting TX of %u bytes (min. %u, max. %u)\n", eth->tx.packet_length,
130 
                   eth->tx.minimum_length, eth->tx.maximum_length );
131 
 
132 
            if (eth->rtx_type == ETH_RTX_FILE) {
133 
                /* write packet length to file */
134 
                nwritten = write( eth->txfd, &(eth->tx.packet_length), sizeof(eth->tx.packet_length) );
135 
            }
136 
 
137 
            /************************************************/
138 
            /* start transmit with reading packet into FIFO */
139 
                debug (3, "TX - entering state READFIFO\n");
140 
            eth->tx.state = ETH_TXSTATE_READFIFO;
141 
        }
142 
        else if ( !TEST_FLAG( eth->regs.moder, ETH_MODER, TXEN ) ) {
143 
            /* stop TX logic */
144 
                debug (3, "TX - entering state IDLE\n");
145 
            eth->tx.state = ETH_TXSTATE_IDLE;
146 
        }
147 
 
148 
        /* stay in this state if (TXEN && !READY) */
149 
        break;
150 696 ivang 
    case ETH_TXSTATE_READFIFO:
151 744 simons 
#if 1
152 702 ivang 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
153 
            read_word = eval_mem32(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
154 
            eth->tx_buff[eth->tx.bytes_sent]   = (unsigned char)(read_word >> 24);
155 
            eth->tx_buff[eth->tx.bytes_sent+1] = (unsigned char)(read_word >> 16);
156 
            eth->tx_buff[eth->tx.bytes_sent+2] = (unsigned char)(read_word >> 8);
157 
            eth->tx_buff[eth->tx.bytes_sent+3] = (unsigned char)(read_word);
158 
            eth->tx.bytes_sent += 4;
159 
        }
160 744 simons 
#else
161 
        if ( eth->tx.bytes_sent < eth->tx.packet_length ) {
162 
            eth->tx_buff[eth->tx.bytes_sent] = eval_mem8(eth->tx.bytes_sent + eth->tx.bd_addr, &breakpoint);
163 
            eth->tx.bytes_sent += 1;
164 
        }
165 
#endif
166 702 ivang 
        else {
167 
            debug (3, "TX - entering state TRANSMIT\n");
168 
            eth->tx.state = ETH_TXSTATE_TRANSMIT;
169 
        }
170 
        break;
171 696 ivang 
    case ETH_TXSTATE_TRANSMIT:
172 702 ivang 
        /* send packet */
173 
        switch (eth->rtx_type) {
174 
        case ETH_RTX_FILE:
175 
            nwritten = write( eth->txfd, eth->tx_buff, eth->tx.packet_length );
176 
            break;
177 
        case ETH_RTX_SOCK:
178 
            memset(&sll, 0, sizeof(sll));
179 705 ivang 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
180 
            nwritten = sendto(eth->rtx_sock, eth->tx_buff, eth->tx.packet_length, 0, (struct sockaddr *)&sll, sizeof(sll));
181 
            break;
182 702 ivang 
        }
183 
 
184 
        /* set BD status */
185 
        if (nwritten == eth->tx.packet_length) {
186 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
187 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXB);
188 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
189 702 ivang 
 
190 705 ivang 
            debug (3, "TX - entering state IDLE\n");
191 702 ivang 
            eth->tx.state = ETH_TXSTATE_IDLE;
192 
            debug (3, "send (%d)bytes OK\n", nwritten);
193 
        }
194 
        else {
195 
            /* XXX - implement retry mechanism here! */
196 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, READY);
197 
            CLEAR_FLAG (eth->tx.bd, ETH_TX_BD, COLLISION);
198 
            SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, TXE);
199 
 
200 
                debug (3, "TX - entering state IDLE\n");
201 
            eth->tx.state = ETH_TXSTATE_IDLE;
202 
            debug (3, "send FAILED!\n");
203 
        }
204 
 
205 
        eth->regs.bd_ram[eth->tx.bd_index] = eth->tx.bd;
206 
 
207 
        /* advance to next BD */
208 
        if (bAdvance) {
209 
            if ( TEST_FLAG( eth->tx.bd, ETH_TX_BD, WRAP ) ||
210 
                            eth->tx.bd_index >= ETH_BD_COUNT )
211 
                eth->tx.bd_index = 0;
212 
            else
213 
                eth->tx.bd_index += 2;
214 
        }
215 
 
216 
        /* generate OK interrupt */
217 
        if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXE_M) ||
218 
             TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, TXB_M) )
219 
        {
220 
            report_interrupt( eth->mac_int );
221 
        }
222 
 
223 
        break;
224 696 ivang 
    }
225 
}
226 
/* ========================================================================= */
227 
 
228 
 
229 
/* ========================================================================= */
230 702 ivang 
/*  RX LOGIC                                                                 */
231 696 ivang 
/*---------------------------------------------------------------------------*/
232 
 
233 
/*
234 
 * RX clock
235 
 * Responsible for starting and finishing RX
236 
 */
237 
void eth_controller_rx_clock( struct eth_device *eth )
238 
{
239 702 ivang 
    int i;
240 
    int breakpoint = 0;
241 
    long nread;
242 
    unsigned long send_word;
243 
 
244 
    fd_set rfds;
245 
 
246 696 ivang 
    switch (eth->rx.state) {
247 
    case ETH_RXSTATE_IDLE:
248 702 ivang 
        if ( TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN) ) {
249 705 ivang 
                debug (3, "RX - entering state WAIT4BD (%d)\n", eth->rx.bd_index);
250 702 ivang 
            eth->rx.state = ETH_RXSTATE_WAIT4BD;
251 
        }
252 
        break;
253 
 
254 696 ivang 
    case ETH_RXSTATE_WAIT4BD:
255 702 ivang 
        eth->rx.bd = eth->regs.bd_ram[eth->rx.bd_index];
256 
        eth->rx.bd_addr = eth->regs.bd_ram[eth->rx.bd_index + 1];
257 
 
258 
        if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, READY ) ) {
259 
            /*****************/
260 
            /* Initialize RX */
261 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, MISS );
262 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, INVALID );
263 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, DRIBBLE );
264 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, UVERRUN );
265 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, COLLISION );
266 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG );
267 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT );
268 
 
269 
            debug( 3,  "Ethernet: Starting RX\n" );
270 
 
271 
            /* Setup file to read from */
272 
            if ( TEST_FLAG( eth->regs.moder, ETH_MODER, LOOPBCK ) ) {
273 
                eth->rx.fd = eth->txfd;
274 
                eth->rx.offset = &(eth->loopback_offset);
275 
            } else {
276 
                eth->rx.fd = eth->rxfd;
277 
                eth->rx.offset = 0;
278 
            }
279 
                debug (3, "RX - entering state RECV\n");
280 
            eth->rx.state = ETH_RXSTATE_RECV;
281 
        }
282 705 ivang 
        else if (!TEST_FLAG( eth->regs.moder, ETH_MODER, RXEN)) {
283 
          debug (3, "RX - entering state IDLE\n");
284 
          eth->rx.state = ETH_RXSTATE_IDLE;
285 
        }
286 
        else {
287 744 simons 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, /*MSG_PEEK | */MSG_DONTWAIT);
288 705 ivang 
            if (nread > 0) {
289 702 ivang 
                SET_FLAG (eth->regs.int_source, ETH_INT_SOURCE, BUSY);
290 723 ivang 
                if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, BUSY_M) )
291 
                  report_interrupt(eth->mac_int);
292 702 ivang 
            }
293 
        }
294 
        break;
295 
 
296 696 ivang 
    case ETH_RXSTATE_RECV:
297 702 ivang 
        switch (eth->rtx_type) {
298 
        case ETH_RTX_FILE:
299 
            /* Read packet length */
300 
            if ( eth_read_rx_file( eth, &(eth->rx.packet_length), sizeof(eth->rx.packet_length) )
301 
                     < sizeof(eth->rx.packet_length) ) {
302 
                /* TODO: just do what real ethernet would do (some kind of error state) */
303 836 ivang 
                debug (4, "eth_start_rx(): File does not have a packet ready for RX (len = %d)\n", eth->rx.packet_length );
304 702 ivang 
                cont_run = 0;
305 
                break;
306 
            }
307 
 
308 
            /* Packet must be big enough to hold a header */
309 
            if ( eth->rx.packet_length < ETH_HLEN ){
310 
                debug( 3,  "eth_start_rx(): Packet too small\n" );
311 
                eth_rx_next_packet( eth );
312 
 
313 836 ivang 
                debug (3, "RX - entering state IDLE\n");
314 702 ivang 
                eth->rx.state = ETH_RXSTATE_IDLE;
315 
                break;
316 
            }
317 
 
318 
            eth->rx.bytes_read = 0;
319 
            eth->rx.bytes_left = eth->rx.packet_length;
320 
 
321 
            /* for now Read entire packet into memory */
322 
            nread = eth_read_rx_file( eth, eth->rx_buff, eth->rx.bytes_left );
323 844 ivang 
            if ( nread < eth->rx.bytes_left ) {
324 702 ivang 
                debug (3, "Read %d from %d. Error!\n", nread, eth->rx.bytes_left);
325 844 ivang 
                eth->rx.error = 1;
326 
                break;
327 
            }
328 
 
329 
            eth->rx.packet_length = nread;
330 
            eth->rx.bytes_left = nread;
331 
            eth->rx.bytes_read = 0;
332 
 
333 
            debug (3, "RX - entering state WRITEFIFO\n");
334 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
335 
 
336 702 ivang 
            break;
337 
 
338 
        case ETH_RTX_SOCK:
339 
            nread = recv(eth->rtx_sock, eth->rx_buff, ETH_MAXPL, MSG_DONTWAIT);
340 744 simons 
 
341 
            if (nread == 0)
342 
                break;
343 
            else if (nread < 0) {
344 
                if ( errno != EAGAIN ) {
345 702 ivang 
                            debug (3, "recv() FAILED!\n");
346 
                            break;
347 
                        }
348 
                        else {
349 
                        break;
350 
                    }
351 744 simons 
            }
352 
            /* If not promiscouos mode, check the destination address */
353 
            if (!TEST_FLAG(eth->regs.moder, ETH_MODER, PRO)) {
354 
                if (TEST_FLAG(eth->regs.moder, ETH_MODER, IAM) && (eth->rx_buff[0] & 1)) {
355 
                /* Nothing for now */
356 
                }
357 
 
358 
                if (eth->mac_address[5] != eth->rx_buff[0] ||
359 
                    eth->mac_address[4] != eth->rx_buff[1] ||
360 
                    eth->mac_address[3] != eth->rx_buff[2] ||
361 
                    eth->mac_address[2] != eth->rx_buff[3] ||
362 
                    eth->mac_address[1] != eth->rx_buff[4] ||
363 
                    eth->mac_address[0] != eth->rx_buff[5])
364 
                        break;
365 
            }
366 
 
367 841 simons 
            eth->rx.packet_length = nread;
368 
            eth->rx.bytes_left = nread;
369 
            eth->rx.bytes_read = 0;
370 
 
371 
            debug (3, "RX - entering state WRITEFIFO\n");
372 
            eth->rx.state = ETH_RXSTATE_WRITEFIFO;
373 
 
374 702 ivang 
            break;
375 
        }
376 841 simons 
        break;
377 
 
378 696 ivang 
    case ETH_RXSTATE_WRITEFIFO:
379 744 simons 
#if 1
380 702 ivang 
        send_word = ((unsigned long)eth->rx_buff[eth->rx.bytes_read]   << 24) |
381 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+1] << 16) |
382 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+2] << 8)  |
383 
                    ((unsigned long)eth->rx_buff[eth->rx.bytes_read+3] );
384 
        set_mem32( eth->rx.bd_addr + eth->rx.bytes_read, send_word, &breakpoint);
385 
        /* update counters */
386 
        debug (3, "Write %d, left %d - %08lXd\n", eth->rx.bytes_read, eth->rx.bytes_left, send_word);
387 
        eth->rx.bytes_left -= 4;
388 
        eth->rx.bytes_read += 4;
389 744 simons 
#else
390 
        set_mem8( eth->rx.bd_addr + eth->rx.bytes_read, eth->rx_buff[eth->rx.bytes_read], &breakpoint);
391 
        eth->rx.bytes_left -= 1;
392 
        eth->rx.bytes_read += 1;
393 
#endif
394 
 
395 702 ivang 
        if ( eth->rx.bytes_left <= 0 ) {
396 
            /* Write result to bd */
397 
            SET_FIELD( eth->rx.bd, ETH_RX_BD, LENGTH, eth->rx.packet_length );
398 
            CLEAR_FLAG( eth->rx.bd, ETH_RX_BD, READY);
399 705 ivang 
            SET_FLAG( eth->regs.int_source, ETH_INT_SOURCE, RXB);
400 836 ivang 
            debug (4, "ETH_INT_SOURCE = %0x\n", eth->regs.int_source);
401 702 ivang 
 
402 
            if ( eth->rx.packet_length < GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MINFL ) )
403 744 simons 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOSHORT);
404 
            if ( eth->rx.packet_length > GET_FIELD( eth->regs.packetlen, ETH_PACKETLEN, MAXFL ) )
405 702 ivang 
                SET_FLAG( eth->rx.bd, ETH_RX_BD, TOOBIG);
406 
 
407 
            eth->regs.bd_ram[eth->rx.bd_index] = eth->rx.bd;
408 
 
409 
            /* advance to next BD */
410 
            if ( TEST_FLAG( eth->rx.bd, ETH_RX_BD, WRAP ) || eth->rx.bd_index >= ETH_BD_COUNT )
411 705 ivang 
                eth->rx.bd_index = eth->regs.tx_bd_num;
412 702 ivang 
            else
413 705 ivang 
                eth->rx.bd_index += 2;
414 702 ivang 
 
415 705 ivang 
            if ( TEST_FLAG(eth->regs.int_mask, ETH_INT_MASK, RXB_M) ) {
416 702 ivang 
                report_interrupt( eth->mac_int );
417 
            }
418 
 
419 
            /* ready to receive next packet */
420 
                debug (3, "RX - entering state IDLE\n");
421 
            eth->rx.state = ETH_RXSTATE_IDLE;
422 
        }
423 
        break;
424 696 ivang 
    }
425 
}
426 702 ivang 
 
427 696 ivang 
/* ========================================================================= */
428 702 ivang 
/* Move to next RX BD */
429 
void eth_rx_next_packet( struct eth_device *eth )
430 
{
431 
    /* Skip any possible leftovers */
432 
    if ( eth->rx.bytes_left )
433 
        eth_skip_rx_file( eth, eth->rx.bytes_left );
434 
}
435 
/* "Skip" bytes in RX file */
436 
void eth_skip_rx_file( struct eth_device *eth, off_t count )
437 
{
438 
    eth->rx.offset += count;
439 
}
440 696 ivang 
 
441 702 ivang 
/* Move RX file position back */
442 
void eth_rewind_rx_file( struct eth_device *eth, off_t count )
443 
{
444 
    eth->rx.offset -= count;
445 
}
446 
/*
447 
 * Utility function to read from the ethernet RX file
448 
 * This function moves the file pointer to the current place in the packet before reading
449 
 */
450 
ssize_t eth_read_rx_file( struct eth_device *eth, void *buf, size_t count )
451 
{
452 
    ssize_t result;
453 
 
454 
    if ( eth->rx.fd <= 0 ) {
455 
        debug( 3,  "Ethernet: No RX file\n" );
456 
        return 0;
457 
    }
458 
 
459 
    if ( eth->rx.offset )
460 
        if ( lseek( eth->rx.fd, *(eth->rx.offset), SEEK_SET ) == (off_t)-1 ) {
461 
            debug( 3,  "Ethernet: Error seeking RX file\n" );
462 
            return 0;
463 
        }
464 696 ivang 
 
465 702 ivang 
    result = read( eth->rx.fd, buf, count );
466 836 ivang 
    debug (4, "Ethernet: read result = %d \n", result);
467 702 ivang 
    if ( eth->rx.offset && result >= 0 )
468 
        *(eth->rx.offset) += result;
469 
 
470 
    return result;
471 
}
472 
 
473 
/* ========================================================================= */
474 
 
475 696 ivang 
/*
476 702 ivang 
  Reset. Initializes all registers to default and places devices in
477 
         memory address space.
478 696 ivang 
*/
479 
void eth_reset()
480 
{
481 
    static int first_time = 1;
482 
    unsigned i;
483 
 
484 
    if (!config.nethernets)
485 702 ivang 
        return;
486 696 ivang 
 
487 841 simons 
    if ( first_time )
488 702 ivang 
        memset( eths, 0, sizeof(eths) );
489 696 ivang 
 
490 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
491 702 ivang 
        struct eth_device *eth = &(eths[i]);
492 
 
493 
        eth->eth_number = i;
494 
        eth_reset_controller( eth );
495 841 simons 
        if ( eth->baseaddr && first_time )
496 
            register_memoryarea( eth->baseaddr, ETH_ADDR_SPACE, 4, eth_read32, eth_write32 );
497 696 ivang 
    }
498 841 simons 
 
499 
    if ( first_time )
500 
        first_time = 0;
501 696 ivang 
}
502 841 simons 
 
503 696 ivang 
/* ========================================================================= */
504 
 
505 
 
506 702 ivang 
static void eth_reset_controller(struct eth_device *eth)
507 
{
508 
    int i = eth->eth_number;
509 
    int j;
510 
    struct sockaddr_ll sll;
511 
 
512 
    eth->baseaddr = config.ethernets[i].baseaddr;
513 
 
514 
    if ( eth->baseaddr != 0 ) {
515 
        /* Mark which DMA controller and channels */
516 
        eth->dma        = config.ethernets[i].dma;
517 725 ivang 
        eth->mac_int    = config.ethernets[i].irq;
518 702 ivang 
        eth->tx_channel = config.ethernets[i].tx_channel;
519 
        eth->rx_channel = config.ethernets[i].rx_channel;
520 725 ivang 
        eth->rtx_type   = config.ethernets[i].rtx_type;
521 702 ivang 
 
522 
        switch (eth->rtx_type) {
523 
        case ETH_RTX_FILE:
524 
            /* (Re-)open TX/RX files */
525 
            eth->rxfile = config.ethernets[i].rxfile;
526 
            eth->txfile = config.ethernets[i].txfile;
527 
 
528 
            if ( eth->rxfd > 0 )
529 
                close( eth->rxfd );
530 
            if ( eth->txfd > 0 )
531 
                close( eth->txfd );
532 
            eth->rxfd = eth->txfd = -1;
533 
 
534 
            if ( (eth->rxfd = open( eth->rxfile, O_RDONLY )) < 0 )
535 
                fprintf( stderr, "Cannot open Ethernet RX file \"%s\"\n", eth->rxfile );
536 
            if ( (eth->txfd = open( eth->txfile,
537 
                                    O_RDWR | O_CREAT | O_APPEND | O_SYNC,
538 
                                    S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH )) < 0 )
539 
                fprintf( stderr, "Cannot open Ethernet TX file \"%s\"\n", eth->txfile );
540 
            eth->loopback_offset = lseek( eth->txfd, 0, SEEK_END );
541 
 
542 
            break;
543 
        case ETH_RTX_SOCK:
544 
            /* (Re-)open TX/RX sockets */
545 
            if (eth->rtx_sock != 0)
546 
                break;
547 
 
548 
            debug (3, "RTX oppening socket...\n");
549 
            eth->rtx_sock = socket(PF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
550 
            if (eth->rtx_sock == -1) {
551 
                fprintf( stderr, "Cannot open rtx_sock.\n");
552 
                return;
553 
            }
554 
 
555 
            /* get interface index number */
556 
            debug (3, "RTX getting interface...\n");
557 
            memset(&(eth->ifr), 0, sizeof(eth->ifr));
558 725 ivang 
            strncpy(eth->ifr.ifr_name, config.ethernets[i].sockif, IFNAMSIZ);
559 702 ivang 
            if (ioctl(eth->rtx_sock, SIOCGIFINDEX, &(eth->ifr)) == -1) {
560 
                fprintf( stderr, "SIOCGIFINDEX failed!\n");
561 
                return;
562 
            }
563 
            debug (3, "RTX Socket Interface : %d\n", eth->ifr.ifr_ifindex);
564 
 
565 
            /* Bind to interface... */
566 
            debug (3, "Binding to the interface ifindex=%d\n", eth->ifr.ifr_ifindex);
567 
            memset(&sll, 0xff, sizeof(sll));
568 
            sll.sll_family = AF_PACKET;    /* allways AF_PACKET */
569 
            sll.sll_protocol = htons(ETH_P_ALL);
570 
            sll.sll_ifindex = eth->ifr.ifr_ifindex;
571 
            if (bind(eth->rtx_sock, (struct sockaddr *)&sll, sizeof(sll)) == -1) {
572 
                fprintf( stderr, "Error bind().\n");
573 
                return;
574 
            }
575 
 
576 
            /* first, flush all received packets. */
577 
            debug (3, "Flush");
578 
            do {
579 
                fd_set fds;
580 
                struct timeval t;
581 
 
582 
                debug( 3, ".");
583 
                FD_ZERO(&fds);
584 
                FD_SET(eth->rtx_sock, &fds);
585 
                memset(&t, 0, sizeof(t));
586 
                j = select(FD_SETSIZE, &fds, NULL, NULL, &t);
587 
                if (j > 0)
588 
                    recv(eth->rtx_sock, eth->rx_buff, j, 0);
589 
            } while (j);
590 
            debug (3, "\n");
591 
 
592 
            break;
593 
        }
594 
 
595 
        /* Set registers to default values */
596 
        memset( &(eth->regs), 0, sizeof(eth->regs) );
597 
        eth->regs.moder = 0x0000A000;
598 
        eth->regs.ipgt = 0x00000012;
599 
        eth->regs.ipgr1 = 0x0000000C;
600 
        eth->regs.ipgr2 = 0x00000012;
601 
        eth->regs.packetlen = 0x003C0600;
602 
        eth->regs.collconf = 0x000F003F;
603 
        eth->regs.miimoder = 0x00000064;
604 
        eth->regs.tx_bd_num = 0x00000080;
605 
 
606 
        /* Initialize TX/RX status */
607 
        memset( &(eth->tx), 0, sizeof(eth->tx) );
608 
        memset( &(eth->rx), 0, sizeof(eth->rx) );
609 
        eth->rx.bd_index = eth->regs.tx_bd_num;
610 
    }
611 
}
612 
/* ========================================================================= */
613 
 
614 
 
615 696 ivang 
/*
616 
  Print register values on stdout
617 
*/
618 
void eth_status( void )
619 
{
620 
    unsigned i;
621 
 
622 
    for ( i = 0; i < MAX_ETHERNETS; ++ i ) {
623 702 ivang 
        struct eth_device *eth = &(eths[i]);
624 
 
625 
        if ( eth->baseaddr == 0 )
626 
            continue;
627 
 
628 
        printf( "\nEthernet MAC %u at 0x%08X:\n", i, eth->baseaddr );
629 
        printf( "MODER        : 0x%08lX\n", eth->regs.moder );
630 
        printf( "INT_SOURCE   : 0x%08lX\n", eth->regs.int_source );
631 
        printf( "INT_MASK     : 0x%08lX\n", eth->regs.int_mask );
632 
        printf( "IPGT         : 0x%08lX\n", eth->regs.ipgt );
633 
        printf( "IPGR1        : 0x%08lX\n", eth->regs.ipgr1 );
634 
        printf( "IPGR2        : 0x%08lX\n", eth->regs.ipgr2 );
635 
        printf( "PACKETLEN    : 0x%08lX\n", eth->regs.packetlen );
636 
        printf( "COLLCONF     : 0x%08lX\n", eth->regs.collconf );
637 
        printf( "TX_BD_NUM    : 0x%08lX\n", eth->regs.tx_bd_num );
638 
        printf( "CTRLMODER    : 0x%08lX\n", eth->regs.controlmoder );
639 
        printf( "MIIMODER     : 0x%08lX\n", eth->regs.miimoder );
640 
        printf( "MIICOMMAND   : 0x%08lX\n", eth->regs.miicommand );
641 
        printf( "MIIADDRESS   : 0x%08lX\n", eth->regs.miiaddress );
642 
        printf( "MIITX_DATA   : 0x%08lX\n", eth->regs.miitx_data );
643 
        printf( "MIIRX_DATA   : 0x%08lX\n", eth->regs.miirx_data );
644 
        printf( "MIISTATUS    : 0x%08lX\n", eth->regs.miistatus );
645 
        printf( "MAC Address  : %02X:%02X:%02X:%02X:%02X:%02X\n",
646 
                eth->mac_address[0], eth->mac_address[1], eth->mac_address[2],
647 
                eth->mac_address[3], eth->mac_address[4], eth->mac_address[5] );
648 744 simons 
        printf( "HASH0        : 0x%08lX\n", eth->regs.hash0 );
649 
        printf( "HASH1        : 0x%08lX\n", eth->regs.hash1 );
650 696 ivang 
    }
651 
}
652 
/* ========================================================================= */
653 
 
654 
 
655 
/*
656 
  Simulation hook. Must be called every clock cycle to simulate Ethernet MAC.
657 
*/
658 
void eth_clock()
659 
{
660 
    unsigned i;
661 
 
662 
    for ( i = 0; i < config.nethernets; ++ i ) {
663 702 ivang 
        eth_controller_tx_clock( &(eths[i]) );
664 
        eth_controller_rx_clock( &(eths[i]) );
665 696 ivang 
    }
666 
}
667 
/* ========================================================================= */
668 
 
669 
 
670 
/*
671 
  Read a register
672 
*/
673 
unsigned long eth_read32( unsigned long addr )
674 
{
675 
    struct eth_device *eth;
676 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
677 
        printf( "eth_read32( 0x%08lX ): Not in registered range(s)\n", addr );
678 
        return 0;
679 696 ivang 
    }
680 
 
681 
    switch( addr ) {
682 
    case ETH_MODER: return eth->regs.moder;
683 
    case ETH_INT_SOURCE: return eth->regs.int_source;
684 
    case ETH_INT_MASK: return eth->regs.int_mask;
685 
    case ETH_IPGT: return eth->regs.ipgt;
686 
    case ETH_IPGR1: return eth->regs.ipgr1;
687 
    case ETH_IPGR2: return eth->regs.ipgr2;
688 
    case ETH_PACKETLEN: return eth->regs.packetlen;
689 
    case ETH_COLLCONF: return eth->regs.collconf;
690 
    case ETH_TX_BD_NUM: return eth->regs.tx_bd_num;
691 
    case ETH_CTRLMODER: return eth->regs.controlmoder;
692 
    case ETH_MIIMODER: return eth->regs.miimoder;
693 
    case ETH_MIICOMMAND: return eth->regs.miicommand;
694 
    case ETH_MIIADDRESS: return eth->regs.miiaddress;
695 
    case ETH_MIITX_DATA: return eth->regs.miitx_data;
696 
    case ETH_MIIRX_DATA: return eth->regs.miirx_data;
697 
    case ETH_MIISTATUS: return eth->regs.miistatus;
698 
    case ETH_MAC_ADDR0: return (((unsigned long)eth->mac_address[3]) << 24) |
699 702 ivang 
                               (((unsigned long)eth->mac_address[2]) << 16) |
700 
                               (((unsigned long)eth->mac_address[1]) << 8) |
701 
                                 (unsigned long)eth->mac_address[0];
702 696 ivang 
    case ETH_MAC_ADDR1: return (((unsigned long)eth->mac_address[5]) << 8) |
703 702 ivang 
                                 (unsigned long)eth->mac_address[4];
704 744 simons 
    case ETH_HASH0: return eth->regs.hash0;
705 
    case ETH_HASH1: return eth->regs.hash1;
706 702 ivang 
    /*case ETH_DMA_RX_TX: return eth_rx( eth );*/
707 696 ivang 
    }
708 
 
709 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) )
710 702 ivang 
        return eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4];
711 696 ivang 
 
712 
    printf( "eth_read32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
713 
    cont_run = 0;
714 
    return 0;
715 
}
716 
/* ========================================================================= */
717 
 
718 
 
719 
/*
720 
  Write a register
721 
*/
722 
void eth_write32( unsigned long addr, unsigned long value )
723 
{
724 
    struct eth_device *eth;
725 702 ivang 
    if ( !eth_find_controller( addr, &eth, &addr ) )    {
726 
        printf( "eth_write32( 0x%08lX ): Not in registered range(s)\n", addr );
727 
    return;
728 696 ivang 
    }
729 
 
730 
    switch( addr ) {
731 841 simons 
    case ETH_MODER: eth->regs.moder = value; if (TEST_FLAG(value, ETH_MODER, RST)) eth_reset(); return;
732 744 simons 
    case ETH_INT_SOURCE: eth->regs.int_source &= ~value; return;
733 696 ivang 
    case ETH_INT_MASK: eth->regs.int_mask = value; return;
734 
    case ETH_IPGT: eth->regs.ipgt = value; return;
735 
    case ETH_IPGR1: eth->regs.ipgr1 = value; return;
736 
    case ETH_IPGR2: eth->regs.ipgr2 = value; return;
737 
    case ETH_PACKETLEN: eth->regs.packetlen = value; return;
738 
    case ETH_COLLCONF: eth->regs.collconf = value; return;
739 
    case ETH_TX_BD_NUM: eth_write_tx_bd_num( eth, value ); return;
740 
    case ETH_CTRLMODER: eth->regs.controlmoder = value; return;
741 
    case ETH_MIIMODER: eth->regs.miimoder = value; return;
742 
    case ETH_MIICOMMAND: eth->regs.miicommand = value; return;
743 
    case ETH_MIIADDRESS: eth->regs.miiaddress = value; return;
744 
    case ETH_MIITX_DATA: eth->regs.miitx_data = value; return;
745 
    case ETH_MIIRX_DATA: eth->regs.miirx_data = value; return;
746 
    case ETH_MIISTATUS: eth->regs.miistatus = value; return;
747 
    case ETH_MAC_ADDR0:
748 702 ivang 
        eth->mac_address[0] = value & 0xFF;
749 
        eth->mac_address[1] = (value >> 8) & 0xFF;
750 
        eth->mac_address[2] = (value >> 16) & 0xFF;
751 
        eth->mac_address[3] = (value >> 24) & 0xFF;
752 
        return;
753 696 ivang 
    case ETH_MAC_ADDR1:
754 702 ivang 
        eth->mac_address[4] = value & 0xFF;
755 
        eth->mac_address[5] = (value >> 8) & 0xFF;
756 
        return;
757 744 simons 
    case ETH_HASH0: eth->regs.hash0 = value; return;
758 
    case ETH_HASH1: eth->regs.hash1 = value; return;
759 702 ivang 
 
760 
    /*case ETH_DMA_RX_TX: eth_tx( eth, value ); return;*/
761 696 ivang 
    }
762 
 
763 
    if ( (addr >= ETH_BD_BASE) && (addr < ETH_BD_BASE + ETH_BD_SPACE) ) {
764 702 ivang 
        eth->regs.bd_ram[(addr - ETH_BD_BASE) / 4] = value;
765 
        return;
766 696 ivang 
    }
767 
 
768 
    printf( "eth_write32( 0x%08lX ): Illegal address\n", addr + eth->baseaddr );
769 
    cont_run = 0;
770 
    return;
771 
}
772 
/* ========================================================================= */
773 
 
774 
 
775 702 ivang 
/* When TX_BD_NUM is written, also reset current RX BD index */
776 
void eth_write_tx_bd_num( struct eth_device *eth, unsigned long value )
777 
{
778 
    eth->rx.bd_index = eth->regs.tx_bd_num = value & 0xFF;
779 
}
780 
/* ========================================================================= */
781 
 
782 
 
783 696 ivang 
/*
784 
  Convert a memory address to a oontroller struct and relative address.
785 
  Return nonzero on success
786 
*/
787 
int eth_find_controller( unsigned long addr, struct eth_device **eth, unsigned long *reladdr )
788 
{
789 
    unsigned i;
790 
    *eth = NULL;
791 
 
792 
    for ( i = 0; i < MAX_ETHERNETS && *eth == NULL; ++ i ) {
793 702 ivang 
        if ( (addr >= eths[i].baseaddr) && (addr < eths[i].baseaddr + ETH_ADDR_SPACE) )
794 
            *eth = &(eths[i]);
795 
        }
796 696 ivang 
 
797 
    /* verify we found a controller */
798 
    if ( *eth == NULL )
799 702 ivang 
        return 0;
800 696 ivang 
 
801 
    /* Verify legal address */
802 
    if ( (addr - (*eth)->baseaddr) % 4 != 0 )
803 702 ivang 
        return 0;
804 696 ivang 
 
805 
    *reladdr = addr - (*eth)->baseaddr;
806 
    return 1;
807 
}

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