OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_61/] [or1ksim/] [sim-config.h] - Blame information for rev 242

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 7 jrydberg
/* config.h -- Simulator configuration header file
2
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
3
 
4
   This file is part of OpenRISC 1000 Architectural Simulator.
5
 
6
   This program is free software; you can redistribute it and/or modify
7
   it under the terms of the GNU General Public License as published by
8
   the Free Software Foundation; either version 2 of the License, or
9
   (at your option) any later version.
10
 
11
   This program is distributed in the hope that it will be useful,
12
   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
   GNU General Public License for more details.
15
 
16
   You should have received a copy of the GNU General Public License
17
   along with this program; if not, write to the Free Software
18
   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19
 
20 173 markom
#include <stdio.h>
21
 
22 7 jrydberg
/* Simulator configuration macros. Eventually this one will be a lot bigger. */
23 30 lampret
 
24 221 markom
#define NR_UARTS        4       /* Number of UARTs simulated */   
25 212 erez
#define NR_DMAS         1       /* Number of DMA controllers */
26 239 markom
#define NONE            0
27
#define VIRTUAL         1
28
#define PHYSICAL        2
29 7 jrydberg
 
30 239 markom
#define STR_SIZE        (256)
31
 
32 7 jrydberg
struct config {
33 239 markom
  struct {
34
    int tagtype;
35
  } dc;
36
 
37
  struct {
38
    int tagtype;
39
  } ic;
40
 
41
  struct {
42
    int bpb_sim;
43
    int btic_sim;
44
  } bp;     /* Branch prediction */
45
  int clkcycle_ns;  /* Clock cycle in nanoseconds */
46
 
47
  struct {
48
    char *rxfile; /* File for RX */
49
    char *txfile; /* File for TX (required) */
50
          int jitter;     /* CZ 250801 - in msecs...time to block */
51
    unsigned long baseaddr; /* Naturally aligned base address */
52
  } uarts[NR_UARTS];
53
 
54
  struct {
55
    unsigned long baseaddr;
56
    unsigned irq;
57
  } dmas[NR_DMAS];
58
 
59
  struct {
60
    char memory_table_file[STR_SIZE]; /* Memory table filename */
61 240 markom
    int enable;                      /* is MC enabled? */
62 239 markom
    unsigned POC;                     /* power on reset configuration register */
63
  } mc;
64
 
65
  int simdebug; /* Simulator debugging */
66 221 markom
  int profile;    /* Is profiler running */
67
  FILE *fprof;    /* profiler file */
68 239 markom
  int iprompt;  /* Interactive prompt */
69
  int dependstats;/* Calculation of dependency statistics */
70
  int dependency; /* Calculation of dependency (implied by dependstats) */
71
  int history;  /* Instruction stream history remembered by the simulator */
72
  int superscalar;/* "Superscalar" simulation */
73
  int slp;
74
  int inhibit_server; /* Don't start up the JTAG proxy server */
75
  int server_port; /* A user specified port number for services */
76
  int pattern_mem; /* A user specified memory initialization pattern */
77
  int random_mem;  /* Initialize the memory with random values */
78
 
79
  char* filename;  /* Original Command Simulator file (CZ) */
80 7 jrydberg
};
81 239 markom
 
82 7 jrydberg
extern struct config config;
83 239 markom
 
84
/* Read environment from a script file. Does not fail - assumes defaukt configuration instead. */
85
void read_script_file (char *filename);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.