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[/] [or1k/] [tags/] [nog_patch_62/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1765

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/* abstract.c -- Abstract entities
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
/* Abstract memory and routines that go with this. I need to
add all sorts of other abstract entities. Currently we have
only memory. */
 
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>
#include <string.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
 
#include "arch.h"
#include "parse.h"
#include "abstract.h"
#include "sim-config.h"
#include "labels.h"
#include "except.h"
#include "debug_unit.h"
#include "opcode/or32.h"
#include "spr_defs.h"
#include "execute.h"
#include "sprs.h"
#include "support/profile.h"
#include "dmmu.h"
#include "immu.h"
#include "dcache_model.h"
#include "icache_model.h"
#include "debug.h"
#include "stats.h"
 
extern char *disassembled;
 
/* Pointer to memory area descriptions that are assigned to individual
   peripheral devices. */
struct dev_memarea *dev_list;
 
/* Temporary variable to increase speed.  */
struct dev_memarea *cur_area;
 
/* Pointer to memory controller device descriptor.  */
struct dev_memarea *mc_area = (struct dev_memarea *)0;
 
/* These are set by mmu if cache inhibit bit is set for current acces.  */
int data_ci, insn_ci;
 
/* Virtual address of current access. */
oraddr_t cur_vadd;
 
/* Calculates bit mask to fit the data */
unsigned int bit_mask (uint32_t data) {
  int i = 0;
  data--;
  while (data >> i)
    data |= 1 << i++;
  return data;
}
 
/* Register read and write function for a memory area.
   addr is inside the area, if addr & addr_mask == addr_compare
   (used also by peripheral devices like 16450 UART etc.) */
void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,
                         uint32_t size, unsigned granularity, unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  struct dev_memarea **pptmp;
  unsigned int size_mask = bit_mask (size);
  int found_error = 0;
  addr_compare &= addr_mask;
 
  debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",
        addr_mask, addr_compare, addr_compare | bit_mask (size), size,
        granularity);
  /* Go to the end of the list. */
  for(pptmp = &dev_list; *pptmp; pptmp = &(*pptmp)->next)
    if ((addr_compare >= (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)
     || (addr_compare + size > (*pptmp)->addr_compare) && (addr_compare < (*pptmp)->addr_compare + (*pptmp)->size)) {
      if (!found_error) {
        fprintf (stderr, "ERROR: Overlapping memory area(s):\n");
        fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                         ", size %08"PRIx32", gran %iB\n",
                 addr_mask, addr_compare, addr_compare | bit_mask (size), size,
                 granularity);
      }
      found_error = 1;
      fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR
                       ", size %08"PRIx32", gran %iB\n",
               (*pptmp)->addr_mask, (*pptmp)->addr_compare,
               (*pptmp)->addr_compare | (*pptmp)->size_mask,
               (*pptmp)->size, (*pptmp)->granularity);
    }
 
  if (found_error)
    exit (-1);
 
  cur_area = *pptmp = (struct dev_memarea *)malloc(sizeof(struct dev_memarea));
 
  if (mc_dev)
    mc_area = *pptmp;
 
  (*pptmp)->addr_mask = addr_mask;
  (*pptmp)->addr_compare = addr_compare;
  (*pptmp)->size = size;
  (*pptmp)->size_mask = size_mask;
  (*pptmp)->granularity = granularity;
  (*pptmp)->readfunc = readfunc;
  (*pptmp)->writefunc = writefunc;
  (*pptmp)->log = 0;
  (*pptmp)->delayr = 2;
  (*pptmp)->delayw = 2;
  (*pptmp)->priv_dat = dat;
  (*pptmp)->chip_select = -1;
  (*pptmp)->next = NULL;
}
 
/* Register read and write function for a memory area.
   Memory areas should be aligned. Memory area is rounded up to
   fit the nearest 2^n aligment.
   (used also by peripheral devices like 16450 UART etc.)
   If mc_dev is 1, this means that this device will be checked first for match
   and will be accessed in case of overlaping memory spaces.
   Only one device can have this set to 1 (used for memory controller) */
void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,
                         unsigned mc_dev,
                         uint32_t (readfunc)(oraddr_t, void *),
                         void (writefunc)(oraddr_t, uint32_t, void *),
                         void *dat)
{
  unsigned int size_mask = bit_mask (size);
  unsigned int addr_mask = ~size_mask;
  register_memoryarea_mask (addr_mask, addr & addr_mask,
                      size_mask + 1, granularity, mc_dev,
                      readfunc, writefunc, dat);
}
 
 
/* Check if access is to registered area of memory. */
inline struct dev_memarea *verify_memoryarea(oraddr_t addr)
{
  struct dev_memarea *ptmp;
 
  /* Check memory controller space first */
  if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))
    return cur_area = mc_area;
 
  /* Check cached value */
  if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))
    return cur_area;
 
  /* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next)
    if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)
      return cur_area = ptmp;
  return cur_area = NULL;
}
 
/* Finds the memory area for the address and adjust the read and write delays for it. */
void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)
{
  if (verify_memoryarea(memaddr)) {
    cur_area->delayr = delayr;
    cur_area->delayw = delayw;
  }
}
 
/* for cpu accesses
 *
 * STATISTICS: check cpu/common/parse.c
 */
inline uint32_t evalsim_mem32(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint32_t evalsim_mem32_void(oraddr_t memaddr)
{
        return(evalsim_mem32_atomic(memaddr, 0));
}
 
uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      break;
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;
      temp |= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
    if (cpu_access)
      runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);
  }
  return temp;
}
 
/* for cpu accesses */
inline uint16_t evalsim_mem16(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint16_t evalsim_mem16_void(oraddr_t memaddr)
{
        return(evalsim_mem16_atomic(memaddr, 0));
}
 
uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;
      temp |= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr * 2;
      break;
    case 2:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);
      if (memaddr & 2)
        temp &= 0xffff;
      else
        temp >>= 16;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline uint8_t evalsim_mem8(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline uint8_t evalsim_mem8_void(oraddr_t memaddr)
{
        return(evalsim_mem8_atomic(memaddr, 0));
}
 
uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)
{
  uint32_t temp = 0;
 
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      temp = cur_area->readfunc(memaddr, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayr;
      break;
    case 2:
      temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);
      if (memaddr & 1)
        temp &= 0xff;
      else
        temp >>= 8;
      break;
    case 4:
      temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);
      temp >>= 8 * (3 - (memaddr & 3));
      temp &= 0xff;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  }
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * this function is only used in dumpmemory() below, so it's
 * safe to asume it's for simulator purposes access only,
 * hence the use of eval_mem32_void()
 *
 * STATISTICS OK.
 */
static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  cur_vadd = memaddr;
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
  temp = evalsim_mem32_void(memaddr);
  if (!cur_area) {
    PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
    temp = 0;
  } else if (cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_READ);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK
 */
uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 4);
  else {
    temp = evalsim_mem32_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR
             ") in eval_direct32()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 32-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)
{
  uint32_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_FETCH);
//  memaddr = simulate_ic_mmu_fetch(memaddr);
 
  cur_vadd = memaddr;
 
  memaddr = immu_translate(memaddr);
 
  if (except_pending)
    return 0;
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);
 
  if (config.ic.enabled)
    temp = ic_simulate_fetch(memaddr);
  else {
    temp = evalsim_mem32(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);
  return temp;
}
 
/* Returns 16-bit values from mem array. Big endian version.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)
{
  uint16_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_READ);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return 0;
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint16_t)dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint16_t eval_direct16(oraddr_t memaddr, int *breakpoint, int through_mmu,
                       int through_dc)
{
  uint32_t temp;
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
      return 0;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = dc_simulate_read(memaddr, 2);
  else {
    temp = evalsim_mem16_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (16-bit access to %"PRIxADDR
             ") in eval_direct16()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  return temp;
}
 
 
/* Returns 8-bit values from mem array.
 *
 * STATISTICS OK (only used for cpu_access, that is architectural access)
 */
uint8_t eval_mem8(oraddr_t memaddr,int* breakpoint)
{
  uint8_t temp;
 
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_READ);
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);  /* 28/05/01 CZ */
 
  cur_vadd = memaddr;
 
  memaddr = dmmu_translate(memaddr, 0);
  if (except_pending)
    return 0;
 
  if (config.dc.enabled)
    temp = (uint8_t)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR")\n",
             memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
 
  if (config.debug.enabled)
    *breakpoint += CheckDebugUnit(DebugLoadData,temp);  /* MM170901 */
  return temp;
}
 
/* for simulator accesses, the ones that cpu wouldn't do
 *
 * STATISTICS OK.
 */
uint8_t eval_direct8(oraddr_t memaddr, int *breakpoint, int through_mmu,
                     int through_dc)
{
  uint8_t temp;
 
  cur_vadd = memaddr;
 
  if (through_mmu)
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
 
  if (through_dc)
    temp = (unsigned char)dc_simulate_read(memaddr, 1);
  else {
    temp = evalsim_mem8_void(memaddr);
    if (!cur_area) {
      PRINTF("EXCEPTION: read out of memory (8-bit access to %"PRIxADDR
             ") in eval_direct8()\n", memaddr);
      except_handle(EXCEPT_BUSERR, cur_vadd);
      temp = 0;
    }
  }
  return temp;
}
 
/* for cpu accesses */
inline void setsim_mem32(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem32_void(oraddr_t memaddr, uint32_t value)
{
  return(setsim_mem32_atomic(memaddr, value, 0));
}
 
void setsim_mem32_atomic(oraddr_t memaddr, uint32_t value, int cpu_access)
{
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 4:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 1:
      cur_area->writefunc(memaddr    , (value >> 24) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, (value >> 16) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, (value >>  8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 3, (value      ) & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 4;
      break;
    case 2:
      cur_area->writefunc(memaddr, (value >> 16) & 0xFFFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 2, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (32-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem16(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem16_void(oraddr_t memaddr, uint16_t value)
{
  return(setsim_mem16_atomic(memaddr, value, 0));
}
 
void setsim_mem16_atomic(oraddr_t memaddr, uint16_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch(cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, (value >> 8) & 0xFF, cur_area->priv_dat);
      cur_area->writefunc(memaddr + 1, value & 0xFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw * 2;
      break;
    case 2:
      cur_area->writefunc(memaddr, value & 0xFFFF, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 4:
      temp = evalsim_mem32_void(memaddr & ~ADDR_C(3));
      temp &= 0xffff << ((memaddr & 2) ? 16 : 0);
      temp |= (unsigned long)(value & 0xffff) << ((memaddr & 2) ? 0 : 16);
      setsim_mem32_atomic(memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    default:
      /* if you add new memory granularity be sure to check the formula
       * below for the read delay and fix it if necessery
       */
      PRINTF("unknown/unhandled memory granularuty\n");
      exit(-1);
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (16-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* for cpu accesses */
inline void setsim_mem8(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 1));
}
 
/* for simulator accesses, the ones that cpu wouldn't do */
inline void setsim_mem8_void(oraddr_t memaddr, uint8_t value)
{
  return(setsim_mem8_atomic(memaddr, value, 0));
}
 
void setsim_mem8_atomic(oraddr_t memaddr, uint8_t value, int cpu_access)
{
  uint32_t temp;
  if (verify_memoryarea(memaddr)) {
    switch (cur_area->granularity) {
    case 1:
      cur_area->writefunc(memaddr, value, cur_area->priv_dat);
      if (cpu_access)
        runtime.sim.mem_cycles += cur_area->delayw;
      break;
    case 2:
      temp = evalsim_mem16_void (memaddr & ~ADDR_C(1));
      temp &= 0xff << ((memaddr & 1) ? 8 : 0);
      temp |= (unsigned short)(value & 0xff) << ((memaddr & 1) ? 0 : 8);
      setsim_mem16_atomic (memaddr & ~ADDR_C(1), temp, cpu_access);
      break;
    case 4:
      temp = evalsim_mem32_void (memaddr & ~ADDR_C(3));
      temp &= ~(0xff << (8 * (3 - (memaddr & 3))));
      temp |= (unsigned long)(value & 0xff) << (8 * (3 - (memaddr & 3)));
      setsim_mem32_atomic (memaddr & ~ADDR_C(3), temp, cpu_access);
      break;
    }
  } else {
    PRINTF("EXCEPTION: write out of memory (8-bit access to %"PRIxADDR")\n",
           memaddr);
    except_handle(EXCEPT_BUSERR, cur_vadd);
  }
}
 
/* Set mem, 32-bit. Big endian version.
 *
 * STATISTICS OK. (the only suspicious usage is in sim-cmd.c,
 *                 where this instruction is used for patching memory,
 *                 wether this is cpu or architectual access is yet to
 *                 be decided)
 */
void set_mem32(oraddr_t memaddr, uint32_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_32 | MPROF_WRITE);
 
  if (memaddr & 3) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %08"PRIx32"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct32(oraddr_t memaddr, uint32_t value,int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 3) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 1, through_dc);
  }
 
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 4);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %08"PRIx32"\n",
             memaddr, value);
}
 
 
/* Set mem, 16-bit. Big endian version. */
 
void set_mem16(oraddr_t memaddr, uint16_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_16 | MPROF_WRITE);
 
  if (memaddr & 1) {
    except_handle (EXCEPT_ALIGN, memaddr);
    return;
  }
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending)
    return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %04"PRIx16"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct16(oraddr_t memaddr, uint16_t value, int* breakpoint,
                  int through_mmu, int through_dc)
{
 
  if (memaddr & 1) {
    PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);
    return;
  }
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 2);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %04"PRIx16"\n",
             memaddr, value);
}
 
/* Set mem, 8-bit. */
 
void set_mem8(oraddr_t memaddr, uint8_t value, int* breakpoint)
{
  if (config.sim.mprofile)
    mprofile (memaddr, MPROF_8 | MPROF_WRITE);
 
  cur_vadd = memaddr;
  memaddr = dmmu_translate(memaddr, 1);;
  /* If we produced exception don't set anything */
  if (except_pending) return;
 
  if (config.debug.enabled) {
    *breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr);  /* 28/05/01 CZ */
    *breakpoint += CheckDebugUnit(DebugStoreData,value);
  }
 
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> write %02"PRIx8"\n", memaddr,
             value);
}
 
/*
 * STATISTICS NOT OK.
 */
void set_direct8(oraddr_t memaddr, uint8_t value, int* breakpoint,
                 int through_mmu, int through_dc)
{
 
  cur_vadd = memaddr;
 
  if (through_mmu) {
    /* 0 - no write access, we do not want a DPF exception do we ;)
     */
    memaddr = peek_into_dtlb(memaddr, 0, through_dc);
  }
 
  /* __PHX__ fixme: we'll get cache hit/miss delay added to cycles count,
   *                and possibly also memory access times.
   */
  if (!through_dc)
    PRINTF("WARNING: statistics might not be OK\n");
  dc_simulate_write(memaddr, value, 1);
 
  if (cur_area && cur_area->log)
    fprintf (cur_area->log, "[%"PRIxADDR"] -> DIRECT write %02"PRIx8"\n",
             memaddr, value);
}
 
 
void dumpmemory(oraddr_t from, oraddr_t to, int disasm, int nl)
{
  oraddr_t i, j;
  struct label_entry *tmp;
  int ilen = disasm ? 4 : 16;
 
  for(i = from; i < to; i += ilen) {
    PRINTF("%"PRIxADDR": ", i);
    for (j = 0; j < ilen;) {
      if (!disasm) {
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
          PRINTF("%02"PRIx8" ", evalsim_mem8(i + j));
        } else PRINTF("XX ");
        j++;
      } else {
        int breakpoint;
        uint32_t _insn = read_mem(i, &breakpoint);
        int index = insn_decode (_insn);
        int len = insn_len (index);
 
        tmp = NULL;
        if (verify_memoryarea(i + j)) {
          struct label_entry *entry;
          entry = get_label(i + j);
          if (entry)
            PRINTF("(%s)", entry->name);
 
          PRINTF(": %08"PRIx32" ", _insn);
          if (index >= 0) {
            disassemble_insn (_insn);
            PRINTF(" %s", disassembled);
          } else
            PRINTF("<invalid>");
        } else PRINTF("XXXXXXXX");
        j += len;
      }
    }
    if (nl)
      PRINTF ("\n");
  }
}
 
uint32_t simmem_read_word(oraddr_t addr, void *priv_dat) {
  return *(uint32_t *)(priv_dat + (addr & cur_area->size_mask));
}
 
void simmem_write_word(oraddr_t addr, uint32_t value, void *priv_dat) {
  *(uint32_t *)(priv_dat + (addr & cur_area->size_mask)) = value;
}
 
uint32_t simmem_read_zero(oraddr_t addr, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory read from non-read memory area 0x%"
                     PRIxADDR".\n", addr);
  return 0;
}
 
void simmem_write_null(oraddr_t addr, uint32_t value, void *dat) {
  if (config.sim.verbose)
    fprintf (stderr, "WARNING: memory write to 0x%"PRIxADDR", non-write memory area (value 0x%08"PRIx32").\n", addr, value);
}
 
/* Initialize memory table from a config struct */
 
void init_memory_table ()
{
  /* If nothing was defined, use default memory block */
  if (config.memory.nmemories) {
    int i;
    for (i = 0; i < config.memory.nmemories; i++) {
      oraddr_t start = config.memory.table[i].baseaddr;
      uint32_t length = config.memory.table[i].size;
      char *type = config.memory.table[i].name;
      int rd = config.memory.table[i].delayr;
      int wd = config.memory.table[i].delayw;
      int ce = config.memory.table[i].ce;
      void *mem = malloc (length);
 
      if (config.sim.verbose)
        debug (1, "%"PRIxADDR" %08"PRIx32" (%"PRIi32" KB): %s (activated by CE%i; read delay = %icyc, write delay = %icyc)\n",
          start, length, length >> 10, type, ce, rd, wd);
 
      if (!mem) {
        fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
        exit (-1);
      }
 
      register_memoryarea(start, length, 4, 0, &simmem_read_word,
                          &simmem_write_word, mem);
      cur_area->chip_select = ce;
      cur_area->valid = 1;
      cur_area->delayw = wd;
      cur_area->delayr = rd;
      if (config.memory.table[i].log[0] != '\0') {
        if ((cur_area->log = fopen (config.memory.table[i].log, "wt+")) == NULL)
          fprintf (stderr, "WARNING: Cannot open '%s'.\n",
                   config.memory.table[i].log);
      } else
        cur_area->log = NULL;
    }
    PRINTF ("\n");
  } else {
    void *mem = malloc (DEFAULT_MEMORY_LEN);
    if (config.sim.verbose)
      fprintf (stderr, "WARNING: Memory not defined, assuming standard configuration.\n");
 
    if (!mem) {
      fprintf (stderr, "Failed to allocate sim memory. Aborting\n");
      exit (-1);
    }
 
    register_memoryarea(DEFAULT_MEMORY_START, DEFAULT_MEMORY_LEN, 4, 0,
                        &simmem_read_word, &simmem_write_word, mem);
    cur_area->chip_select = 0;
    cur_area->valid = 1;
    cur_area->delayw = 1;
    cur_area->delayr = 1;
    cur_area->log = NULL;
  }
}
 
/* Changes read/write memory in read/write only */
 
void lock_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->delayr < 0 && ptmp->readfunc == &simmem_read_word)
      ptmp->readfunc = &simmem_read_zero;
    if (ptmp->delayw < 0 && ptmp->writefunc == &simmem_write_word)
      ptmp->writefunc = &simmem_write_null;
 
    /* If this mem area is not for memory chip under MC control
       then this area is valid all the time */
    if (ptmp->readfunc != &simmem_read_word) {
      ptmp->valid = 1;
      ptmp->chip_select = -1;
    }
  }
}
 
/* Closes files, etc. */
 
void done_memory_table ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    if (ptmp->log)
      fclose (ptmp->log);
  }
}
 
/* Displays current memory configuration */
 
void memory_table_status ()
{
  struct dev_memarea *ptmp;
 
  /* Check list of registered devices. */
  for(ptmp = dev_list; ptmp; ptmp = ptmp->next) {
    PRINTF ("addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %"PRIx32
            ", gran %iB\n",
      ptmp->addr_mask, ptmp->addr_compare, ptmp->addr_compare | bit_mask (ptmp->size),
      ptmp->size, ptmp->granularity);
    PRINTF ("\t");
    if (ptmp->delayr >= 0)
      PRINTF ("read delay = %i cycles, ", ptmp->delayr);
    else
      PRINTF ("reads not possible, ");
 
    if (ptmp->delayw >= 0)
      PRINTF ("write delay = %i cycles", ptmp->delayw);
    else
      PRINTF ("writes not possible");
 
    if (ptmp->log)
      PRINTF (", (logged)\n");
    else
      PRINTF ("\n");
  }
}
 
/* Outputs time in pretty form to dest string */
 
char *generate_time_pretty (char *dest, long time_ps)
{
  int exp3 = 0;
  if (time_ps) {
    while ((time_ps % 1000) == 0) {
      time_ps /= 1000;
      exp3++;
    }
  }
  sprintf (dest, "%li%cs", time_ps, "pnum"[exp3]);
  return dest;
}

Line No.	Rev	Author	Line
1	2	cvs	`/* abstract.c -- Abstract entities`
2			`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20	66	lampret	`/* Abstract memory and routines that go with this. I need to`
21	2	cvs	`add all sorts of other abstract entities. Currently we have`
22			`only memory. */`
23
24	221	markom	`#include <stdlib.h>`
25	2	cvs	`#include <stdio.h>`
26			`#include <ctype.h>`
27			`#include <string.h>`
28
29	6	lampret	`#include "config.h"`
30	1350	nogj
31			`#ifdef HAVE_INTTYPES_H`
32			`#include <inttypes.h>`
33			`#endif`
34
35			`#include "port.h"`
36	6	lampret
37	1350	nogj	`#include "arch.h"`
38	2	cvs	`#include "parse.h"`
39			`#include "abstract.h"`
40	1358	nogj	`#include "sim-config.h"`
41	261	markom	`#include "labels.h"`
42	32	lampret	`#include "except.h"`
43	123	markom	`#include "debug_unit.h"`
44	134	markom	`#include "opcode/or32.h"`
45	1432	nogj	`#include "spr_defs.h"`
46			`#include "execute.h"`
47			`#include "sprs.h"`
48	547	markom	`#include "support/profile.h"`
49	1308	phoenix	`#include "dmmu.h"`
50	1446	nogj	`#include "immu.h"`
51	1308	phoenix	`#include "dcache_model.h"`
52			`#include "icache_model.h"`
53			`#include "debug.h"`
54	1344	nogj	`#include "stats.h"`
55	2	cvs
56	138	markom	`extern char *disassembled;`
57	2	cvs
58	30	lampret	`/* Pointer to memory area descriptions that are assigned to individual`
59			`peripheral devices. */`
60			`struct dev_memarea *dev_list;`
61
62	221	markom	`/* Temporary variable to increase speed. */`
63			`struct dev_memarea *cur_area;`
64
65	970	simons	`/* Pointer to memory controller device descriptor. */`
66			`struct dev_memarea mc_area = (struct dev_memarea )0;`
67
68	638	simons	`/* These are set by mmu if cache inhibit bit is set for current acces. */`
69			`int data_ci, insn_ci;`
70
71	525	simons	`/* Virtual address of current access. */`
72	1350	nogj	`oraddr_t cur_vadd;`
73	525	simons
74	261	markom	`/* Calculates bit mask to fit the data */`
75	1350	nogj	`unsigned int bit_mask (uint32_t data) {`
76	261	markom	`int i = 0;`
77			`data--;`
78	382	markom	`while (data >> i)`
79	261	markom	`data \|= 1 << i++;`
80			`return data;`
81			`}`
82
83			`/* Register read and write function for a memory area.`
84			`addr is inside the area, if addr & addr_mask == addr_compare`
85			`(used also by peripheral devices like 16450 UART etc.) */`
86	1350	nogj	`void register_memoryarea_mask(oraddr_t addr_mask, oraddr_t addr_compare,`
87			`uint32_t size, unsigned granularity, unsigned mc_dev,`
88	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
89			`void (writefunc)(oraddr_t, uint32_t, void *),`
90			`void *dat)`
91	30	lampret	`{`
92	239	markom	`struct dev_memarea **pptmp;`
93	1350	nogj	`unsigned int size_mask = bit_mask (size);`
94	261	markom	`int found_error = 0;`
95			`addr_compare &= addr_mask;`
96	221	markom
97	1350	nogj	`debug(5, "addr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR", size %08"PRIx32", gran %iB\n",`
98			`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
99			`granularity);`
100	239	markom	`/* Go to the end of the list. */`
101	261	markom	`for(pptmp = &dev_list; pptmp; pptmp = &(pptmp)->next)`
102			`if ((addr_compare >= (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)`
103			`\|\| (addr_compare + size > (pptmp)->addr_compare) && (addr_compare < (pptmp)->addr_compare + (*pptmp)->size)) {`
104	262	markom	`if (!found_error) {`
105	261	markom	`fprintf (stderr, "ERROR: Overlapping memory area(s):\n");`
106	1350	nogj	`fprintf (stderr, "\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
107			`", size %08"PRIx32", gran %iB\n",`
108	1308	phoenix	`addr_mask, addr_compare, addr_compare \| bit_mask (size), size,`
109			`granularity);`
110	262	markom	`}`
111	261	markom	`found_error = 1;`
112	1350	nogj	`fprintf (stderr, "and\taddr & %"PRIxADDR" == %"PRIxADDR" to %"PRIxADDR`
113			`", size %08"PRIx32", gran %iB\n",`
114	1308	phoenix	`(pptmp)->addr_mask, (pptmp)->addr_compare,`
115			`(pptmp)->addr_compare \| (pptmp)->size_mask,`
116			`(pptmp)->size, (pptmp)->granularity);`
117	261	markom	`}`
118
119			`if (found_error)`
120			`exit (-1);`
121	537	markom
122	239	markom	`cur_area = pptmp = (struct dev_memarea )malloc(sizeof(struct dev_memarea));`
123	970	simons
124			`if (mc_dev)`
125			`mc_area = *pptmp;`
126
127	261	markom	`(*pptmp)->addr_mask = addr_mask;`
128			`(*pptmp)->addr_compare = addr_compare;`
129	239	markom	`(*pptmp)->size = size;`
130	261	markom	`(*pptmp)->size_mask = size_mask;`
131	239	markom	`(*pptmp)->granularity = granularity;`
132			`(*pptmp)->readfunc = readfunc;`
133			`(*pptmp)->writefunc = writefunc;`
134	479	markom	`(*pptmp)->log = 0;`
135	882	simons	`(*pptmp)->delayr = 2;`
136			`(*pptmp)->delayw = 2;`
137	1359	nogj	`(*pptmp)->priv_dat = dat;`
138	1362	nogj	`(*pptmp)->chip_select = -1;`
139	239	markom	`(*pptmp)->next = NULL;`
140	261	markom	`}`
141	221	markom
142	261	markom	`/* Register read and write function for a memory area.`
143			`Memory areas should be aligned. Memory area is rounded up to`
144			`fit the nearest 2^n aligment.`
145	970	simons	`(used also by peripheral devices like 16450 UART etc.)`
146			`If mc_dev is 1, this means that this device will be checked first for match`
147	1359	nogj	`and will be accessed in case of overlaping memory spaces.`
148	970	simons	`Only one device can have this set to 1 (used for memory controller) */`
149	1350	nogj	`void register_memoryarea(oraddr_t addr, uint32_t size, unsigned granularity,`
150			`unsigned mc_dev,`
151	1359	nogj	`uint32_t (readfunc)(oraddr_t, void *),`
152			`void (writefunc)(oraddr_t, uint32_t, void *),`
153			`void *dat)`
154	261	markom	`{`
155	1350	nogj	`unsigned int size_mask = bit_mask (size);`
156			`unsigned int addr_mask = ~size_mask;`
157	261	markom	`register_memoryarea_mask (addr_mask, addr & addr_mask,`
158	970	simons	`size_mask + 1, granularity, mc_dev,`
159	1359	nogj	`readfunc, writefunc, dat);`
160	30	lampret	`}`
161
162	261	markom
163	30	lampret	`/* Check if access is to registered area of memory. */`
164	1350	nogj	`inline struct dev_memarea *verify_memoryarea(oraddr_t addr)`
165	30	lampret	`{`
166	239	markom	`struct dev_memarea *ptmp;`
167	221	markom
168	970	simons	`/* Check memory controller space first */`
169			`if (mc_area && (addr & mc_area->addr_mask) == (mc_area->addr_compare & mc_area->addr_mask))`
170			`return cur_area = mc_area;`
171
172			`/* Check cached value */`
173	560	markom	`if (cur_area && (addr & cur_area->addr_mask) == (cur_area->addr_compare & cur_area->addr_mask))`
174			`return cur_area;`
175
176			`/* When mc is enabled, we must check valid also, otherwise we assume it is nonzero */`
177	1375	nogj	`/* Check list of registered devices. */`
178			`for(ptmp = dev_list; ptmp; ptmp = ptmp->next)`
179			`if ((addr & ptmp->addr_mask) == (ptmp->addr_compare & ptmp->addr_mask) && ptmp->valid)`
180			`return cur_area = ptmp;`
181	239	markom	`return cur_area = NULL;`
182	30	lampret	`}`
183
184	882	simons	`/* Finds the memory area for the address and adjust the read and write delays for it. */`
185	1350	nogj	`void adjust_rw_delay(oraddr_t memaddr, unsigned int delayr, unsigned int delayw)`
186	882	simons	`{`
187			`if (verify_memoryarea(memaddr)) {`
188			`cur_area->delayr = delayr;`
189			`cur_area->delayw = delayw;`
190			`}`
191			`}`
192
193	1319	phoenix	`/* for cpu accesses`
194			`*`
195			`* STATISTICS: check cpu/common/parse.c`
196			`*/`
197	1350	nogj	`inline uint32_t evalsim_mem32(oraddr_t memaddr)`
198	560	markom	`{`
199	1319	phoenix	`return(evalsim_mem32_atomic(memaddr, 1));`
200			`}`
201	560	markom
202	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
203	1350	nogj	`inline uint32_t evalsim_mem32_void(oraddr_t memaddr)`
204	1319	phoenix	`{`
205			`return(evalsim_mem32_atomic(memaddr, 0));`
206			`}`
207
208	1350	nogj	`uint32_t evalsim_mem32_atomic(oraddr_t memaddr, int cpu_access)`
209	1319	phoenix	`{`
210	1350	nogj	`uint32_t temp = 0;`
211	1319	phoenix
212	560	markom	`if (verify_memoryarea(memaddr)) {`
213			`switch(cur_area->granularity) {`
214			`case 4:`
215	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
216	560	markom	`break;`
217			`case 1:`
218	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 24;`
219			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat) << 16;`
220			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat) << 8;`
221			`temp \|= cur_area->readfunc(memaddr + 3, cur_area->priv_dat);`
222	560	markom	`break;`
223			`case 2:`
224	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 16;`
225			`temp \|= cur_area->readfunc(memaddr + 2, cur_area->priv_dat);`
226	560	markom	`break;`
227	1319	phoenix	`default:`
228			`/* if you add new memory granularity be sure to check the formula`
229			`* below for the read delay and fix it if necessery`
230			`*/`
231			`PRINTF("unknown/unhandled memory granularuty\n");`
232			`exit(-1);`
233	560	markom	`}`
234	1319	phoenix	`if (cpu_access)`
235			`runtime.sim.mem_cycles += cur_area->delayr * (4 / cur_area->granularity);`
236	560	markom	`}`
237			`return temp;`
238			`}`
239
240	1319	phoenix	`/* for cpu accesses */`
241	1350	nogj	`inline uint16_t evalsim_mem16(oraddr_t memaddr)`
242	560	markom	`{`
243	1319	phoenix	`return(evalsim_mem16_atomic(memaddr, 1));`
244			`}`
245	560	markom
246	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
247	1350	nogj	`inline uint16_t evalsim_mem16_void(oraddr_t memaddr)`
248	1319	phoenix	`{`
249			`return(evalsim_mem16_atomic(memaddr, 0));`
250			`}`
251
252	1350	nogj	`uint16_t evalsim_mem16_atomic(oraddr_t memaddr, int cpu_access)`
253	1319	phoenix	`{`
254	1350	nogj	`uint32_t temp = 0;`
255	1319	phoenix
256	560	markom	`if (verify_memoryarea(memaddr)) {`
257			`switch(cur_area->granularity) {`
258			`case 1:`
259	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat) << 8;`
260			`temp \|= cur_area->readfunc(memaddr + 1, cur_area->priv_dat);`
261	1319	phoenix	`if (cpu_access)`
262			`runtime.sim.mem_cycles += cur_area->delayr * 2;`
263	560	markom	`break;`
264			`case 2:`
265	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
266	1319	phoenix	`if (cpu_access)`
267			`runtime.sim.mem_cycles += cur_area->delayr;`
268	560	markom	`break;`
269			`case 4:`
270	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~UINT32_C(3), cpu_access);`
271	560	markom	`if (memaddr & 2)`
272			`temp &= 0xffff;`
273			`else`
274			`temp >>= 16;`
275			`break;`
276	1319	phoenix	`default:`
277			`/* if you add new memory granularity be sure to check the formula`
278			`* below for the read delay and fix it if necessery`
279			`*/`
280			`PRINTF("unknown/unhandled memory granularuty\n");`
281			`exit(-1);`
282	560	markom	`}`
283			`}`
284			`return temp;`
285			`}`
286
287	1319	phoenix	`/* for cpu accesses */`
288	1350	nogj	`inline uint8_t evalsim_mem8(oraddr_t memaddr)`
289	560	markom	`{`
290	1319	phoenix	`return(evalsim_mem8_atomic(memaddr, 1));`
291			`}`
292	560	markom
293	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do */`
294	1350	nogj	`inline uint8_t evalsim_mem8_void(oraddr_t memaddr)`
295	1319	phoenix	`{`
296			`return(evalsim_mem8_atomic(memaddr, 0));`
297			`}`
298
299	1350	nogj	`uint8_t evalsim_mem8_atomic(oraddr_t memaddr, int cpu_access)`
300	1319	phoenix	`{`
301	1350	nogj	`uint32_t temp = 0;`
302	1319	phoenix
303	560	markom	`if (verify_memoryarea(memaddr)) {`
304			`switch(cur_area->granularity) {`
305			`case 1:`
306	1359	nogj	`temp = cur_area->readfunc(memaddr, cur_area->priv_dat);`
307	1319	phoenix	`if (cpu_access)`
308			`runtime.sim.mem_cycles += cur_area->delayr;`
309	560	markom	`break;`
310			`case 2:`
311	1350	nogj	`temp = evalsim_mem16_atomic (memaddr & ~ADDR_C(1), cpu_access);`
312	560	markom	`if (memaddr & 1)`
313			`temp &= 0xff;`
314			`else`
315			`temp >>= 8;`
316			`break;`
317			`case 4:`
318	1350	nogj	`temp = evalsim_mem32_atomic (memaddr & ~ADDR_C(3), cpu_access);`
319	560	markom	`temp >>= 8 * (3 - (memaddr & 3));`
320			`temp &= 0xff;`
321			`break;`
322	1319	phoenix	`default:`
323			`/* if you add new memory granularity be sure to check the formula`
324			`* below for the read delay and fix it if necessery`
325			`*/`
326			`PRINTF("unknown/unhandled memory granularuty\n");`
327			`exit(-1);`
328	560	markom	`}`
329			`}`
330			`return temp;`
331			`}`
332
333	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
334			`*`
335	1350	nogj	`* this function is only used in dumpmemory() below, so it's`
336	1319	phoenix	`* safe to asume it's for simulator purposes access only,`
337			`* hence the use of eval_mem32_void()`
338			`*`
339			`* STATISTICS OK.`
340			`*/`
341	1350	nogj	`static uint32_t read_mem(oraddr_t memaddr, int* breakpoint)`
342	349	simons	`{`
343	1350	nogj	`uint32_t temp;`
344	349	simons
345	525	simons	`cur_vadd = memaddr;`
346	550	markom	`if (config.debug.enabled)`
347	349	simons	`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
348	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
349	611	simons	`if (!cur_area) {`
350	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
351			`memaddr);`
352	611	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
353			`temp = 0;`
354	1386	nogj	`} else if (cur_area->log)`
355			`fprintf (cur_area->log, "[%"PRIxADDR"] -> read %08"PRIx32"\n", memaddr, temp);`
356	611	simons
357	550	markom	`if (config.debug.enabled)`
358	349	simons	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
359			`return temp;`
360	537	markom	`}`
361	349	simons
362	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
363			`*`
364			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
365			`*/`
366	1350	nogj	`uint32_t eval_mem32(oraddr_t memaddr,int* breakpoint)`
367	2	cvs	`{`
368	1350	nogj	`uint32_t temp;`
369	123	markom
370	547	markom	`if (config.sim.mprofile)`
371			`mprofile (memaddr, MPROF_32 \| MPROF_READ);`
372
373	538	markom	`if (memaddr & 3) {`
374			`except_handle (EXCEPT_ALIGN, memaddr);`
375			`return 0;`
376			`}`
377	557	markom
378	631	simons	`if (config.debug.enabled)`
379			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
380
381	574	markom	`cur_vadd = memaddr;`
382	631	simons
383			`memaddr = dmmu_translate(memaddr, 0);`
384	1386	nogj	`if (except_pending)`
385	574	markom	`return 0;`
386
387	992	simons	`if (config.dc.enabled)`
388			`temp = dc_simulate_read(memaddr, 4);`
389			`else {`
390			`temp = evalsim_mem32(memaddr);`
391			`if (!cur_area) {`
392	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
393			`memaddr);`
394	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
395			`temp = 0;`
396			`}`
397	611	simons	`}`
398
399	550	markom	`if (config.debug.enabled)`
400	270	markom	`breakpoint += CheckDebugUnit(DebugLoadData,temp); / MM170901 */`
401	239	markom	`return temp;`
402	66	lampret	`}`
403
404	1319	phoenix	`/* for simulator accesses, the ones that cpu wouldn't do`
405			`*`
406			`* STATISTICS OK`
407			`*/`
408	1350	nogj	`uint32_t eval_direct32(oraddr_t memaddr, int *breakpoint, int through_mmu,`
409			`int through_dc)`
410	1240	phoenix	`{`
411	1350	nogj	`uint32_t temp;`
412	1240	phoenix
413			`if (memaddr & 3) {`
414			`PRINTF("%s:%d %s(): ERR unaligned access\n", __FILE__, __LINE__, __FUNCTION__);`
415			`return 0;`
416			`}`
417
418			`cur_vadd = memaddr;`
419
420			`if (through_mmu)`
421			`memaddr = peek_into_dtlb(memaddr, 0, through_dc);`
422
423			`if (through_dc)`
424			`temp = dc_simulate_read(memaddr, 4);`
425			`else {`
426	1319	phoenix	`temp = evalsim_mem32_void(memaddr);`
427	1240	phoenix	`if (!cur_area) {`
428	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR`
429			`") in eval_direct32()\n", memaddr);`
430	1240	phoenix	`except_handle(EXCEPT_BUSERR, cur_vadd);`
431			`temp = 0;`
432			`}`
433			`}`
434
435			`return temp;`
436			`}`
437
438
439	1319	phoenix	`/* Returns 32-bit values from mem array. Big endian version.`
440			`*`
441			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
442			`*/`
443	1386	nogj	`uint32_t eval_insn(oraddr_t memaddr, int* breakpoint)`
444	349	simons	`{`
445	1350	nogj	`uint32_t temp;`
446	349	simons
447	547	markom	`if (config.sim.mprofile)`
448			`mprofile (memaddr, MPROF_32 \| MPROF_FETCH);`
449	532	markom	`// memaddr = simulate_ic_mmu_fetch(memaddr);`
450	1244	hpanther
451	1386	nogj	`cur_vadd = memaddr;`
452	1244	hpanther
453	1386	nogj	`memaddr = immu_translate(memaddr);`
454
455			`if (except_pending)`
456			`return 0;`
457
458			`if (config.debug.enabled)`
459			`*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr);`
460
461	631	simons	`if (config.ic.enabled)`
462			`temp = ic_simulate_fetch(memaddr);`
463	992	simons	`else {`
464	631	simons	`temp = evalsim_mem32(memaddr);`
465	992	simons	`if (!cur_area) {`
466	1350	nogj	`PRINTF("EXCEPTION: read out of memory (32-bit access to %"PRIxADDR")\n",`
467			`memaddr);`
468	992	simons	`except_handle(EXCEPT_BUSERR, cur_vadd);`
469			`temp = 0;`
470			`}`
471	611	simons	`}`
472
473	1386	nogj	`if (config.debug.enabled)`
474			`*breakpoint += CheckDebugUnit(DebugLoadData,temp);`
475	349	simons	`return temp;`
476			`}`
477
478	1319	phoenix	`/* Returns 16-bit values from mem array. Big endian version.`
479			`*`
480			`* STATISTICS OK (only used for cpu_access, that is architectural access)`
481			`*/`
482	1350	nogj	`uint16_t eval_mem16(oraddr_t memaddr,int* breakpoint)`
483	2	cvs	`{`
484	1350	nogj	`uint16_t temp;`
485	547	markom
486			`if (config.sim.mprofile)`
487			`mprofile (memaddr, MPROF_16 \| MPROF_READ);`
488
489	538	markom	`if (memaddr & 1) {`
490			`except_handle (EXCEPT_ALIGN, memaddr);`
491			`return 0;`
492			`}`
493	574	markom
494	631	simons	`if (config.debug.enabled)`
495			`breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); / 28/05/01 CZ */`
496
497	574	markom	`cur_vadd = memaddr;`
498	631	simons
499			`memaddr = dmmu_translate(memaddr, 0);`
500	1386	nogj	`if (except_pending)`

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[/] [or1k/] [tags/] [nog_patch_62/] [or1ksim/] [cpu/] [common/] [abstract.c] - Blame information for rev 1765