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[/] [or1k/] [tags/] [nog_patch_68/] [or1ksim/] [cuc/] [verilog.c] - Blame information for rev 1308

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1 1244 hpanther 
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
2 
 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org
3 
 *
4 
 *    This file is part of OpenRISC 1000 Architectural Simulator.
5 
 *
6 
 *    This program is free software; you can redistribute it and/or modify
7 
 *    it under the terms of the GNU General Public License as published by
8 
 *    the Free Software Foundation; either version 2 of the License, or
9 
 *    (at your option) any later version.
10 
 *
11 
 *    This program is distributed in the hope that it will be useful,
12 
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
 *    GNU General Public License for more details.
15 
 *
16 
 *    You should have received a copy of the GNU General Public License
17 
 *    along with this program; if not, write to the Free Software
18 
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
#include <stdio.h>
21 
#include <stdlib.h>
22 
#include <stdarg.h>
23 
#include <assert.h>
24 1308 phoenix 
 
25 
#include "abstract.h"
26 1244 hpanther 
#include "cuc.h"
27 
#include "insn.h"
28 
#include "profiler.h"
29 
#include "sim-config.h"
30 
 
31 
/* Shortcut */
32 
#define GEN(x...) fprintf (fo, x)
33 
 
34 
/* Find index of load/store/call */
35 
int find_lsc_index (cuc_func *f, int ref)
36 
{
37 
  int c = 0;
38 
  int i;
39 
  int load;
40 
 
41 
  if (f->INSN(ref).index == II_CALL) {
42 
    for (i = 0; i < f->nmsched; i++) {
43 
      if (f->msched[i] == ref) break;
44 
      if (f->mtype[i] & MT_CALL) c++;
45 
    }
46 
  } else {
47 
    load = II_IS_LOAD (f->INSN(ref).index);
48 
    for (i = 0; i < f->nmsched; i++) {
49 
      if (f->msched[i] == ref) break;
50 
      if (load && (f->mtype[i] & MT_LOAD)
51 
       || !load && (f->mtype[i] & MT_STORE)) c++;
52 
    }
53 
  }
54 
  return c;
55 
}
56 
 
57 
/* Print out dependencies as verilog expression */
58 
void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
59 
{
60 
  if (t) {
61 
    int first = 0;
62 
    while (t) {
63 
      if (f->INSN(t->ref).type & IT_MEMORY) {
64 
        GEN ("%s%c_end[%i]", first ? " && " : "",
65 
                  II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
66 
      } else if (f->INSN(t->ref).index == II_CALL) {
67 
        GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
68 
      } else {
69 1308 phoenix 
        PRINTF ("print_deps: err %lx\n", t->ref);
70 1244 hpanther 
        assert (0);
71 
      }
72 
      first = 1;
73 
      t = t->next;
74 
    }
75 
  } else {
76 
    if (registered) GEN ("bb_start_r[%i]", b);
77 
    else GEN ("bb_start[%i]", b);
78 
  }
79 
}
80 
 
81 
char *print_op_v (cuc_func *f, char *s, int ref, int j)
82 
{
83 
  unsigned long op = f->INSN(ref).op[j];
84 
  unsigned long opt = f->INSN(ref).opt[j];
85 
  switch (opt & ~OPT_DEST) {
86 
    case OPT_NONE: assert (0); break;
87 
    case OPT_CONST: if (f->INSN(ref).type & IT_COND && (f->INSN(ref).index == II_CMOV
88 
                     || f->INSN(ref).index == II_ADD)) {
89 
                      assert (op == 0 || op == 1);
90 1308 phoenix 
                      sprintf (s, "1'b%lx", op);
91 
                    } else sprintf (s, "32'h%lx", op);
92 1244 hpanther 
                    break;
93 
    case OPT_REGISTER:
94 
                    if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
95 1308 phoenix 
                    else sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
96 1244 hpanther 
                    break;
97 
#if 0
98 
    case OPT_FREG:  assert (opt & OPT_DEST);
99 
                    sprintf (s, "fr%i_o", op);
100 
                    break;
101 
#endif
102 1308 phoenix 
    case OPT_REF:   sprintf (s, "t%lx_%lx", REF_BB(op), REF_I(op)); break;
103 1244 hpanther 
  }
104 
  return s;
105 
}
106 
 
107 
/* Prints out specified instruction */
108 
void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
109 
{
110 
  cuc_insn *ii = &f->bb[b].insn[i];
111 
  char *s = known[ii->index].rtl;
112 
  char tmp[200] = "";
113 
 
114 
  assert (s);
115 
  while (*s) {
116 
    if (*s <= MAX_OPERANDS) {
117 
      char t[30];
118 
      sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
119 
    } else if (*s == '\b') sprintf (tmp, "%s%i", b);
120 
    else sprintf (tmp, "%s%c", tmp, *s);
121 
    s++;
122 
  }
123 
  GEN ("%-40s /* %s */\n", tmp, ii->disasm);
124 
  if (ii->type & IT_MEMORY) {
125 1308 phoenix 
    int nls = find_lsc_index (f, REF (b, i));
126 1244 hpanther 
    if (II_IS_LOAD (ii->index)) {
127 
      int nm;
128 
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
129 
      assert (nm < f->nmsched);
130 
 
131 
      GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
132 
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
133 
        case 1: GEN ("l_dat_i & 32'hff;\n");
134 
                break;
135 
        case 2: GEN ("l_dat_i & 32'hffff;\n");
136 
                break;
137 
        case 4 | MT_SIGNED:
138 
        case 4: GEN ("l_dat_i;\n");
139 
                break;
140 
        case 1 | MT_SIGNED:
141 
                GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
142 
                break;
143 
        case 2 | MT_SIGNED:
144 
                GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
145 
                break;
146 
        default: assert (0);
147 
      }
148 
    }
149 
  } else if (ii->index == II_LRBB) {
150 
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
151 
    assert (f->bb[b].prev[0] >= 0);
152 
    if (f->bb[b].prev[0] == BBID_START)
153 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
154 
    else
155 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
156 
  } else if (ii->index == II_REG) {
157 
    assert (ii->opt[1] == OPT_REF);
158 
    GEN ("  if (");
159 
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
160 
    else GEN ("bb_stb[%i]", b);
161 1308 phoenix 
    GEN (") t%x_%x <= #Tp t%lx_%lx;\n",  b, i,
162 1244 hpanther 
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
163 
  }
164 
}
165 
 
166 
/* Outputs binary number */
167 
static char *bin_str (unsigned long x, int len)
168 
{
169 
  static char bx[33];
170 
  char *s = bx;
171 
  while (len > 0) *s++ = '0' + ((x >> --len) & 1);
172 
  *s = '\0';
173 
  return bx;
174 
}
175 
 
176 
/* Returns index of branch instruction inside a block b */
177 
static int branch_index (cuc_bb *bb)
178 
{
179 
  int i;
180 
  for (i = bb->ninsn - 1; i >= 0; i--)
181 
    if (bb->insn[i].type & IT_BRANCH) return i;
182 
  return -1;
183 
}
184 
 
185 
static void print_turn_off_dep (FILE *fo, cuc_func *f, dep_list *dep)
186 
{
187 
  while (dep) {
188 
    assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
189 
    GEN ("      %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
190 
            : II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
191 
    dep = dep->next;
192 
  }
193 
}
194 
 
195 
static int func_index (cuc_func *f, int ref)
196 
{
197 
  int i;
198 
  unsigned long addr;
199 
  assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
200 
  addr = f->INSN(ref).op[0];
201 
  for (i = 0; i < f->nfdeps; i++)
202 
    if (f->fdeps[i]->start_addr == addr) return i;
203 
 
204 
  assert (0);
205 
  return -1;
206 
}
207 
 
208 
/* Generates verilog file out of insn dataflow */
209 
void output_verilog (cuc_func *f, char *filename, char *funcname)
210 
{
211 
  FILE *fo;
212 
  int b, i, j;
213 
  int ci = 0, co = 0;
214 
  int nloads = 0, nstores = 0, ncalls = 0;
215 
  char tmp[256];
216 
  sprintf (tmp, "%s.v", filename);
217 
 
218 
  log ("Generating verilog file \"%s\"\n", tmp);
219 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
220 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
221 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
222 
    exit (1);
223 
  }
224 
 
225 
  /* output header */
226 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
227 
  GEN ("   (C) 2002 Opencores\n");
228 
  GEN ("   function   \"%s\"\n", funcname);
229 1308 phoenix 
  GEN ("   at         %08lx - %08lx\n", f->start_addr, f->end_addr);
230 1244 hpanther 
  GEN ("   num BBs    %i */\n\n", f->num_bb);
231 
 
232 
  GEN ("`include \"timescale.v\"\n\n");
233 
  GEN ("module %s (clk, rst,\n", filename);
234 
  GEN ("              l_adr_o, l_dat_i, l_req_o,\n");
235 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i,\n");
236 
  GEN ("              s_adr_o, s_dat_o, s_req_o,\n");
237 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i,\n");
238 
 
239 
  GEN ("/* inputs */  ");
240 
  for (i = 0; i < MAX_REGS; i++)
241 
    if (f->used_regs[i]) {
242 
      GEN ("r%i_i, ", i);
243 
      ci++;
244 
    }
245 
  if (!ci) GEN ("/* NONE */");
246 
 
247 
  GEN ("\n/* outputs */ ");
248 
  for (i = 0; i < MAX_REGS; i++)
249 
    if (f->lur[i] >= 0 && !f->saved_regs[i]) {
250 
      GEN ("r%i_o, ", i);
251 
      co++;
252 
    }
253 
 
254 
  if (!co) GEN ("/* NONE */");
255 
  if (f->nfdeps) {
256 
    GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
257 
                    log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
258 
    for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
259 
  }
260 
  GEN ("\n              start_i, end_o, busy_o);\n\n");
261 
 
262 
  GEN ("parameter Tp = 1;\n\n");
263 
 
264 
  GEN ("input         clk, rst;\n");
265 
  GEN ("input         start_i;\t/* Module starts when set to 1 */ \n");
266 
  GEN ("output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
267 
  GEN ("output        busy_o;\t/* Set when module should not be interrupted */\n");
268 
  GEN ("\n/* Bus signals */\n");
269 
  GEN ("output        l_req_o, s_req_o;\n");
270 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
271 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
272 
  GEN ("output [31:0] l_adr_o, s_adr_o;\n");
273 
  GEN ("output        l_linbrst_o, s_linbrst_o;\n");
274 
  GEN ("input  [31:0] l_dat_i;\n");
275 
  GEN ("output [31:0] s_dat_o;\n\n");
276 
 
277 
  GEN ("reg           l_req_o, s_req_o;\n");
278 
  GEN ("reg    [31:0] l_adr_o, s_adr_o;\n");
279 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
280 
  GEN ("reg    [31:0] s_dat_o;\n");
281 
  GEN ("reg           l_linbrst_o, s_linbrst_o;\n");
282 
 
283 
  if (ci || co) GEN ("\n/* module ports */\n");
284 
  if (ci) {
285 
    int first = 1;
286 
    GEN ("input  [31:0]");
287 
    for (i = 0; i < MAX_REGS; i++)
288 
      if (f->used_regs[i]) {
289 
        GEN ("%sr%i_i", first ? " " : ", ", i);
290 
        first = 0;
291 
      }
292 
    GEN (";\n");
293 
  }
294 
 
295 
  if (co) {
296 
    int first = 1;
297 
    GEN ("output [31:0]");
298 
    for (i = 0; i < MAX_REGS; i++)
299 
      if (f->lur[i] >= 0 && !f->saved_regs[i]) {
300 
        GEN ("%sr%i_o", first ? " " : ", ", i);
301 
        first = 0;
302 
      }
303 
    GEN (";\n");
304 
  }
305 
 
306 
  if (f->nfdeps) {
307 
    GEN ("\n/* Function calls */\n");
308 
    GEN ("output [31:0] fr3_o");
309 
    for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
310 
    GEN (";\n");
311 
    GEN ("input  [31:0] fr11_i;\n");
312 
    if (log2_int(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2_int(f->nfdeps));
313 
    GEN ("output        fstart_o;\n");
314 
    GEN ("input         fend_i;\n");
315 
  }
316 
 
317 
  /* Count loads & stores */
318 
  for (i = 0; i < f->nmsched; i++)
319 
    if (f->mtype[i] & MT_STORE) nstores++;
320 
    else if (f->mtype[i] & MT_LOAD) nloads++;
321 
    else if (f->mtype[i] & MT_CALL) ncalls++;
322 
 
323 
  /* Output internal registers for loads */
324 
  if (nloads) {
325 
    int first = 1;
326 
    int num = 0;
327 
    GEN ("\n/* internal registers for loads */\n");
328 
    for (i = 0; i < f->nmsched; i++)
329 
      if (f->mtype[i] & MT_LOAD) {
330 
        GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ",
331 
                REF_BB(f->msched[i]), REF_I(f->msched[i]));
332 
 
333 
        if (num >= 8) {
334 
          GEN (";\n");
335 
          first = 1;
336 
          num = 0;
337 
        } else {
338 
          first = 0;
339 
          num++;
340 
        }
341 
      }
342 
    if (!first) GEN (";\n");
343 
  }
344 
 
345 
  /* Internal register for function return value */
346 
  if (f->nfdeps) {
347 
    GEN ("\n/* Internal register for function return value */\n");
348 
    GEN ("reg     [31:0] fr11_r;\n");
349 
  }
350 
 
351 
  GEN ("\n/* 'zero or one' hot state machines */\n");
352 
  if (nloads) GEN ("reg     [%i:0] l_stb; /* loads */\n", nloads - 1);
353 
  if (nstores) GEN ("reg     [%i:0] s_stb; /* stores */\n", nstores - 1);
354 
  GEN ("reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
355 
 
356 
  {
357 
    int first = 2;
358 
    int num = 0;
359 
    for (b = 0; b < f->num_bb; b++)
360 
      for (i = 0; i < f->bb[b].ninsn; i++)
361 
        if (f->bb[b].insn[i].type & IT_COND
362 
         && f->bb[b].insn[i].index != II_REG
363 
         && f->bb[b].insn[i].index != II_LRBB) {
364 
          if (first == 2) GEN ("\n/* basic block condition wires */\n");
365 
          GEN ("%st%x_%x", first ? "wire          " : ", ", b, i);
366 
          if (num >= 8) {
367 
            GEN (";\n");
368 
            first = 1;
369 
            num = 0;
370 
          } else {
371 
            first = 0;
372 
            num++;
373 
          }
374 
        }
375 
    if (!first) GEN (";\n");
376 
 
377 
    GEN ("\n/* forward declaration of normal wires */\n");
378 
    num = 0;
379 
    first = 1;
380 
    for (b = 0; b < f->num_bb; b++)
381 
      for (i = 0; i < f->bb[b].ninsn; i++)
382 
        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
383 
         && f->bb[b].insn[i].index != II_REG
384 
         && f->bb[b].insn[i].index != II_LRBB) {
385 
          /* Exclude loads */
386 
          if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
387 
          GEN ("%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);
388 
          if (num >= 8) {
389 
            GEN (";\n");
390 
            first = 1;
391 
            num = 0;
392 
          } else {
393 
            first = 0;
394 
            num++;
395 
          }
396 
        }
397 
    if (!first) GEN (";\n");
398 
 
399 
    GEN ("\n/* forward declaration registers */\n");
400 
    num = 0;
401 
    first = 1;
402 
    for (b = 0; b < f->num_bb; b++)
403 
      for (i = 0; i < f->bb[b].ninsn; i++)
404 
        if (f->bb[b].insn[i].index == II_REG
405 
         && f->bb[b].insn[i].index != II_LRBB) {
406 
          GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);
407 
          if (num >= 8) {
408 
            GEN (";\n");
409 
            first = 1;
410 
            num = 0;
411 
          } else {
412 
            first = 0;
413 
            num++;
414 
          }
415 
        }
416 
    if (!first) GEN (";\n");
417 
 
418 
    num = 0;
419 
    first = 1;
420 
    for (b = 0; b < f->num_bb; b++)
421 
      for (i = 0; i < f->bb[b].ninsn; i++)
422 
        if (f->bb[b].insn[i].index != II_REG
423 
         && f->bb[b].insn[i].index == II_LRBB) {
424 
          GEN ("%st%x_%x", first ? "reg           " : ", ", b, i);
425 
          if (num >= 8) {
426 
            GEN (";\n");
427 
            first = 1;
428 
            num = 0;
429 
          } else {
430 
            first = 0;
431 
            num++;
432 
          }
433 
        }
434 
    if (!first) GEN (";\n");
435 
  }
436 
 
437 
  if (nloads || nstores) GEN ("\n/* dependencies */\n");
438 
  if (nloads) GEN ("wire    [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
439 
                  nloads - 1, nloads);
440 
  if (nstores) GEN ("wire    [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
441 
                  nstores - 1, nstores);
442 
  if (ncalls) GEN ("wire    [%i:0] f_end = f_stb & {%i{fend_i}};\n",
443 
                  ncalls - 1, ncalls);
444 
 
445 
  GEN ("\n/* last dependency */\n");
446 
  GEN ("wire   end_o = ");
447 
  for (b = 0; b < f->num_bb; b++) {
448 
    for (i = 0; i < 2; i++) if (f->bb[b].next[i] == BBID_END) {
449 
      GEN ("bb_stb[%i]", b);
450 
      if (f->bb[b].mdep) {
451 
        GEN (" && ");
452 
        print_deps (fo, f, b, f->bb[b].mdep, 0);
453 
      }
454 
      /* Is branch to BBID_END conditional? */
455 
      if (f->bb[b].next[1 - i] >= 0) {
456 
        int bidx = branch_index (&f->bb[b]);
457 
        char t[30];
458 
        print_op_v (f, t, REF (b, bidx), 1);
459 
        GEN (" && %s%s", i ? "" : "!", t);
460 
      }
461 
    }
462 
  }
463 
  GEN (";\n");
464 
  GEN ("wire   busy_o = |bb_stb;\n");
465 
 
466 
 
467 
  GEN ("\n/* Basic block triggers */\n");
468 
  GEN ("wire   [%2i:0] bb_start = {\n", f->num_bb - 1);
469 
  for (b = f->num_bb - 1; b >= 0; b--) {
470 
    GEN ("    /* bb_start[%2i] */ ", b);
471 
    for (i = 0; i < 2; i++) if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START) {
472 
      cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
473 
      int t;
474 
      if (i) GEN ("\n                    || ");
475 
      if (prev->mdep) {
476 
        print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
477 
        GEN (" && ");
478 
      }
479 
      GEN ("bb_stb[%i]", f->bb[b].prev[i]);
480 
      if (prev->next[0] >= 0 && prev->next[0] != BBID_END
481 
       && prev->next[1] >= 0 && prev->next[1] != BBID_END) {
482 
        int bi = REF (f->bb[b].prev[i], branch_index (&f->bb[f->bb[b].prev[i]]));
483 
        int ci;
484 
        assert (bi >= 0);
485 
        ci = f->INSN(bi).op[1];
486 
        t = prev->next[0] == b;
487 
        GEN (" && ");
488 
        if (f->INSN(bi).opt[1] & OPT_REF) {
489 
          GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
490 
        } else {
491 
          cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
492 
          assert (f->INSN(bi).opt[1] & OPT_CONST);
493 
          GEN ("%s%i", t ? "" : "!", ci);
494 
        }
495 
      }
496 
    } else break;
497 
    if (!i) GEN ("start_i");
498 
    if (b == 0) GEN ("};\n");
499 
    else GEN (",\n");
500 
  }
501 
 
502 
  GEN ("\n/* Register the bb_start */\n");
503 
  GEN ("reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
504 
  GEN ("always @(posedge rst or posedge clk)\n");
505 
  GEN ("begin\n");
506 
  GEN ("  if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
507 
  GEN ("  else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
508 
  GEN ("  else bb_start_r <= #Tp bb_start;\n");
509 
  GEN ("end\n");
510 
 
511 
  GEN ("\n/* Logic */\n");
512 
  /* output body */
513 
  for (b = 0; b < f->num_bb; b++) {
514 
    GEN ("\t\t/* BB%i */\n", b);
515 
    for (i = 0; i < f->bb[b].ninsn; i++)
516 
      print_insn_v (fo, f, b, i);
517 
    GEN ("\n");
518 
  }
519 
 
520 
  if (co) {
521 
    GEN ("\n/* Outputs */\n");
522 
    for (i = 0; i < MAX_REGS; i++)
523 
      if (f->lur[i] >= 0 && !f->saved_regs[i])
524 
        GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
525 
                        REF_I(f->lur[i]));
526 
  }
527 
 
528 
  if (nstores) {
529 
    int cur_store;
530 
    GEN ("\n/* Memory stores */\n");
531 
    GEN ("always @(s_stb");
532 
    for (i = 0; i < f->nmsched; i++)
533 
      if (f->mtype[i] & MT_STORE) {
534 
        char t[30];
535 
        unsigned long opt = f->INSN(f->msched[i]).opt[0];
536 
        if ((opt & ~OPT_DEST) != OPT_CONST) {
537 
          GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
538 
        }
539 
      }
540 
 
541 
    cur_store = 0;
542 
    GEN (")\nbegin\n");
543 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
544 
      char t[30];
545 
      GEN ("  %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
546 
                      print_op_v (f, t, f->msched[i], 0));
547 
      cur_store++;
548 
      //PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
549 
    }
550 
    GEN ("  else s_dat_o = 32'hx;\n");
551 
    GEN ("end\n");
552 
  }
553 
 
554 
  /* Generate load and store state machine */
555 
#if 0
556 
  GEN ("\n/* Load&store state machine */\n");
557 
  GEN ("always @(posedge clk or posedge rst)\n");
558 
  GEN ("  if (rst) begin\n");
559 
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
560 
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
561 
  GEN ("  end else begin\n");
562 
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
563 
    int cur = 0;
564 
    dep_list *dep = f->INSN(f->msched[i]).dep;
565 
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
566 
    GEN ("    if (");
567 
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
568 
    GEN (") begin\n");
569 
    print_turn_off_dep (fo, f, dep);
570 
    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
571 
    GEN ("    end\n");
572 
  }
573 
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
574 
  GEN ("  end\n");
575 
#endif
576 
 
577 
  /* Generate state generator machine */
578 
  for (j = 0; j < 2; j++) {
579 
    char c;
580 
    char *s;
581 
 
582 
    switch (j) {
583 
      case 0: c = 'l'; s = "Load"; break;
584 
      case 1: c = 's'; s = "Store"; break;
585 
      case 2: c = 'c'; s = "Calls"; break;
586 
    }
587 
    if (j == 0 && nloads
588 
     || j == 1 && nstores
589 
     || j == 2 && ncalls) {
590 
      int cur = 0;
591 
      char t[30];
592 
 
593 
      GEN ("\n/* %s state generator machine */\n", s);
594 
      GEN ("always @(");
595 
      for (i = 0; i < f->nmsched; i++) {
596 
        print_op_v (f, t, f->msched[i], 1);
597 
        GEN ("%s or ", t);
598 
      }
599 
      GEN ("bb_start_r");
600 
      if (nloads) GEN (" or l_end");
601 
      if (nstores) GEN (" or s_end");
602 
      GEN (")\n");
603 
      GEN ("begin\n  ");
604 
      cucdebug (1, "%s\n", s);
605 
      for (i = 0; i < f->nmsched; i++)
606 
        if (j == 0 && f->mtype[i] & MT_LOAD
607 
         || j == 1 && f->mtype[i] & MT_STORE
608 
         || j == 2 && f->mtype[i] & MT_CALL) {
609 
        cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
610 
        assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
611 
        GEN ("if (");
612 
        print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
613 
        GEN (") begin\n");
614 
        GEN ("    %c_req_o = 1'b1;\n", c);
615 
        GEN ("    %c_sel_o[3:0] = 4'b", c);
616 
        switch (f->mtype[i] & MT_WIDTH) {
617 
          case 1: GEN ("0001 << (%s & 32'h3);\n",
618 
                                  print_op_v (f, t, f->msched[i], 1)); break;
619 
          case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
620 
                                  print_op_v (f, t, f->msched[i], 1)); break;
621 
          case 4: GEN ("1111;\n"); break;
622 
          default: assert (0);
623 
        }
624 
        GEN ("    %c_linbrst_o = 1'b%i;\n", c,
625 
                      (f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
626 1308 phoenix 
        GEN ("    %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
627 1244 hpanther 
                      REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
628 
        GEN ("  end else ");
629 
      }
630 
      GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
631 
      GEN ("    %c_req_o = 1'b0;\n", c);
632 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
633 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
634 
      GEN ("    %c_adr_o = 32'hx;\n", c);
635 
      GEN ("  end else begin\n");
636 
      GEN ("    %c_req_o = 1'b0;\n", c);
637 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
638 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
639 
      GEN ("    %c_adr_o = 32'hx;\n", c);
640 
      GEN ("  end\n");
641 
      GEN ("end\n");
642 
    }
643 
  }
644 
 
645 
  if (ncalls) {
646 
    int cur_call = 0;
647 
    GEN ("\n/* Function calls state machine */\n");
648 
    GEN ("always @(posedge clk or posedge rst)\n");
649 
    GEN ("begin\n");
650 
    GEN ("  if (rst) begin\n");
651 
    GEN ("    f_stb <= #Tp %i'h0;\n", nstores);
652 
    for (i = 0; i < 6; i++) GEN ("    fr%i_o <= #Tp 32'h0;\n", i + 3);
653 
    if (log2_int(ncalls)) GEN ("    fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
654 
    GEN ("    fstart_o <= #Tp 1'b0;\n");
655 
    //GEN ("    f11_r <= #Tp 32'h0;\n");
656 
    GEN ("  end else begin\n");
657 
    cucdebug (1, "calls \n");
658 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
659 
      dep_list *dep = f->INSN(f->msched[i]).dep;
660 
      cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
661 
      assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
662 
      GEN ("    if (");
663 
      print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
664 
      GEN (") begin\n");
665 
      print_turn_off_dep (fo, f, dep);
666 
      GEN ("      f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
667 
      GEN ("      fstart_o <= #Tp 1'b1;\n");
668 
      if (log2_int (f->nfdeps))
669 
        GEN ("      fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps), func_index (f, f->msched[i]));
670 
 
671 
      for (j = 0; j < 6; j++)
672 
        GEN ("      fr%i_o <= #Tp t%x_%x;\n", j + 3,
673 
                       REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
674 
      GEN ("    end\n");
675 
    }
676 
    GEN ("    if (f_end[%i]) begin\n", ncalls - 1);
677 
    GEN ("      f_stb <= #Tp %i'h0;\n", ncalls);
678 
    GEN ("      f_start_o <= #Tp 1'b0;\n");
679 
    GEN ("    end\n");
680 
    GEN ("  end\n");
681 
    GEN ("end\n");
682 
  }
683 
 
684 
  GEN ("\n/* Basic blocks state machine */\n");
685 
  GEN ("always @(posedge clk or posedge rst)\n");
686 
  GEN ("begin\n");
687 
  GEN ("  if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
688 
  GEN ("  else if (end_o) begin\n");
689 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
690 
  for (i = 0; i < f->num_bb; i++) {
691 
    GEN ("  end else if (bb_start[%i]) begin\n", i);
692 
    GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
693 
  }
694 
  GEN ("  end else if (end_o) begin\n");
695 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
696 
  GEN ("  end\n");
697 
  GEN ("end\n");
698 
 
699 
  /* output footer */
700 
  GEN ("\nendmodule\n");
701 
 
702 
  fclose (fo);
703 
}
704 
 
705 
void generate_main (int nfuncs, cuc_func **f, char *filename)
706 
{
707 
  FILE *fo;
708 
  int i, j, nrf, first;
709 
  char tmp[256];
710 
  int ncallees[MAX_FUNCS];
711 
  int nl[MAX_FUNCS], ns[MAX_FUNCS];
712 
  int maxncallees = 0;
713 
  sprintf (tmp, "%s_top.v", filename);
714 
 
715 
  for (i = 0, nrf = 0; i < nfuncs; i++) {
716 
    nl[i] = ns[i] = 0;
717 
    ncallees[i] = 0;
718 
    if (f[i]) {
719 
      f[i]->tmp = nrf++;
720 
      for (j = 0; j < f[i]->nmsched; j++)
721 
        if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
722 
        else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
723 
      for (j = 0; j < f[i]->nfdeps; j++)
724 
        ncallees[f[i]->fdeps[j]->tmp]++;
725 
    }
726 
  }
727 
  if (!nrf) return;
728 
 
729 
  for (i = 0; i < nrf; i++)
730 
    if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
731 
 
732 
  log ("Generating verilog file \"%s\"\n", tmp);
733 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
734 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
735 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
736 
    exit (1);
737 
  }
738 
 
739 
  /* output header */
740 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
741 
  GEN ("   (C) 2002 Opencores */\n\n");
742 
  GEN ("/* Includes %i functions:", nrf);
743 
  for (i = 0; i < nfuncs; i++) if (f[i])
744 
    GEN ("\n%s", prof_func[i].name);
745 
  GEN (" */\n\n");
746 
 
747 
  GEN ("`include \"timescale.v\"\n\n");
748 
  GEN ("module %s (clk, rst,\n", filename);
749 
  GEN ("              /* Load and store master Wishbone ports */\n");
750 
  GEN ("              l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
751 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
752 
  GEN ("              s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
753 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
754 
  GEN ("              /* cuc interface */\n");
755 
  GEN ("              cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
756 
 
757 
  GEN ("parameter Tp = 1;\n");
758 
  GEN ("\n/* module ports */\n");
759 
  GEN ("input         clk, rst, cuc_stb_i, cuc_we_i;\n");
760 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
761 
  GEN ("output        l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
762 
  GEN ("reg           l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
763 
  GEN ("output        s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
764 
  GEN ("reg           s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
765 
  GEN ("output        cuc_rdy_o; /* Not registered ! */\n");
766 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
767 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
768 
  GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
769 
  GEN ("reg    [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
770 
  GEN ("input  [15:0] cuc_adr_i;\n");
771 
  GEN ("input  [31:0] l_dat_i, cuc_dat_i;\n\n");
772 
 
773 
  GEN ("wire   [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
774 
  GEN ("wire   [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
775 
  GEN ("wire   [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
776 
  GEN ("wire   [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
777 
  GEN ("reg    [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
778 
 
779 
  GEN ("assign i_selected = {\n");
780 
  for (i = 0; i < nrf; i++)
781 
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
782 
 
783 
  GEN ("assign i_first_reg = {\n");
784 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
785 
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
786 
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
787 
  }
788 
 
789 
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
790 
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
791 
 
792 
  GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
793 
  GEN ("assign i_start_bidok = {\n");
794 
  for (i = 0; i < nrf; i++)
795 
    GEN ("    i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
796 
  GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
797 
  GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
798 
 
799 
  GEN ("\nalways @(posedge clk or posedge rst)\n");
800 
  GEN ("begin\n");
801 
  GEN ("  if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
802 
  GEN ("  else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
803 
  GEN ("end\n");
804 
 
805 
 
806 
  /* Function specific data */
807 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
808 
    int ci = 0, co = 0;
809 
    int fn = f[i]->tmp;
810 
    GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
811 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
812 
      GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg    [31:0]" : ",", fn, j);
813 
      first = 0;
814 
      ci++;
815 
    }
816 
    if (ci) GEN (";\n");
817 
 
818 
    for (j = 0, first = 1; j < MAX_REGS; j++)
819 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
820 
        GEN ("%s i%i_r%io", first ? "/* outputs */\nwire   [31:0]" : ",", fn, j);
821 
        first = 0;
822 
        co++;
823 
      }
824 
    if (co) GEN (";\n");
825 
    GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
826 
 
827 
    GEN ("always @(posedge clk or posedge rst)\n");
828 
    GEN ("  if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
829 
    GEN ("  else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
830 
 
831 
    if (ci) {
832 
      GEN ("\n/* write register access */\n");
833 
      GEN ("always @(posedge clk or posedge rst)\n");
834 
      GEN ("begin\n");
835 
      GEN ("  if (rst) begin\n");
836 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
837 
        GEN ("    i%i_r%ii <= #Tp 32'h0;\n", fn, j);
838 
      GEN ("  end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
839 
      GEN ("    case (cuc_adr_i[5:0])\n");
840 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
841 
        GEN ("      %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
842 
      GEN ("    endcase\n");
843 
      GEN ("end\n");
844 
    }
845 
 
846 
    GEN ("\n");
847 
  }
848 
 
849 
  /* Generate machine for reading all function registers. Register read can be
850 
     delayed till function completion */
851 
  {
852 
    int co;
853 
    GEN ("/* read register access - data */\n");
854 
    GEN ("always @(posedge clk or posedge rst)\n");
855 
    GEN ("  if (rst) cuc_dat_o <= #Tp 32'h0;\n");
856 
    GEN ("  else if (cuc_stb_i && cuc_we_i) begin\n");
857 
    GEN ("    ");
858 
 
859 
    for (i = 0; i < nfuncs; i++) if (f[i]) {
860 
      co = 0;
861 
      for (j = 0; j < MAX_REGS; j++)
862 
        if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
863 
 
864 
      GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
865 
      if (co) {
866 
        first = 1;
867 
        GEN ("\n      case (cuc_adr_i[5:0])\n");
868 
        for (j = 0; j < MAX_REGS; j++)
869 
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
870 
            GEN ("        %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
871 
        GEN ("      endcase\n");
872 
      } else {
873 
        GEN ("      cuc_dat_o <= #Tp 32'hx;\n");
874 
      }
875 
      GEN ("    else ");
876 
    }
877 
    GEN ("cuc_dat_o <= #Tp 32'hx;\n");
878 
    GEN ("  end else cuc_dat_o <= #Tp 32'hx;\n");
879 
 
880 
    GEN ("\n/* read register access - acknowledge */\n");
881 
    GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
882 
  }
883 
 
884 
  /* Store/load Wishbone bridge */
885 
  for (j = 0; j < 2; j++) {
886 
    char t = j ? 's' : 'l';
887 
    GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
888 
    GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
889 
    GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
890 
    GEN ("reg       %ccyc_ip;\n\n", t);
891 
    GEN ("always @(posedge clk)\n");
892 
    GEN ("begin\n");
893 
    GEN ("  %c_we_o <= #Tp 1'b%i;\n", t, j);
894 
    GEN ("  %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
895 
    GEN ("  %c_stb_o <= #Tp |i_%c_req;\n", t, t);
896 
    GEN ("end\n");
897 
 
898 
    GEN ("\n/* highest bid */\n");
899 
    GEN ("always @(");
900 
    for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
901 
    GEN (")\n");
902 
    for (i = 0; i < nrf; i++) GEN ("  %sif (i_%c_req) %cm_bid = %i'h%x;\n",
903 
                    i ? "else " : "", t, t, log2_int (nrf) + 1, i);
904 
 
905 
    GEN ("\n/* selected transfer */\n");
906 
    GEN ("always @(posedge clk or posedge rst)\n");
907 
    GEN ("  if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
908 
    GEN ("  else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2_int (nrf) + 1);
909 
    GEN ("  else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
910 
 
911 
    GEN ("\n/* Cycle */\n");
912 
    GEN ("\nalways @(posedge clk or posedge rst)\n");
913 
    GEN ("  if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
914 
    GEN ("  else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
915 
    GEN ("  else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
916 
  }
917 
 
918 
  GEN ("\n/* Acknowledge */\n");
919 
  for (i = 0; i < nrf; i++) {
920 
    GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
921 
    GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
922 
  }
923 
 
924 
  GEN ("\n/* data, address selects and burst enables */\n");
925 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
926 
  for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
927 
  for (i = 0; i < nrf; i++) GEN ("wire [3:0]  i%i_s_sel, i%i_l_sel;\n", i, i);
928 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
929 
  GEN ("\nalways @(posedge clk)\n");
930 
  GEN ("begin\n");
931 
  GEN ("  s_dat_o <= #Tp ");
932 
  for (i = 0; i < nrf - 1; i++)
933 
    GEN ("\n    sm_bid == %i ? i%i_s_dat : ", i, i);
934 
  GEN ("i%i_s_dat;\n", nrf - 1);
935 
  GEN ("  s_adr_o <= #Tp ");
936 
  for (i = 0; i < nrf - 1; i++)
937 
    GEN ("\n    sm_bid == %i ? i%i_s_adr : ", i, i);
938 
  GEN ("i%i_s_adr;\n", nrf - 1);
939 
  GEN ("  s_sel_o <= #Tp ");
940 
  for (i = 0; i < nrf - 1; i++)
941 
    GEN ("\n    sm_bid == %i ? i%i_s_sel : ", i, i);
942 
  GEN ("i%i_s_sel;\n", nrf - 1);
943 
  GEN ("  s_linbrst_o <= #Tp ");
944 
  for (i = 0; i < nrf - 1; i++)
945 
    GEN ("\n    sm_bid == %i ? i%i_s_linbrst : ", i, i);
946 
  GEN ("i%i_s_linbrst;\n", nrf - 1);
947 
  GEN ("end\n\n");
948 
 
949 
  GEN ("always @(posedge clk)\n");
950 
  GEN ("begin\n");
951 
  GEN ("  l_adr_o <= #Tp ");
952 
  for (i = 0; i < nrf - 1; i++)
953 
    GEN ("\n    lm_bid == %i ? i%i_l_adr : ", i, i);
954 
  GEN ("i%i_l_adr;\n", nrf - 1);
955 
  GEN ("  l_sel_o <= #Tp ");
956 
  for (i = 0; i < nrf - 1; i++)
957 
    GEN ("\n    lm_bid == %i ? i%i_l_sel : ", i, i);
958 
  GEN ("i%i_l_sel;\n", nrf - 1);
959 
  GEN ("  l_linbrst_o <= #Tp ");
960 
  for (i = 0; i < nrf - 1; i++)
961 
    GEN ("\n    lm_bid == %i ? i%i_l_linbrst : ", i, i);
962 
  GEN ("i%i_l_linbrst;\n", nrf - 1);
963 
  GEN ("end\n\n");
964 
 
965 
  /* start/end signals */
966 
  GEN ("\n\n/* start/end signals */\n");
967 
  for (i = 0; i < nrf; i++) {
968 
    if (log2_int (maxncallees + 1))
969 
      GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
970 
        log2_int (maxncallees + 1), i, i, i, i, i);
971 
    else GEN ("wire i%i_current = 0;\n", i);
972 
  }
973 
  GEN ("\n");
974 
 
975 
  for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
976 
    if (log2_int (ncallees[i])) {
977 
      GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
978 
      GEN ("always @(start%i", f[i]->tmp);
979 
      for (j = 0, first = 1; j < f[i]->nfdeps; j++)
980 
        if (f[i]->fdeps[j]) GEN (", ");
981 
      GEN (")\n");
982 
      GEN ("begin !!!\n"); //TODO
983 
      GEN ("  \n");
984 
      GEN ("end\n");
985 
    }
986 
    GEN ("wire i%i_start = main_start[%i];\n", j, j);
987 
    j++;
988 
  }
989 
  GEN ("\n");
990 
 
991 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
992 
    int nf = f[i]->tmp;
993 
    GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
994 
    GEN ("  .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
995 
                    nf, nf, nf);
996 
    GEN ("  .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
997 
                    nf, nf, nf);
998 
    GEN ("  .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
999 
                    nf, nf, nf);
1000 
    GEN ("  .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
1001 
                    nf, nf, nf);
1002 
    GEN ("  ");
1003 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
1004 
      GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
1005 
 
1006 
    if (first) GEN ("\n  ");
1007 
    for (j = 0, first = 1; j < MAX_REGS; j++)
1008 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1009 
        GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
1010 
    if (first) GEN ("\n  ");
1011 
    if (f[i]->nfdeps) {
1012 
      GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
1013 
      GEN ("  .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
1014 
      GEN ("  .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n  ");
1015 
    }
1016 
    GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
1017 
  }
1018 
 
1019 
  /* output footer */
1020 
  GEN ("\nendmodule\n");
1021 
 
1022 
  fclose (fo);
1023 
}
1024 
 

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