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[/] [or1k/] [tags/] [nog_patch_69/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1765

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Line No. Rev Author Line
1 1452 nogj 
/* op.c -- Micro operations for the recompiler
2 
   Copyright (C) 2005 György `nog' Jeney, nog@sdf.lonestar.org
3 
 
4 
This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
This program is free software; you can redistribute it and/or modify
7 
it under the terms of the GNU General Public License as published by
8 
the Free Software Foundation; either version 2 of the License, or
9 
(at your option) any later version.
10 
 
11 
This program is distributed in the hope that it will be useful,
12 
but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
GNU General Public License for more details.
15 
 
16 
You should have received a copy of the GNU General Public License
17 
along with this program; if not, write to the Free Software
18 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
 
21 
#include <stdio.h>
22 
#include <stdint.h>
23 
#include <stdlib.h>
24 
 
25 
#include "config.h"
26 
 
27 
#ifdef HAVE_INTTYPES_H
28 
#include <inttypes.h>
29 
#endif
30 
 
31 
#include "port.h"
32 
#include "arch.h"
33 
#include "spr_defs.h"
34 
#include "opcode/or32.h"
35 
#include "sim-config.h"
36 
#include "except.h"
37 
#include "abstract.h"
38 
#include "execute.h"
39 
#include "sprs.h"
40 
#include "sched.h"
41 
 
42 
#include "op_support.h"
43 
 
44 
#include "i386_regs.h"
45 
 
46 
#include "dyn_rec.h"
47 
 
48 
/* This must be here since the function in op_i386.h use this variable */
49 
register struct cpu_state *env asm(CPU_STATE_REG);
50 
 
51 
#include "op_i386.h"
52 
 
53 
/* FIXME: Move this */
54 
void analysis (struct iqueue_entry *current);
55 
 
56 
/* FIXME: Move this */
57 
#define PAGE_LEN 8192
58 
 
59 
/*
60 
 * WARNING: Before going of and wildly editing everything in the file remember
61 
 * the following about its contents:
62 
 * 1) The `functions' don't EVER return.  In otherwords haveing return state-
63 
 *    ments _anywere_ in this file is likely not to work.  This is because
64 
 *    dyngen just strips away the ret from the end of the function and just uses
65 
 *    the function `body'.  If a ret statement is executed _anyware_ inside the
66 
 *    dynamicly generated code, then it is undefined were we shall jump to.
67 
 * 2) Because of 1), try not to have overly complicated functions.  In too
68 
 *    complicated functions, gcc may decide to generate premature `exits'.  This
69 
 *    is what passing the -fno-reorder-blocks command line switch to gcc helps
70 
 *    with.  This is ofcourse not desired and is rather flaky as we don't (and
71 
 *    can't) control the kind of code that gcc generates: It may work for one
72 
 *    and break for another.  The less branches there are the less likely it is
73 
 *    that a premature return shall occur.
74 
 * 3) If gcc decides that it is going to be a basterd then it will optimise a
75 
 *    very simple condition (if/switch) with a premature exit.  But gcc can't
76 
 *    fuck ME over!  Just stick a FORCE_RET; at the END of the offending
77 
 *    function.
78 
 * 4) All operations must start with `op_'.  dyngen ignores all other functions.
79 
 * 5) Local variables are depriciated: They hinder performance.
80 
 * 6) Function calls are expensive as the stack has to be shifted (twice).
81 
 */
82 
 
83 
/*#define __or_dynop __attribute__((noreturn))*/
84 
#define __or_dynop
85 
 
86 
/* Temporaries to hold the (simulated) registers in */
87 
register uint32_t t0 asm(T0_REG);
88 
register uint32_t t1 asm(T1_REG);
89 
register uint32_t t2 asm(T2_REG);
90 
 
91 
#define OP_PARAM1 ((uorreg_t)(&__op_param1))
92 
#define OP_PARAM2 ((uorreg_t)(&__op_param2))
93 
#define OP_PARAM3 ((uorreg_t)(&__op_param3))
94 
 
95 
extern uorreg_t __op_param1;
96 
extern uorreg_t __op_param2;
97 
extern uorreg_t __op_param3;
98 
 
99 
#define xglue(x, y) x ## y
100 
#define glue(x, y) xglue(x, y)
101 
 
102 
/* Helper function.  Whenever we escape the recompiled code and there is a
103 
 * potential that an exception may happen this function must be called */
104 
static inline void save_t_temporary(void)
105 
{
106 
  env->t0 = t0;
107 
  env->t1 = t1;
108 
  env->t2 = t2;
109 
}
110 
 
111 
/* Wrapper around do_scheduler.  This is needed because op_do_sched must be as
112 
 * small as possible. */
113 
void do_sched_wrap(void)
114 
{
115 
  save_t_temporary();
116 
  upd_sim_cycles();
117 
  do_scheduler();
118 
}
119 
 
120 
/* Helper function.  Hopefully it will get inlined */
121 
__or_dynop void op_t0_imm(void)
122 
{
123 
  t0 = OP_PARAM1;
124 
}
125 
 
126 
__or_dynop void op_t1_imm(void)
127 
{
128 
  t1 = OP_PARAM1;
129 
}
130 
 
131 
__or_dynop void op_t2_imm(void)
132 
{
133 
  t2 = OP_PARAM1;
134 
}
135 
 
136 
__or_dynop void op_clear_t0(void)
137 
{
138 
  t0 = 0;
139 
}
140 
 
141 
__or_dynop void op_clear_t1(void)
142 
{
143 
  t1 = 0;
144 
}
145 
 
146 
__or_dynop void op_clear_t2(void)
147 
{
148 
  t2 = 0;
149 
}
150 
 
151 
__or_dynop void op_move_t0_t1(void)
152 
{
153 
  t0 = t1;
154 
}
155 
 
156 
__or_dynop void op_move_t0_t2(void)
157 
{
158 
  t0 = t2;
159 
}
160 
 
161 
__or_dynop void op_move_t1_t0(void)
162 
{
163 
  t1 = t0;
164 
}
165 
 
166 
__or_dynop void op_move_t1_t2(void)
167 
{
168 
  t1 = t2;
169 
}
170 
 
171 
__or_dynop void op_move_t2_t0(void)
172 
{
173 
  t2 = t0;
174 
}
175 
 
176 
__or_dynop void op_move_t2_t1(void)
177 
{
178 
  t2 = t1;
179 
}
180 
 
181 
__or_dynop void op_set_pc_delay_t0(void)
182 
{
183 
  env->pc_delay = t0;
184 
  env->delay_insn = 1;
185 
}
186 
 
187 
__or_dynop void op_set_pc_delay_t1(void)
188 
{
189 
  env->pc_delay = t1;
190 
  env->delay_insn = 1;
191 
}
192 
 
193 
__or_dynop void op_set_pc_delay_t2(void)
194 
{
195 
  env->pc_delay = t2;
196 
  env->delay_insn = 1;
197 
}
198 
 
199 
__or_dynop void op_set_pc_delay_imm(void)
200 
{
201 
  env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
202 
  env->delay_insn = 1;
203 
}
204 
 
205 
__or_dynop void op_set_pc_delay_pc(void)
206 
{
207 
  env->pc_delay = get_pc();
208 
  env->delay_insn = 1;
209 
}
210 
 
211 
__or_dynop void op_clear_pc_delay(void)
212 
{
213 
  env->pc_delay = 0;
214 
  env->delay_insn = 1;
215 
}
216 
 
217 
__or_dynop void op_do_jump(void)
218 
{
219 
  do_jump(env->pc_delay);
220 
}
221 
 
222 
/* Only used to handle branch instruction ie. j.bf and j.bnf */
223 
__or_dynop void op_do_jump_check(void)
224 
{
225 
  if(env->delay_insn) {
226 
    env->delay_insn = 0;
227 
    do_jump(env->pc_delay);
228 
  }
229 
}
230 
 
231 
/* Only used to jump out to the next page */
232 
__or_dynop void op_do_jump_pc(void)
233 
{
234 
  do_jump(get_pc());
235 
}
236 
 
237 
__or_dynop void op_clear_delay_insn(void)
238 
{
239 
  env->delay_insn = 0;
240 
}
241 
 
242 
__or_dynop void op_jmp_imm(void)
243 
{
244 
  env->ts_current = 0;
245 
  set_pc(env->pc_delay);
246 
  OP_JUMP(OP_PARAM1);
247 
}
248 
 
249 
__or_dynop void op_jmp_imm_check(void)
250 
{
251 
  if(env->delay_insn) {
252 
    env->ts_current = 0;
253 
    env->delay_insn = 0;
254 
    set_pc(env->pc_delay);
255 
    OP_JUMP(OP_PARAM1);
256 
  }
257 
}
258 
 
259 
__or_dynop void op_set_flag(void)
260 
{
261 
  env->sprs[SPR_SR] |= SPR_SR_F;
262 
}
263 
 
264 
__or_dynop void op_clear_flag(void)
265 
{
266 
  env->sprs[SPR_SR] &= ~SPR_SR_F;
267 
}
268 
 
269 
__or_dynop void op_check_flag(void)
270 
{
271 
  if(env->sprs[SPR_SR] & SPR_SR_F) {
272 
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
273 
    env->delay_insn = 1;
274 
  }
275 
}
276 
 
277 
__or_dynop void op_check_not_flag(void)
278 
{
279 
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
280 
    env->pc_delay = get_pc() + (orreg_t)OP_PARAM1;
281 
    env->delay_insn = 1;
282 
  }
283 
}
284 
 
285 
__or_dynop void op_set_ts_current(void)
286 
{
287 
  env->ts_current = 1;
288 
}
289 
 
290 
__or_dynop void op_set_pc_preemt(void)
291 
{
292 
  env->ts_current = 1;
293 
  env->sprs[SPR_PPC] = get_pc();
294 
  set_pc(env->pc_delay);
295 
}
296 
 
297 
__or_dynop void op_set_pc_preemt_check(void)
298 
{
299 
  if(env->delay_insn) {
300 
    env->ts_current = 1;
301 
    env->sprs[SPR_PPC] = get_pc();
302 
    set_pc(env->pc_delay);
303 
  }
304 
}
305 
 
306 
__or_dynop void op_nop_exit(void)
307 
{
308 
  upd_sim_cycles();
309 
  save_t_temporary();
310 
  op_support_nop_exit();
311 
  FORCE_RET;
312 
}
313 
 
314 
__or_dynop void op_nop_reset(void)
315 
{
316 
  upd_sim_cycles();
317 
  op_support_nop_reset();
318 
  handle_except(EXCEPT_RESET);
319 
}
320 
 
321 
__or_dynop void op_nop_printf(void)
322 
{
323 
  save_t_temporary();
324 
  upd_sim_cycles();
325 
  op_support_nop_printf();
326 
  FORCE_RET;
327 
}
328 
 
329 
__or_dynop void op_nop_report(void)
330 
{
331 
  save_t_temporary();
332 
  upd_sim_cycles();
333 
  op_support_nop_report();
334 
  FORCE_RET;
335 
}
336 
 
337 
__or_dynop void op_nop_report_imm(void)
338 
{
339 
  save_t_temporary();
340 
  upd_sim_cycles();
341 
  op_support_nop_report_imm(OP_PARAM1);
342 
}
343 
 
344 
__or_dynop void op_check_null_except_t0_delay(void)
345 
{
346 
  if(!t0) {
347 
    /* Do exception */
348 
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
349 
    env->delay_insn = 0;
350 
    handle_except(EXCEPT_ILLEGAL);
351 
  }
352 
}
353 
 
354 
 
355 
__or_dynop void op_check_null_except_t0(void)
356 
{
357 
  if(!t0) {
358 
    /* Do exception */
359 
    env->sprs[SPR_EEAR_BASE] = get_pc();
360 
    handle_except(EXCEPT_ILLEGAL);
361 
  }
362 
}
363 
 
364 
__or_dynop void op_check_null_except_t1_delay(void)
365 
{
366 
  if(!t1) {
367 
    /* Do exception */
368 
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
369 
    env->delay_insn = 0;
370 
    handle_except(EXCEPT_ILLEGAL);
371 
  }
372 
}
373 
 
374 
 
375 
__or_dynop void op_check_null_except_t1(void)
376 
{
377 
  if(!t1) {
378 
    /* Do exception */
379 
    env->sprs[SPR_EEAR_BASE] = get_pc();
380 
    handle_except(EXCEPT_ILLEGAL);
381 
  }
382 
}
383 
 
384 
__or_dynop void op_check_null_except_t2_delay(void)
385 
{
386 
  if(!t2) {
387 
    /* Do exception */
388 
    env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
389 
    env->delay_insn = 0;
390 
    handle_except(EXCEPT_ILLEGAL);
391 
  }
392 
}
393 
 
394 
__or_dynop void op_check_null_except_t2(void)
395 
{
396 
  if(!t2) {
397 
    /* Do exception */
398 
    env->sprs[SPR_EEAR_BASE] = get_pc();
399 
    handle_except(EXCEPT_ILLEGAL);
400 
  }
401 
}
402 
 
403 
__or_dynop void op_analysis(void)
404 
{
405 
  env->iqueue.insn_index = OP_PARAM1;
406 
  env->iqueue.insn = OP_PARAM2;
407 
  env->iqueue.insn_addr = get_pc();
408 
  upd_sim_cycles();
409 
  runtime.cpu.instructions++;
410 
  analysis(&env->iqueue);
411 
  FORCE_RET;
412 
}
413 
 
414 
#define OP_EXTRA
415 
 
416 
#define OP /
417 
#define OP_CAST(T) (orreg_t)T
418 
#define OP_NAME div
419 
#include "op_arith_op.h"
420 
#undef OP_NAME
421 
#undef OP_CAST
422 
#undef OP
423 
 
424 
#define OP /
425 
#define OP_CAST(T) T
426 
#define OP_NAME divu
427 
#include "op_arith_op.h"
428 
#undef OP_NAME
429 
#undef OP_CAST
430 
#undef OP
431 
 
432 
#define OP *
433 
#define OP_CAST(T) T
434 
#define OP_NAME mulu
435 
#include "op_arith_op.h"
436 
#undef OP_NAME
437 
#undef OP_CAST
438 
#undef OP
439 
 
440 
#define OP -
441 
#define OP_CAST(T) (orreg_t)T
442 
#define OP_NAME sub
443 
#include "op_arith_op.h"
444 
#undef OP_NAME
445 
#undef OP_CAST
446 
#undef OP
447 
 
448 
#undef OP_EXTRA
449 
 
450 
#define OP_HAS_IMM
451 
 
452 
#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)
453 
#define OP +
454 
#define OP_CAST(T) (orreg_t)T
455 
#define OP_NAME addc
456 
#include "op_arith_op.h"
457 
#undef OP_NAME
458 
#undef OP_CAST
459 
#undef OP
460 
 
461 
#undef OP_EXTRA
462 
#define OP_EXTRA
463 
 
464 
#define OP +
465 
#define OP_CAST(T) (orreg_t)T
466 
#define OP_NAME add
467 
#include "op_arith_op.h"
468 
#undef OP_NAME
469 
#undef OP_CAST
470 
#undef OP
471 
 
472 
#define OP &
473 
#define OP_CAST(T) T
474 
#define OP_NAME and
475 
#include "op_arith_op.h"
476 
#undef OP_NAME
477 
#undef OP_CAST
478 
#undef OP
479 
 
480 
#define OP *
481 
#define OP_CAST(T) (orreg_t)T
482 
#define OP_NAME mul
483 
#include "op_arith_op.h"
484 
#undef OP_NAME
485 
#undef OP_CAST
486 
#undef OP
487 
 
488 
#define OP |
489 
#define OP_CAST(T) T
490 
#define OP_NAME or
491 
#include "op_arith_op.h"
492 
#undef OP_NAME
493 
#undef OP_CAST
494 
#undef OP
495 
 
496 
#define OP <<
497 
#define OP_CAST(T) T
498 
#define OP_NAME sll
499 
#include "op_arith_op.h"
500 
#undef OP_NAME
501 
#undef OP_CAST
502 
#undef OP
503 
 
504 
#define OP >>
505 
#define OP_CAST(T) (orreg_t)T
506 
#define OP_NAME sra
507 
#include "op_arith_op.h"
508 
#undef OP_NAME
509 
#undef OP_CAST
510 
#undef OP
511 
 
512 
#define OP >>
513 
#define OP_CAST(T) T
514 
#define OP_NAME srl
515 
#include "op_arith_op.h"
516 
#undef OP_NAME
517 
#undef OP_CAST
518 
#undef OP
519 
 
520 
#define OP ^
521 
#define OP_CAST(T) T
522 
#define OP_NAME xor
523 
#include "op_arith_op.h"
524 
#undef OP_NAME
525 
#undef OP_CAST
526 
#undef OP
527 
 
528 
#undef OP_EXTRA
529 
#undef OP_HAS_IMM
530 
 
531 
#define EXT_NAME extbs
532 
#define EXT_TYPE int8_t
533 
#define EXT_CAST (orreg_t)
534 
#include "op_extend_op.h"
535 
#undef EXT_CAST
536 
#undef EXT_TYPE
537 
#undef EXT_NAME
538 
 
539 
#define EXT_NAME extbz
540 
#define EXT_TYPE uint8_t
541 
#define EXT_CAST (uorreg_t)
542 
#include "op_extend_op.h"
543 
#undef EXT_CAST
544 
#undef EXT_TYPE
545 
#undef EXT_NAME
546 
 
547 
#define EXT_NAME exths
548 
#define EXT_TYPE int16_t
549 
#define EXT_CAST (orreg_t)
550 
#include "op_extend_op.h"
551 
#undef EXT_CAST
552 
#undef EXT_TYPE
553 
#undef EXT_NAME
554 
 
555 
#define EXT_NAME exthz
556 
#define EXT_TYPE uint16_t
557 
#define EXT_CAST (uorreg_t)
558 
#include "op_extend_op.h"
559 
#undef EXT_CAST
560 
#undef EXT_TYPE
561 
#undef EXT_NAME
562 
 
563 
#define COMP ==
564 
#define COMP_NAME sfeq
565 
#define COMP_CAST(t) t
566 
#include "op_comp_op.h"
567 
#undef COMP_CAST
568 
#undef COMP_NAME
569 
#undef COMP
570 
 
571 
#define COMP !=
572 
#define COMP_NAME sfne
573 
#define COMP_CAST(t) t
574 
#include "op_comp_op.h"
575 
#undef COMP_CAST
576 
#undef COMP_NAME
577 
#undef COMP
578 
 
579 
#define COMP >
580 
#define COMP_NAME sfgtu
581 
#define COMP_CAST(t) t
582 
#include "op_comp_op.h"
583 
#undef COMP_CAST
584 
#undef COMP_NAME
585 
#undef COMP
586 
 
587 
#define COMP >=
588 
#define COMP_NAME sfgeu
589 
#define COMP_CAST(t) t
590 
#include "op_comp_op.h"
591 
#undef COMP_CAST
592 
#undef COMP_NAME
593 
#undef COMP
594 
 
595 
#define COMP <
596 
#define COMP_NAME sfltu
597 
#define COMP_CAST(t) t
598 
#include "op_comp_op.h"
599 
#undef COMP_CAST
600 
#undef COMP_NAME
601 
#undef COMP
602 
 
603 
#define COMP <=
604 
#define COMP_NAME sfleu
605 
#define COMP_CAST(t) t
606 
#include "op_comp_op.h"
607 
#undef COMP_CAST
608 
#undef COMP_NAME
609 
#undef COMP
610 
 
611 
#define COMP >
612 
#define COMP_NAME sfgts
613 
#define COMP_CAST(t) (orreg_t)t
614 
#include "op_comp_op.h"
615 
#undef COMP_CAST
616 
#undef COMP_NAME
617 
#undef COMP
618 
 
619 
#define COMP >=
620 
#define COMP_NAME sfges
621 
#define COMP_CAST(t) (orreg_t)t
622 
#include "op_comp_op.h"
623 
#undef COMP_CAST
624 
#undef COMP_NAME
625 
#undef COMP
626 
 
627 
#define COMP <
628 
#define COMP_NAME sflts
629 
#define COMP_CAST(t) (orreg_t)t
630 
#include "op_comp_op.h"
631 
#undef COMP_CAST
632 
#undef COMP_NAME
633 
#undef COMP
634 
 
635 
#define COMP <=
636 
#define COMP_NAME sfles
637 
#define COMP_CAST(t) (orreg_t)t
638 
#include "op_comp_op.h"
639 
#undef COMP_CAST
640 
#undef COMP_NAME
641 
#undef COMP
642 
 
643 
#define REG 1
644 
#include "op_t_reg_mov_op.h"
645 
#undef REG
646 
 
647 
#define REG 2
648 
#include "op_t_reg_mov_op.h"
649 
#undef REG
650 
 
651 
#define REG 3
652 
#include "op_t_reg_mov_op.h"
653 
#undef REG
654 
 
655 
#define REG 4
656 
#include "op_t_reg_mov_op.h"
657 
#undef REG
658 
 
659 
#define REG 5
660 
#include "op_t_reg_mov_op.h"
661 
#undef REG
662 
 
663 
#define REG 6
664 
#include "op_t_reg_mov_op.h"
665 
#undef REG
666 
 
667 
#define REG 7
668 
#include "op_t_reg_mov_op.h"
669 
#undef REG
670 
 
671 
#define REG 8
672 
#include "op_t_reg_mov_op.h"
673 
#undef REG
674 
 
675 
#define REG 9
676 
#include "op_t_reg_mov_op.h"
677 
#undef REG
678 
 
679 
#define REG 10
680 
#include "op_t_reg_mov_op.h"
681 
#undef REG
682 
 
683 
#define REG 11
684 
#include "op_t_reg_mov_op.h"
685 
#undef REG
686 
 
687 
#define REG 12
688 
#include "op_t_reg_mov_op.h"
689 
#undef REG
690 
 
691 
#define REG 13
692 
#include "op_t_reg_mov_op.h"
693 
#undef REG
694 
 
695 
#define REG 14
696 
#include "op_t_reg_mov_op.h"
697 
#undef REG
698 
 
699 
#define REG 15
700 
#include "op_t_reg_mov_op.h"
701 
#undef REG
702 
 
703 
#define REG 16
704 
#include "op_t_reg_mov_op.h"
705 
#undef REG
706 
 
707 
#define REG 17
708 
#include "op_t_reg_mov_op.h"
709 
#undef REG
710 
 
711 
#define REG 18
712 
#include "op_t_reg_mov_op.h"
713 
#undef REG
714 
 
715 
#define REG 19
716 
#include "op_t_reg_mov_op.h"
717 
#undef REG
718 
 
719 
#define REG 20
720 
#include "op_t_reg_mov_op.h"
721 
#undef REG
722 
 
723 
#define REG 21
724 
#include "op_t_reg_mov_op.h"
725 
#undef REG
726 
 
727 
#define REG 22
728 
#include "op_t_reg_mov_op.h"
729 
#undef REG
730 
 
731 
#define REG 23
732 
#include "op_t_reg_mov_op.h"
733 
#undef REG
734 
 
735 
#define REG 24
736 
#include "op_t_reg_mov_op.h"
737 
#undef REG
738 
 
739 
#define REG 25
740 
#include "op_t_reg_mov_op.h"
741 
#undef REG
742 
 
743 
#define REG 26
744 
#include "op_t_reg_mov_op.h"
745 
#undef REG
746 
 
747 
#define REG 27
748 
#include "op_t_reg_mov_op.h"
749 
#undef REG
750 
 
751 
#define REG 28
752 
#include "op_t_reg_mov_op.h"
753 
#undef REG
754 
 
755 
#define REG 29
756 
#include "op_t_reg_mov_op.h"
757 
#undef REG
758 
 
759 
#define REG 30
760 
#include "op_t_reg_mov_op.h"
761 
#undef REG
762 
 
763 
#define REG 31
764 
#include "op_t_reg_mov_op.h"
765 
#undef REG
766 
 
767 
#define DST_T t0
768 
#define SRC_T t0
769 
#include "op_ff1_op.h"
770 
#undef SRC_T
771 
 
772 
#define SRC_T t1
773 
#include "op_ff1_op.h"
774 
#undef SRC_T
775 
 
776 
#define SRC_T t2
777 
#include "op_ff1_op.h"
778 
#undef SRC_T
779 
#undef DST_T
780 
 
781 
#define DST_T t1
782 
#define SRC_T t0
783 
#include "op_ff1_op.h"
784 
#undef SRC_T
785 
 
786 
#define SRC_T t1
787 
#include "op_ff1_op.h"
788 
#undef SRC_T
789 
 
790 
#define SRC_T t2
791 
#include "op_ff1_op.h"
792 
#undef SRC_T
793 
#undef DST_T
794 
 
795 
#define DST_T t2
796 
#define SRC_T t0
797 
#include "op_ff1_op.h"
798 
#undef SRC_T
799 
 
800 
#define SRC_T t1
801 
#include "op_ff1_op.h"
802 
#undef SRC_T
803 
 
804 
#define SRC_T t2
805 
#include "op_ff1_op.h"
806 
#undef SRC_T
807 
#undef DST_T
808 
 
809 
#define SPR_T_NAME SPR_T
810 
#define GPR_T_NAME GPR_T
811 
 
812 
#define SPR_T t0
813 
#define GPR_T t0
814 
#include "op_mftspr_op.h"
815 
#undef GPR_T
816 
 
817 
#define GPR_T t1
818 
#include "op_mftspr_op.h"
819 
#undef GPR_T
820 
 
821 
#define GPR_T t2
822 
#include "op_mftspr_op.h"
823 
#undef GPR_T
824 
#undef SPR_T
825 
 
826 
#define SPR_T t1
827 
#define GPR_T t0
828 
#include "op_mftspr_op.h"
829 
#undef GPR_T
830 
 
831 
#define GPR_T t1
832 
#include "op_mftspr_op.h"
833 
#undef GPR_T
834 
 
835 
#define GPR_T t2
836 
#include "op_mftspr_op.h"
837 
#undef GPR_T
838 
#undef SPR_T
839 
 
840 
#define SPR_T t2
841 
#define GPR_T t0
842 
#include "op_mftspr_op.h"
843 
#undef GPR_T
844 
 
845 
#define GPR_T t1
846 
#include "op_mftspr_op.h"
847 
#undef GPR_T
848 
 
849 
#define GPR_T t2
850 
#include "op_mftspr_op.h"
851 
#undef GPR_T
852 
#undef SPR_T
853 
 
854 
#undef GPR_T_NAME
855 
#undef SPR_T_NAME
856 
 
857 
#define SPR_T_NAME imm
858 
#define GPR_T_NAME GPR_T
859 
 
860 
#define SPR_T 0
861 
 
862 
#define GPR_T t0
863 
#include "op_mftspr_op.h"
864 
#undef GPR_T
865 
 
866 
#define GPR_T t1
867 
#include "op_mftspr_op.h"
868 
#undef GPR_T
869 
 
870 
#define GPR_T t2
871 
#include "op_mftspr_op.h"
872 
#undef GPR_T
873 
#undef SPR_T
874 
 
875 
#undef SPR_T_NAME
876 
#undef GPR_T_NAME
877 
 
878 
#define ONLY_MTSPR
879 
#define SPR_T_NAME SPR_T
880 
#define GPR_T_NAME clear
881 
 
882 
#define GPR_T 0
883 
 
884 
#define SPR_T t0
885 
#include "op_mftspr_op.h"
886 
#undef SPR_T
887 
 
888 
#define SPR_T t1
889 
#include "op_mftspr_op.h"
890 
#undef SPR_T
891 
 
892 
#define SPR_T t2
893 
#include "op_mftspr_op.h"
894 
#undef SPR_T
895 
 
896 
#undef GPR_T
897 
 
898 
#undef SPR_T_NAME
899 
#undef GPR_T_NAME
900 
 
901 
#define SPR_T_NAME imm
902 
#define GPR_T_NAME clear
903 
#define GPR_T 0
904 
#define SPR_T 0
905 
#include "op_mftspr_op.h"
906 
#undef SPR_T
907 
#undef GPR_T
908 
#undef GPR_T_NAME
909 
#undef SPR_T_NAME
910 
 
911 
#undef ONLY_MTSPR
912 
 
913 
#define OP +=
914 
#define OP_NAME mac
915 
#include "op_mac_op.h"
916 
#undef OP_NAME
917 
#undef OP
918 
 
919 
#define OP -=
920 
#define OP_NAME msb
921 
#include "op_mac_op.h"
922 
#undef OP_NAME
923 
#undef OP
924 
 
925 
#define LS_OP_NAME lbz
926 
#define LS_OP_CAST
927 
#define LS_OP_FUNC eval_mem8
928 
#include "op_lwhb_op.h"
929 
#undef LS_OP_FUNC
930 
#undef LS_OP_CAST
931 
#undef LS_OP_NAME
932 
 
933 
#define LS_OP_NAME lbs
934 
#define LS_OP_CAST (int8_t)
935 
#define LS_OP_FUNC eval_mem8
936 
#include "op_lwhb_op.h"
937 
#undef LS_OP_FUNC
938 
#undef LS_OP_CAST
939 
#undef LS_OP_NAME
940 
 
941 
#define LS_OP_NAME lhz
942 
#define LS_OP_CAST
943 
#define LS_OP_FUNC eval_mem16
944 
#include "op_lwhb_op.h"
945 
#undef LS_OP_FUNC
946 
#undef LS_OP_CAST
947 
#undef LS_OP_NAME
948 
 
949 
#define LS_OP_NAME lhs
950 
#define LS_OP_CAST (int16_t)
951 
#define LS_OP_FUNC eval_mem16
952 
#include "op_lwhb_op.h"
953 
#undef LS_OP_FUNC
954 
#undef LS_OP_CAST
955 
#undef LS_OP_NAME
956 
 
957 
#define LS_OP_NAME lwz
958 
#define LS_OP_CAST
959 
#define LS_OP_FUNC eval_mem32
960 
#include "op_lwhb_op.h"
961 
#undef LS_OP_FUNC
962 
#undef LS_OP_CAST
963 
#undef LS_OP_NAME
964 
 
965 
#define LS_OP_NAME lws
966 
#define LS_OP_CAST (int32_t)
967 
#define LS_OP_FUNC eval_mem32
968 
#include "op_lwhb_op.h"
969 
#undef LS_OP_FUNC
970 
#undef LS_OP_CAST
971 
#undef LS_OP_NAME
972 
 
973 
#define S_OP_NAME sb
974 
#define S_FUNC set_mem8
975 
#include "op_swhb_op.h"
976 
#undef S_FUNC
977 
#undef S_OP_NAME
978 
 
979 
#define S_OP_NAME sh
980 
#define S_FUNC set_mem16
981 
#include "op_swhb_op.h"
982 
#undef S_FUNC
983 
#undef S_OP_NAME
984 
 
985 
#define S_OP_NAME sw
986 
#define S_FUNC set_mem32
987 
#include "op_swhb_op.h"
988 
#undef S_FUNC
989 
#undef S_OP_NAME
990 
 
991 
__or_dynop void op_join_mem_cycles(void)
992 
{
993 
  join_mem_cycles();
994 
}
995 
 
996 
__or_dynop void op_store_link_addr_gpr(void)
997 
{
998 
  env->reg[LINK_REGNO] = get_pc() + 8;
999 
}
1000 
 
1001 
__or_dynop void op_set_rfe_pc(void)
1002 
{
1003 
  set_pc(env->sprs[SPR_EPCR_BASE] - 4);
1004 
}
1005 
 
1006 
__or_dynop void op_prep_rfe(void)
1007 
{
1008 
  env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
1009 
  env->sprs[SPR_PPC] = get_pc();
1010 
}
1011 
 
1012 
__or_dynop void op_rfe(void)
1013 
{
1014 
  do_rfe();
1015 
  FORCE_RET;
1016 
}
1017 
 
1018 
static inline void prep_except(oraddr_t epcr_base)
1019 
{
1020 
  env->sprs[SPR_EPCR_BASE] = epcr_base;
1021 
 
1022 
  env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR];
1023 
 
1024 
  /* Address translation is always disabled when starting exception. */
1025 
  env->sprs[SPR_SR] &= ~SPR_SR_DME;
1026 
  env->sprs[SPR_SR] &= ~SPR_SR_IME;
1027 
 
1028 
  env->sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */
1029 
 
1030 
  env->sprs[SPR_SR] |= SPR_SR_SM;     /* SUPV mode */
1031 
  env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);    /* Disable interrupts. */
1032 
}
1033 
 
1034 
__or_dynop void op_set_except_pc(void)
1035 
{
1036 
  set_pc(OP_PARAM1);
1037 
}
1038 
 
1039 
/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
1040 
 * Therefore the pc will point to the instruction after the l.sys or l.trap
1041 
 * instruction */
1042 
__or_dynop void op_prep_sys_delay(void)
1043 
{
1044 
  env->delay_insn = 0;
1045 
  prep_except(get_pc() - 4);
1046 
}
1047 
 
1048 
__or_dynop void op_prep_sys(void)
1049 
{
1050 
  prep_except(get_pc() + 4);
1051 
}
1052 
 
1053 
__or_dynop void op_prep_trap_delay(void)
1054 
{
1055 
  env->delay_insn = 0;
1056 
  prep_except(get_pc() - 4);
1057 
}
1058 
 
1059 
__or_dynop void op_prep_trap(void)
1060 
{
1061 
  prep_except(get_pc());
1062 
}
1063 
 
1064 
__or_dynop void op_do_except(void)
1065 
{
1066 
  handle_except(OP_PARAM1);
1067 
}
1068 
 
1069 
/* FIXME: This `instruction' should be split up like the l.trap and l.sys
1070 
 * instructions are done */
1071 
__or_dynop void op_illegal_delay(void)
1072 
{
1073 
  env->delay_insn = 0;
1074 
  env->sprs[SPR_EEAR_BASE] = get_pc() - 4;
1075 
  handle_except(EXCEPT_ILLEGAL);
1076 
}
1077 
 
1078 
__or_dynop void op_illegal(void)
1079 
{
1080 
  env->sprs[SPR_EEAR_BASE] = get_pc();
1081 
  handle_except(EXCEPT_ILLEGAL);
1082 
}
1083 
 
1084 
__or_dynop void op_do_sched(void)
1085 
{
1086 
  handle_sched();
1087 
}
1088 
 
1089 
__or_dynop void op_macc(void)
1090 
{
1091 
  env->sprs[SPR_MACLO] = 0;
1092 
  env->sprs[SPR_MACHI] = 0;
1093 
}
1094 
 
1095 
__or_dynop void op_store_insn_ea(void)
1096 
{
1097 
  env->insn_ea = OP_PARAM1;
1098 
}
1099 
 
1100 
__or_dynop void op_calc_insn_ea_t0(void)
1101 
{
1102 
  env->insn_ea = t0 + OP_PARAM1;
1103 
}
1104 
 
1105 
__or_dynop void op_calc_insn_ea_t1(void)
1106 
{
1107 
  env->insn_ea = t1 + OP_PARAM1;
1108 
}
1109 
 
1110 
__or_dynop void op_calc_insn_ea_t2(void)
1111 
{
1112 
  env->insn_ea = t2 + OP_PARAM1;
1113 
}
1114 
 
1115 
__or_dynop void op_macrc_t0(void)
1116 
{
1117 
  /* FIXME: How is this supposed to work?  The architechture manual says that
1118 
   * the low 32-bits shall be saved into rD.  I have just copied this code from
1119 
   * insnset.c to make testbench/mul pass */
1120 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1121 
 
1122 
  t0 = (orreg_t)(temp >> 28);
1123 
  env->sprs[SPR_MACLO] = 0;
1124 
  env->sprs[SPR_MACHI] = 0;
1125 
}
1126 
 
1127 
__or_dynop void op_macrc_t1(void)
1128 
{
1129 
  /* FIXME: How is this supposed to work?  The architechture manual says that
1130 
   * the low 32-bits shall be saved into rD.  I have just copied this code from
1131 
   * insnset.c to make testbench/mul pass */
1132 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1133 
 
1134 
  t1 = (orreg_t)(temp >> 28);
1135 
 
1136 
  env->sprs[SPR_MACLO] = 0;
1137 
  env->sprs[SPR_MACHI] = 0;
1138 
}
1139 
 
1140 
__or_dynop void op_macrc_t2(void)
1141 
{
1142 
  /* FIXME: How is this supposed to work?  The architechture manual says that
1143 
   * the low 32-bits shall be saved into rD.  I have just copied this code from
1144 
   * insnset.c to make testbench/mul pass */
1145 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1146 
 
1147 
  t2 = (orreg_t)(temp >> 28);
1148 
 
1149 
  env->sprs[SPR_MACLO] = 0;
1150 
  env->sprs[SPR_MACHI] = 0;
1151 
}
1152 
 
1153 
__or_dynop void op_mac_imm_t0(void)
1154 
{
1155 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1156 
 
1157 
  temp += (int64_t)t0 * (int64_t)OP_PARAM1;
1158 
 
1159 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
1160 
  env->sprs[SPR_MACHI] = temp >> 32;
1161 
}
1162 
 
1163 
__or_dynop void op_mac_imm_t1(void)
1164 
{
1165 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1166 
 
1167 
  temp += (int64_t)t1 * (int64_t)OP_PARAM1;
1168 
 
1169 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
1170 
  env->sprs[SPR_MACHI] = temp >> 32;
1171 
}
1172 
 
1173 
__or_dynop void op_mac_imm_t2(void)
1174 
{
1175 
  int64_t temp = env->sprs[SPR_MACLO] | ((int64_t)env->sprs[SPR_MACHI] << 32);
1176 
 
1177 
  temp += (int64_t)t2 * (int64_t)OP_PARAM1;
1178 
 
1179 
  env->sprs[SPR_MACLO] = temp & 0xffffffff;
1180 
  env->sprs[SPR_MACHI] = temp >> 32;
1181 
}
1182 
 
1183 
__or_dynop void op_cmov_t0_t0_t1(void)
1184 
{
1185 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
1186 
}
1187 
 
1188 
__or_dynop void op_cmov_t0_t0_t2(void)
1189 
{
1190 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
1191 
}
1192 
 
1193 
__or_dynop void op_cmov_t0_t1_t0(void)
1194 
{
1195 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
1196 
}
1197 
 
1198 
__or_dynop void op_cmov_t0_t1_t2(void)
1199 
{
1200 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
1201 
  FORCE_RET;
1202 
}
1203 
 
1204 
__or_dynop void op_cmov_t0_t2_t0(void)
1205 
{
1206 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
1207 
}
1208 
 
1209 
__or_dynop void op_cmov_t0_t2_t1(void)
1210 
{
1211 
  t0 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
1212 
  FORCE_RET;
1213 
}
1214 
 
1215 
__or_dynop void op_cmov_t1_t0_t1(void)
1216 
{
1217 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
1218 
}
1219 
 
1220 
__or_dynop void op_cmov_t1_t0_t2(void)
1221 
{
1222 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
1223 
  FORCE_RET;
1224 
}
1225 
 
1226 
__or_dynop void op_cmov_t1_t1_t0(void)
1227 
{
1228 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
1229 
}
1230 
 
1231 
__or_dynop void op_cmov_t1_t1_t2(void)
1232 
{
1233 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
1234 
}
1235 
 
1236 
__or_dynop void op_cmov_t1_t2_t0(void)
1237 
{
1238 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
1239 
  FORCE_RET;
1240 
}
1241 
 
1242 
__or_dynop void op_cmov_t1_t2_t1(void)
1243 
{
1244 
  t1 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
1245 
}
1246 
 
1247 
__or_dynop void op_cmov_t2_t0_t1(void)
1248 
{
1249 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t1;
1250 
  FORCE_RET;
1251 
}
1252 
 
1253 
__or_dynop void op_cmov_t2_t0_t2(void)
1254 
{
1255 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t0 : t2;
1256 
}
1257 
 
1258 
__or_dynop void op_cmov_t2_t1_t0(void)
1259 
{
1260 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t0;
1261 
  FORCE_RET;
1262 
}
1263 
 
1264 
__or_dynop void op_cmov_t2_t1_t2(void)
1265 
{
1266 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t1 : t2;
1267 
}
1268 
 
1269 
__or_dynop void op_cmov_t2_t2_t0(void)
1270 
{
1271 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t0;
1272 
}
1273 
 
1274 
__or_dynop void op_cmov_t2_t2_t1(void)
1275 
{
1276 
  t2 = env->sprs[SPR_SR] & SPR_SR_F ? t2 : t1;
1277 
}
1278 
 
1279 
__or_dynop void op_neg_t0_t0(void)
1280 
{
1281 
  t0 = -t0;
1282 
}
1283 
 
1284 
__or_dynop void op_neg_t0_t1(void)
1285 
{
1286 
  t0 = -t1;
1287 
}
1288 
 
1289 
__or_dynop void op_neg_t0_t2(void)
1290 
{
1291 
  t0 = -t2;
1292 
}
1293 
 
1294 
__or_dynop void op_neg_t1_t0(void)
1295 
{
1296 
  t1 = -t0;
1297 
}
1298 
 
1299 
__or_dynop void op_neg_t1_t1(void)
1300 
{
1301 
  t1 = -t1;
1302 
}
1303 
 
1304 
__or_dynop void op_neg_t1_t2(void)
1305 
{
1306 
  t1 = -t2;
1307 
}
1308 
 
1309 
__or_dynop void op_neg_t2_t0(void)
1310 
{
1311 
  t2 = -t0;
1312 
}
1313 
 
1314 
__or_dynop void op_neg_t2_t1(void)
1315 
{
1316 
  t2 = -t1;
1317 
}
1318 
 
1319 
__or_dynop void op_neg_t2_t2(void)
1320 
{
1321 
  t2 = -t2;
1322 
}
1323 
 

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