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[/] [or1k/] [tags/] [nog_patch_69/] [or1ksim/] [testbench/] [int_test.S] - Blame information for rev 600

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1 576 markom 
/* Within the test we'll use following global variables:
2 
 
3 
   r16 interrupt counter
4 
   r17 current tick timer comparison counter
5 
   r18 sanity counter
6 
   r19 loop counter
7 
   r20 temp value of SR reg
8 
   r21 temp value of TTMR reg.
9 
   r23 RAM_START
10 
 
11 
   r25-r31 used by int handler
12 
 
13 
   The test do the following:
14 
   We set up the tick timer to trigger once and then we trigger interrupts incrementally
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   on every cycle in the specified test program; on interrupt handler we check if data computed
16 
   so far exactly matches precalculated values. If interrupt has returned incorreclty, we can
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   detect this using assertion routine at the end.
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*/
19 
 
20 
#include "spr_defs.h"
21 
#define  RAM_START 0x40000000
22 
 
23 
.section .except
24 
.org 0x100
25 
  l.j     _main
26 
  l.nop
27 
 
28 600 simons 
.org 0x500
29 576 markom 
#
30 600 simons 
# Tick timer exception handler
31 576 markom 
#
32 
 
33 
  l.addi  r31,r3,0
34 
# get interrupted program pc
35 
  l.mfspr r25,r0,SPR_EPCR_BASE
36 
 
37 
# calculate instruction address
38 
  l.movhi r26,hi(_ie_start)
39 
  l.ori   r26,r26,lo(_ie_start)
40 
  l.addi  r3,r25,0    #print insn index
41 
  l.nop   2
42 
  l.sub   r25,r25,r26
43 
  l.addi  r3,r25,0    #print insn index
44 
  l.nop   2
45 
 
46 
  l.addi  r3,r31,0    # restore r3
47 
  l.sfeqi r25, 0x00
48 
  l.bf    _i00
49 
  l.sfeqi r25, 0x04
50 
  l.bf    _i04
51 
  l.sfeqi r25, 0x08
52 
  l.bf    _i08
53 
  l.sfeqi r25, 0x0c
54 
  l.bf    _i0c
55 
  l.sfeqi r25, 0x10
56 
  l.bf    _i10
57 
  l.sfeqi r25, 0x14
58 
  l.bf    _i14
59 
  l.sfeqi r25, 0x18
60 
  l.bf    _i18
61 
  l.sfeqi r25, 0x1c
62 
  l.bf    _i1c
63 
  l.sfeqi r25, 0x20
64 
  l.bf    _i20
65 
  l.sfeqi r25, 0x24
66 
  l.bf    _i24
67 
  l.sfeqi r25, 0x28
68 
  l.bf    _i28
69 
  l.sfeqi r25, 0x2c
70 
  l.bf    _i2c
71 
  l.sfeqi r25, 0x30
72 
  l.bf    _i30
73 
  l.sfeqi r25, 0x34
74 
  l.bf    _i34
75 
  l.sfeqi r25, 0x38
76 
  l.bf    _i38
77 
  l.nop
78 
 
79 
# value not defined
80 
_die:
81 
  l.nop   2             #print r3
82 
 
83 
  l.addi  r3,r0,0xeeee
84 
  l.nop   2
85 
  l.addi  r3,r0,1
86 
  l.nop   1
87 
1:
88 
  l.j     1b
89 
  l.nop
90 
 
91 
.section  .text
92 
_main:
93 
        l.nop
94 600 simons 
  l.addi  r3,r0,SPR_SR_SM
95 
  l.mtspr r0,r3,SPR_SR
96 576 markom 
        l.nop
97 
 
98 
#
99 
# set tick counter to initial 3 cycles
100 
#
101 
  l.addi r16,r0,0
102 
  l.addi r17,r0,1
103 
  l.addi r18,r0,0
104 
  l.addi r19,r0,0
105 
  l.addi r22,r0,0
106 
 
107 
  l.movhi r23,hi(RAM_START)
108 
  l.ori   r23,r23,lo(RAM_START)
109 
 
110 
#
111 
# unmask all ints
112 
#
113 
        l.movhi r5,0xffff
114 
        l.ori   r5,r5,0xffff
115 
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
116 
 
117 600 simons 
# Set r20 to hold enable tick exception
118 576 markom 
        l.mfspr r20,r0,SPR_SR
119 600 simons 
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
120 576 markom 
 
121 
# Set r21 to hold value of TTMR
122 
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
123 
        l.add  r21,r5,r17
124 
 
125 
#
126 
# MAIN LOOP
127 
#
128 
_main_loop:
129 
# reinitialize memory and registers
130 
  l.addi  r3,r0,0xaaaa
131 
  l.addi  r9,r0,0xbbbb
132 
  l.sw    0(r23),r3
133 
  l.sw    4(r23),r9
134 
  l.sw    8(r23),r3
135 
 
136 
# Reinitializes tick timer
137 
  l.addi  r17,r17,1
138 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
139 
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
140 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
141 
        l.addi  r21,r21,1
142 
 
143 
# Enable exceptions and interrupts
144 
        l.mtspr r0,r20,SPR_SR   # set SR
145 
 
146 
##### TEST CODE #####
147 
_ie_start:
148 
  l.movhi r3,0x1234         #00
149 
  l.sw    0(r23),r3         #04
150 
  l.movhi r3,hi(RAM_START)  #08
151 
  l.lwz   r3,0(r3)          #0c
152 
  l.movhi r3,hi(RAM_START)  #10
153 
  l.addi  r3,r3,4           #14
154 
  l.j     1f                #18
155 
  l.lwz   r3,0(r3)          #1c
156 
  l.addi  r3,r3,1           #20
157 
1:
158 
  l.sfeqi r3,0xdead         #24
159 
  l.jal   2f                #28
160 
  l.addi  r3,r0,0x5678      #2c
161 
 
162 
_return_addr:
163 
2:
164 
  l.bf    _die              #30
165 
  l.sw    8(r23),r3         #34
166 
_ie_end:
167 
  l.nop                     #38
168 
##### END OF TEST CODE #####
169 
 
170 
# do some testing
171 
 
172 
  l.j     _main_loop
173 
  l.nop
174 
 
175 
_i00:
176 
  l.sfeqi r3,0xaaaa
177 
  l.bnf   _die
178 
  l.nop
179 
  l.j     _resume
180 
  l.nop
181 
_i04:
182 
  l.movhi  r26,0x1234
183 
  l.sfeq   r3,r26
184 
  l.bnf   _die
185 
  l.nop
186 
  l.lwz   r26,0(r23)
187 
  l.sfeqi r26,0xaaaa
188 
  l.bnf   _die
189 
  l.nop
190 
  l.j     _resume
191 
  l.nop
192 
_i08:
193 
  l.movhi r26,0x1234
194 
  l.sfeq  r3,r26
195 
  l.bnf   _die
196 
  l.nop
197 
  l.lwz   r27,0(r23)
198 
  l.sfeq  r27,r26
199 
  l.bnf   _die
200 
  l.nop
201 
  l.j     _resume
202 
  l.nop
203 
_i0c:
204 
  l.sfeq  r3,r23
205 
  l.bnf   _die
206 
  l.nop
207 
  l.j     _resume
208 
  l.nop
209 
_i10:
210 
  l.movhi r26,0x1234
211 
  l.sfeq  r26,r3
212 
  l.bnf   _die
213 
  l.nop
214 
  l.j     _resume
215 
  l.nop
216 
_i14:
217 
  l.sfeq  r3,r23
218 
  l.bnf   _die
219 
  l.nop
220 
  l.j     _resume
221 
  l.nop
222 
_i18:
223 
  l.addi  r26,r23,4
224 
  l.sfeq  r3,r26
225 
  l.bnf   _die
226 
  l.nop
227 
  l.j     _resume
228 
  l.nop
229 
_i1c:
230 
  l.j     _die
231 
  l.nop
232 
_i20:
233 
  l.j     _die
234 
  l.nop
235 
_i24:
236 
  l.mfspr r26,r0,SPR_ESR_BASE
237 
  l.addi  r30,r3,0
238 
  l.addi  r3,r26,0
239 
  l.nop   2
240 
  l.addi  r3,r30,0
241 
  l.andi  r26,r26,SPR_SR_F
242 
  l.sfeq  r26,r0
243 
  l.bf   _die
244 
  l.nop
245 
  l.sfeqi  r3,0xbbbb
246 
  l.bnf   _die
247 
  l.nop
248 
  l.j     _resume
249 
  l.nop
250 
_i28:
251 
  l.mfspr r26,r0,SPR_ESR_BASE
252 
  l.addi  r30,r3,0
253 
  l.addi  r3,r26,0
254 
  l.nop   2
255 
  l.addi  r3,r30,0
256 
  l.andi  r26,r26,SPR_SR_F
257 
  l.sfeq  r26,r0
258 
  l.bnf    _die
259 
  l.nop
260 
  l.sfeqi  r22,1
261 
  l.bf     _resume
262 
  l.addi   r22,r0,1
263 
  l.sfeqi  r9,0xbbbb
264 
  l.bnf   _die
265 
  l.nop
266 
  l.j     _resume
267 
  l.nop
268 
_i2c:
269 
  l.movhi  r26,hi(_return_addr)
270 
  l.ori    r26,r26,lo(_return_addr)
271 
  l.sfeq   r9,r26
272 
  l.bnf   _die
273 
  l.nop
274 
  l.sfeqi  r3,0xbbbb
275 
  l.bnf   _die
276 
  l.nop
277 
  l.j     _resume
278 
  l.nop
279 
_i30:
280 
  l.sfeqi  r3,0x5678
281 
  l.bnf   _die
282 
  l.nop
283 
  l.j     _resume
284 
  l.nop
285 
_i34:
286 
  l.sfeqi  r3,0x5678
287 
  l.bnf   _die
288 
  l.nop
289 
  l.lwz    r26,8(r23)
290 
  l.sfeqi  r26,0xaaaa
291 
  l.bnf   _die
292 
  l.nop
293 
  l.j     _resume
294 
  l.nop
295 
_i38:
296 
  l.lwz    r26,8(r23)
297 
  l.sfeqi  r26,0x5678
298 
  l.bnf   _die
299 
  l.nop
300 
#
301 
# mark finished ok
302 
#
303 
  l.movhi r3,hi(0xdeaddead)
304 
  l.ori   r3,r3,lo(0xdeaddead)
305 
  l.nop   2
306 
  l.addi  r3,r0,0
307 
  l.nop   1
308 
_ok:
309 
  l.j     _ok
310 
  l.nop
311 
 
312 
_resume:
313 
  l.mfspr  r27,r0,SPR_ESR_BASE
314 600 simons 
  l.addi   r26,r0,SPR_SR_TEE
315 576 markom 
  l.addi   r28,r0,-1
316 
  l.xor    r26,r26,r28
317 
  l.and    r26,r26,r27
318 
  l.mtspr  r0,r26,SPR_ESR_BASE
319 
 
320 
  l.rfe
321 
  l.addi    r3,r3,5         # should not be executed

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