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[/] [or1k/] [tags/] [nog_patch_70/] [or1ksim/] [cuc/] [verilog.c] - Blame information for rev 1765

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1 1244 hpanther 
/* verilog.c -- OpenRISC Custom Unit Compiler, verilog generator
2 
 *    Copyright (C) 2002 Marko Mlinar, markom@opencores.org
3 
 *
4 
 *    This file is part of OpenRISC 1000 Architectural Simulator.
5 
 *
6 
 *    This program is free software; you can redistribute it and/or modify
7 
 *    it under the terms of the GNU General Public License as published by
8 
 *    the Free Software Foundation; either version 2 of the License, or
9 
 *    (at your option) any later version.
10 
 *
11 
 *    This program is distributed in the hope that it will be useful,
12 
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 
 *    GNU General Public License for more details.
15 
 *
16 
 *    You should have received a copy of the GNU General Public License
17 
 *    along with this program; if not, write to the Free Software
18 
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
19 
 
20 
#include <stdio.h>
21 
#include <stdlib.h>
22 
#include <stdarg.h>
23 
#include <assert.h>
24 1308 phoenix 
 
25 1350 nogj 
#include "config.h"
26 
 
27 
#ifdef HAVE_INTTYPES_H
28 
#include <inttypes.h>
29 
#endif
30 
 
31 
#include "port.h"
32 
#include "arch.h"
33 1308 phoenix 
#include "abstract.h"
34 1244 hpanther 
#include "cuc.h"
35 
#include "insn.h"
36 
#include "profiler.h"
37 
#include "sim-config.h"
38 
 
39 
/* Shortcut */
40 
#define GEN(x...) fprintf (fo, x)
41 
 
42 
/* Find index of load/store/call */
43 
int find_lsc_index (cuc_func *f, int ref)
44 
{
45 
  int c = 0;
46 
  int i;
47 
  int load;
48 
 
49 
  if (f->INSN(ref).index == II_CALL) {
50 
    for (i = 0; i < f->nmsched; i++) {
51 
      if (f->msched[i] == ref) break;
52 
      if (f->mtype[i] & MT_CALL) c++;
53 
    }
54 
  } else {
55 
    load = II_IS_LOAD (f->INSN(ref).index);
56 
    for (i = 0; i < f->nmsched; i++) {
57 
      if (f->msched[i] == ref) break;
58 
      if (load && (f->mtype[i] & MT_LOAD)
59 
       || !load && (f->mtype[i] & MT_STORE)) c++;
60 
    }
61 
  }
62 
  return c;
63 
}
64 
 
65 
/* Print out dependencies as verilog expression */
66 
void print_deps (FILE *fo, cuc_func *f, int b, dep_list *t, int registered)
67 
{
68 
  if (t) {
69 
    int first = 0;
70 
    while (t) {
71 
      if (f->INSN(t->ref).type & IT_MEMORY) {
72 
        GEN ("%s%c_end[%i]", first ? " && " : "",
73 
                  II_IS_LOAD (f->INSN(t->ref).index) ? 'l' : 's', find_lsc_index (f, t->ref));
74 
      } else if (f->INSN(t->ref).index == II_CALL) {
75 
        GEN ("%sf_end[%i]", first ? " && " : "", find_lsc_index (f, t->ref));
76 
      } else {
77 1308 phoenix 
        PRINTF ("print_deps: err %lx\n", t->ref);
78 1244 hpanther 
        assert (0);
79 
      }
80 
      first = 1;
81 
      t = t->next;
82 
    }
83 
  } else {
84 
    if (registered) GEN ("bb_start_r[%i]", b);
85 
    else GEN ("bb_start[%i]", b);
86 
  }
87 
}
88 
 
89 
char *print_op_v (cuc_func *f, char *s, int ref, int j)
90 
{
91 
  unsigned long op = f->INSN(ref).op[j];
92 
  unsigned long opt = f->INSN(ref).opt[j];
93 
  switch (opt & ~OPT_DEST) {
94 
    case OPT_NONE: assert (0); break;
95 
    case OPT_CONST: if (f->INSN(ref).type & IT_COND && (f->INSN(ref).index == II_CMOV
96 
                     || f->INSN(ref).index == II_ADD)) {
97 
                      assert (op == 0 || op == 1);
98 1308 phoenix 
                      sprintf (s, "1'b%lx", op);
99 
                    } else sprintf (s, "32'h%lx", op);
100 1244 hpanther 
                    break;
101 
    case OPT_REGISTER:
102 
                    if (opt & OPT_DEST) sprintf (s, "t%x_%x", REF_BB(ref), REF_I(ref));
103 1308 phoenix 
                    else sprintf (s, "r%li_%c", op, opt & OPT_DEST ? 'o' : 'i');
104 1244 hpanther 
                    break;
105 
#if 0
106 
    case OPT_FREG:  assert (opt & OPT_DEST);
107 
                    sprintf (s, "fr%i_o", op);
108 
                    break;
109 
#endif
110 1308 phoenix 
    case OPT_REF:   sprintf (s, "t%lx_%lx", REF_BB(op), REF_I(op)); break;
111 1244 hpanther 
  }
112 
  return s;
113 
}
114 
 
115 
/* Prints out specified instruction */
116 
void print_insn_v (FILE *fo, cuc_func *f, int b, int i)
117 
{
118 
  cuc_insn *ii = &f->bb[b].insn[i];
119 
  char *s = known[ii->index].rtl;
120 
  char tmp[200] = "";
121 
 
122 
  assert (s);
123 
  while (*s) {
124 
    if (*s <= MAX_OPERANDS) {
125 
      char t[30];
126 
      sprintf (tmp, "%s%s", tmp, print_op_v (f, t, REF(b, i), *s - 1));
127 
    } else if (*s == '\b') sprintf (tmp, "%s%i", b);
128 
    else sprintf (tmp, "%s%c", tmp, *s);
129 
    s++;
130 
  }
131 
  GEN ("%-40s /* %s */\n", tmp, ii->disasm);
132 
  if (ii->type & IT_MEMORY) {
133 1308 phoenix 
    int nls = find_lsc_index (f, REF (b, i));
134 1244 hpanther 
    if (II_IS_LOAD (ii->index)) {
135 
      int nm;
136 
      for (nm = 0; nm < f->nmsched; nm++) if (f->msched[nm] == REF (b, i)) break;
137 
      assert (nm < f->nmsched);
138 
 
139 
      GEN ("  if (l_end[%i]) t%x_%x <= #Tp ", nls, b, i);
140 
      switch (f->mtype[nm] & (MT_WIDTH | MT_SIGNED)) {
141 
        case 1: GEN ("l_dat_i & 32'hff;\n");
142 
                break;
143 
        case 2: GEN ("l_dat_i & 32'hffff;\n");
144 
                break;
145 
        case 4 | MT_SIGNED:
146 
        case 4: GEN ("l_dat_i;\n");
147 
                break;
148 
        case 1 | MT_SIGNED:
149 
                GEN ("{24{l_dat_i[7]}, l_dat_i[7:0]};\n");
150 
                break;
151 
        case 2 | MT_SIGNED:
152 
                GEN ("{16{l_dat_i[15]}, l_dat_i[15:0]};\n");
153 
                break;
154 
        default: assert (0);
155 
      }
156 
    }
157 
  } else if (ii->index == II_LRBB) {
158 
    GEN ("  if (rst) t%x_%x <= #Tp 1'b0;\n", b, i);
159 
    assert (f->bb[b].prev[0] >= 0);
160 
    if (f->bb[b].prev[0] == BBID_START)
161 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp start_i;\n", b, b, i);
162 
    else
163 
      GEN ("  else if (bb_start[%i]) t%x_%x <= #Tp bb_stb[%i];\n", b, b, i, f->bb[b].prev[0]);
164 
  } else if (ii->index == II_REG) {
165 
    assert (ii->opt[1] == OPT_REF);
166 
    GEN ("  if (");
167 
    if (f->bb[b].mdep) print_deps (fo, f, b, f->bb[b].mdep, 0);
168 
    else GEN ("bb_stb[%i]", b);
169 1308 phoenix 
    GEN (") t%x_%x <= #Tp t%lx_%lx;\n",  b, i,
170 1244 hpanther 
                    REF_BB (ii->op[1]), REF_I (ii->op[1]));
171 
  }
172 
}
173 
 
174 
/* Outputs binary number */
175 
static char *bin_str (unsigned long x, int len)
176 
{
177 
  static char bx[33];
178 
  char *s = bx;
179 
  while (len > 0) *s++ = '0' + ((x >> --len) & 1);
180 
  *s = '\0';
181 
  return bx;
182 
}
183 
 
184 
/* Returns index of branch instruction inside a block b */
185 
static int branch_index (cuc_bb *bb)
186 
{
187 
  int i;
188 
  for (i = bb->ninsn - 1; i >= 0; i--)
189 
    if (bb->insn[i].type & IT_BRANCH) return i;
190 
  return -1;
191 
}
192 
 
193 
static void print_turn_off_dep (FILE *fo, cuc_func *f, dep_list *dep)
194 
{
195 
  while (dep) {
196 
    assert (f->INSN(dep->ref).type & IT_MEMORY || f->INSN(dep->ref).index == II_CALL);
197 
    GEN ("      %c_stb[%i] <= #Tp 1'b0;\n", f->INSN(dep->ref).index == II_CALL ? 'f'
198 
            : II_IS_LOAD (f->INSN(dep->ref).index) ? 'l' : 's', find_lsc_index (f, dep->ref));
199 
    dep = dep->next;
200 
  }
201 
}
202 
 
203 
static int func_index (cuc_func *f, int ref)
204 
{
205 
  int i;
206 
  unsigned long addr;
207 
  assert (f->INSN(ref).index == II_CALL && f->INSN(ref).opt[0] & OPT_CONST);
208 
  addr = f->INSN(ref).op[0];
209 
  for (i = 0; i < f->nfdeps; i++)
210 
    if (f->fdeps[i]->start_addr == addr) return i;
211 
 
212 
  assert (0);
213 
  return -1;
214 
}
215 
 
216 
/* Generates verilog file out of insn dataflow */
217 
void output_verilog (cuc_func *f, char *filename, char *funcname)
218 
{
219 
  FILE *fo;
220 
  int b, i, j;
221 
  int ci = 0, co = 0;
222 
  int nloads = 0, nstores = 0, ncalls = 0;
223 
  char tmp[256];
224 
  sprintf (tmp, "%s.v", filename);
225 
 
226 
  log ("Generating verilog file \"%s\"\n", tmp);
227 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
228 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
229 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
230 
    exit (1);
231 
  }
232 
 
233 
  /* output header */
234 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
235 
  GEN ("   (C) 2002 Opencores\n");
236 
  GEN ("   function   \"%s\"\n", funcname);
237 1308 phoenix 
  GEN ("   at         %08lx - %08lx\n", f->start_addr, f->end_addr);
238 1244 hpanther 
  GEN ("   num BBs    %i */\n\n", f->num_bb);
239 
 
240 
  GEN ("`include \"timescale.v\"\n\n");
241 
  GEN ("module %s (clk, rst,\n", filename);
242 
  GEN ("              l_adr_o, l_dat_i, l_req_o,\n");
243 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i,\n");
244 
  GEN ("              s_adr_o, s_dat_o, s_req_o,\n");
245 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i,\n");
246 
 
247 
  GEN ("/* inputs */  ");
248 
  for (i = 0; i < MAX_REGS; i++)
249 
    if (f->used_regs[i]) {
250 
      GEN ("r%i_i, ", i);
251 
      ci++;
252 
    }
253 
  if (!ci) GEN ("/* NONE */");
254 
 
255 
  GEN ("\n/* outputs */ ");
256 
  for (i = 0; i < MAX_REGS; i++)
257 
    if (f->lur[i] >= 0 && !f->saved_regs[i]) {
258 
      GEN ("r%i_o, ", i);
259 
      co++;
260 
    }
261 
 
262 
  if (!co) GEN ("/* NONE */");
263 
  if (f->nfdeps) {
264 
    GEN ("\n/* f. calls */, fstart_o, %sfend_i, fr11_i, ",
265 
                    log2_int (f->nfdeps) > 0 ? "fid_o, " : "");
266 
    for (i = 0; i < 6; i++) GEN ("fr%i_o, ", i + 3);
267 
  }
268 
  GEN ("\n              start_i, end_o, busy_o);\n\n");
269 
 
270 
  GEN ("parameter Tp = 1;\n\n");
271 
 
272 
  GEN ("input         clk, rst;\n");
273 
  GEN ("input         start_i;\t/* Module starts when set to 1 */ \n");
274 
  GEN ("output        end_o;\t/* Set when module finishes, cleared upon start_i == 1 */\n");
275 
  GEN ("output        busy_o;\t/* Set when module should not be interrupted */\n");
276 
  GEN ("\n/* Bus signals */\n");
277 
  GEN ("output        l_req_o, s_req_o;\n");
278 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
279 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
280 
  GEN ("output [31:0] l_adr_o, s_adr_o;\n");
281 
  GEN ("output        l_linbrst_o, s_linbrst_o;\n");
282 
  GEN ("input  [31:0] l_dat_i;\n");
283 
  GEN ("output [31:0] s_dat_o;\n\n");
284 
 
285 
  GEN ("reg           l_req_o, s_req_o;\n");
286 
  GEN ("reg    [31:0] l_adr_o, s_adr_o;\n");
287 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
288 
  GEN ("reg    [31:0] s_dat_o;\n");
289 
  GEN ("reg           l_linbrst_o, s_linbrst_o;\n");
290 
 
291 
  if (ci || co) GEN ("\n/* module ports */\n");
292 
  if (ci) {
293 
    int first = 1;
294 
    GEN ("input  [31:0]");
295 
    for (i = 0; i < MAX_REGS; i++)
296 
      if (f->used_regs[i]) {
297 
        GEN ("%sr%i_i", first ? " " : ", ", i);
298 
        first = 0;
299 
      }
300 
    GEN (";\n");
301 
  }
302 
 
303 
  if (co) {
304 
    int first = 1;
305 
    GEN ("output [31:0]");
306 
    for (i = 0; i < MAX_REGS; i++)
307 
      if (f->lur[i] >= 0 && !f->saved_regs[i]) {
308 
        GEN ("%sr%i_o", first ? " " : ", ", i);
309 
        first = 0;
310 
      }
311 
    GEN (";\n");
312 
  }
313 
 
314 
  if (f->nfdeps) {
315 
    GEN ("\n/* Function calls */\n");
316 
    GEN ("output [31:0] fr3_o");
317 
    for (i = 1; i < 6; i++) GEN (", fr%i_o", i + 3);
318 
    GEN (";\n");
319 
    GEN ("input  [31:0] fr11_i;\n");
320 
    if (log2_int(f->nfdeps) > 0) GEN ("output [%i:0] fid_o;\n", log2_int(f->nfdeps));
321 
    GEN ("output        fstart_o;\n");
322 
    GEN ("input         fend_i;\n");
323 
  }
324 
 
325 
  /* Count loads & stores */
326 
  for (i = 0; i < f->nmsched; i++)
327 
    if (f->mtype[i] & MT_STORE) nstores++;
328 
    else if (f->mtype[i] & MT_LOAD) nloads++;
329 
    else if (f->mtype[i] & MT_CALL) ncalls++;
330 
 
331 
  /* Output internal registers for loads */
332 
  if (nloads) {
333 
    int first = 1;
334 
    int num = 0;
335 
    GEN ("\n/* internal registers for loads */\n");
336 
    for (i = 0; i < f->nmsched; i++)
337 
      if (f->mtype[i] & MT_LOAD) {
338 
        GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ",
339 
                REF_BB(f->msched[i]), REF_I(f->msched[i]));
340 
 
341 
        if (num >= 8) {
342 
          GEN (";\n");
343 
          first = 1;
344 
          num = 0;
345 
        } else {
346 
          first = 0;
347 
          num++;
348 
        }
349 
      }
350 
    if (!first) GEN (";\n");
351 
  }
352 
 
353 
  /* Internal register for function return value */
354 
  if (f->nfdeps) {
355 
    GEN ("\n/* Internal register for function return value */\n");
356 
    GEN ("reg     [31:0] fr11_r;\n");
357 
  }
358 
 
359 
  GEN ("\n/* 'zero or one' hot state machines */\n");
360 
  if (nloads) GEN ("reg     [%i:0] l_stb; /* loads */\n", nloads - 1);
361 
  if (nstores) GEN ("reg     [%i:0] s_stb; /* stores */\n", nstores - 1);
362 
  GEN ("reg     [%i:0] bb_stb; /* basic blocks */\n", f->num_bb - 1);
363 
 
364 
  {
365 
    int first = 2;
366 
    int num = 0;
367 
    for (b = 0; b < f->num_bb; b++)
368 
      for (i = 0; i < f->bb[b].ninsn; i++)
369 
        if (f->bb[b].insn[i].type & IT_COND
370 
         && f->bb[b].insn[i].index != II_REG
371 
         && f->bb[b].insn[i].index != II_LRBB) {
372 
          if (first == 2) GEN ("\n/* basic block condition wires */\n");
373 
          GEN ("%st%x_%x", first ? "wire          " : ", ", b, i);
374 
          if (num >= 8) {
375 
            GEN (";\n");
376 
            first = 1;
377 
            num = 0;
378 
          } else {
379 
            first = 0;
380 
            num++;
381 
          }
382 
        }
383 
    if (!first) GEN (";\n");
384 
 
385 
    GEN ("\n/* forward declaration of normal wires */\n");
386 
    num = 0;
387 
    first = 1;
388 
    for (b = 0; b < f->num_bb; b++)
389 
      for (i = 0; i < f->bb[b].ninsn; i++)
390 
        if (!(f->bb[b].insn[i].type & (IT_COND | IT_BRANCH))
391 
         && f->bb[b].insn[i].index != II_REG
392 
         && f->bb[b].insn[i].index != II_LRBB) {
393 
          /* Exclude loads */
394 
          if (f->bb[b].insn[i].type & IT_MEMORY && II_IS_LOAD (f->bb[b].insn[i].index)) continue;
395 
          GEN ("%st%x_%x", first ? "wire   [31:0] " : ", ", b, i);
396 
          if (num >= 8) {
397 
            GEN (";\n");
398 
            first = 1;
399 
            num = 0;
400 
          } else {
401 
            first = 0;
402 
            num++;
403 
          }
404 
        }
405 
    if (!first) GEN (";\n");
406 
 
407 
    GEN ("\n/* forward declaration registers */\n");
408 
    num = 0;
409 
    first = 1;
410 
    for (b = 0; b < f->num_bb; b++)
411 
      for (i = 0; i < f->bb[b].ninsn; i++)
412 
        if (f->bb[b].insn[i].index == II_REG
413 
         && f->bb[b].insn[i].index != II_LRBB) {
414 
          GEN ("%st%x_%x", first ? "reg    [31:0] " : ", ", b, i);
415 
          if (num >= 8) {
416 
            GEN (";\n");
417 
            first = 1;
418 
            num = 0;
419 
          } else {
420 
            first = 0;
421 
            num++;
422 
          }
423 
        }
424 
    if (!first) GEN (";\n");
425 
 
426 
    num = 0;
427 
    first = 1;
428 
    for (b = 0; b < f->num_bb; b++)
429 
      for (i = 0; i < f->bb[b].ninsn; i++)
430 
        if (f->bb[b].insn[i].index != II_REG
431 
         && f->bb[b].insn[i].index == II_LRBB) {
432 
          GEN ("%st%x_%x", first ? "reg           " : ", ", b, i);
433 
          if (num >= 8) {
434 
            GEN (";\n");
435 
            first = 1;
436 
            num = 0;
437 
          } else {
438 
            first = 0;
439 
            num++;
440 
          }
441 
        }
442 
    if (!first) GEN (";\n");
443 
  }
444 
 
445 
  if (nloads || nstores) GEN ("\n/* dependencies */\n");
446 
  if (nloads) GEN ("wire    [%i:0] l_end = l_stb & {%i{l_rdy_i}};\n",
447 
                  nloads - 1, nloads);
448 
  if (nstores) GEN ("wire    [%i:0] s_end = s_stb & {%i{s_rdy_i}};\n",
449 
                  nstores - 1, nstores);
450 
  if (ncalls) GEN ("wire    [%i:0] f_end = f_stb & {%i{fend_i}};\n",
451 
                  ncalls - 1, ncalls);
452 
 
453 
  GEN ("\n/* last dependency */\n");
454 
  GEN ("wire   end_o = ");
455 
  for (b = 0; b < f->num_bb; b++) {
456 
    for (i = 0; i < 2; i++) if (f->bb[b].next[i] == BBID_END) {
457 
      GEN ("bb_stb[%i]", b);
458 
      if (f->bb[b].mdep) {
459 
        GEN (" && ");
460 
        print_deps (fo, f, b, f->bb[b].mdep, 0);
461 
      }
462 
      /* Is branch to BBID_END conditional? */
463 
      if (f->bb[b].next[1 - i] >= 0) {
464 
        int bidx = branch_index (&f->bb[b]);
465 
        char t[30];
466 
        print_op_v (f, t, REF (b, bidx), 1);
467 
        GEN (" && %s%s", i ? "" : "!", t);
468 
      }
469 
    }
470 
  }
471 
  GEN (";\n");
472 
  GEN ("wire   busy_o = |bb_stb;\n");
473 
 
474 
 
475 
  GEN ("\n/* Basic block triggers */\n");
476 
  GEN ("wire   [%2i:0] bb_start = {\n", f->num_bb - 1);
477 
  for (b = f->num_bb - 1; b >= 0; b--) {
478 
    GEN ("    /* bb_start[%2i] */ ", b);
479 
    for (i = 0; i < 2; i++) if (f->bb[b].prev[i] >= 0 && f->bb[b].prev[i] != BBID_START) {
480 
      cuc_bb *prev = &f->bb[f->bb[b].prev[i]];
481 
      int t;
482 
      if (i) GEN ("\n                    || ");
483 
      if (prev->mdep) {
484 
        print_deps (fo, f, f->bb[b].prev[i], prev->mdep, 0);
485 
        GEN (" && ");
486 
      }
487 
      GEN ("bb_stb[%i]", f->bb[b].prev[i]);
488 
      if (prev->next[0] >= 0 && prev->next[0] != BBID_END
489 
       && prev->next[1] >= 0 && prev->next[1] != BBID_END) {
490 
        int bi = REF (f->bb[b].prev[i], branch_index (&f->bb[f->bb[b].prev[i]]));
491 
        int ci;
492 
        assert (bi >= 0);
493 
        ci = f->INSN(bi).op[1];
494 
        t = prev->next[0] == b;
495 
        GEN (" && ");
496 
        if (f->INSN(bi).opt[1] & OPT_REF) {
497 
          GEN ("%st%x_%x", t ? "" : "!", REF_BB(ci), REF_I(ci));
498 
        } else {
499 
          cucdebug (5, "%x!%x!%x\n", bi, ci, f->INSN(bi).opt[1]);
500 
          assert (f->INSN(bi).opt[1] & OPT_CONST);
501 
          GEN ("%s%i", t ? "" : "!", ci);
502 
        }
503 
      }
504 
    } else break;
505 
    if (!i) GEN ("start_i");
506 
    if (b == 0) GEN ("};\n");
507 
    else GEN (",\n");
508 
  }
509 
 
510 
  GEN ("\n/* Register the bb_start */\n");
511 
  GEN ("reg   [%2i:0] bb_start_r;\n\n", f->num_bb - 1);
512 
  GEN ("always @(posedge rst or posedge clk)\n");
513 
  GEN ("begin\n");
514 
  GEN ("  if (rst) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
515 
  GEN ("  else if (end_o) bb_start_r <= #Tp %i'b0;\n", f->num_bb);
516 
  GEN ("  else bb_start_r <= #Tp bb_start;\n");
517 
  GEN ("end\n");
518 
 
519 
  GEN ("\n/* Logic */\n");
520 
  /* output body */
521 
  for (b = 0; b < f->num_bb; b++) {
522 
    GEN ("\t\t/* BB%i */\n", b);
523 
    for (i = 0; i < f->bb[b].ninsn; i++)
524 
      print_insn_v (fo, f, b, i);
525 
    GEN ("\n");
526 
  }
527 
 
528 
  if (co) {
529 
    GEN ("\n/* Outputs */\n");
530 
    for (i = 0; i < MAX_REGS; i++)
531 
      if (f->lur[i] >= 0 && !f->saved_regs[i])
532 
        GEN ("assign r%i_o = t%x_%x;\n", i, REF_BB(f->lur[i]),
533 
                        REF_I(f->lur[i]));
534 
  }
535 
 
536 
  if (nstores) {
537 
    int cur_store;
538 
    GEN ("\n/* Memory stores */\n");
539 
    GEN ("always @(s_stb");
540 
    for (i = 0; i < f->nmsched; i++)
541 
      if (f->mtype[i] & MT_STORE) {
542 
        char t[30];
543 
        unsigned long opt = f->INSN(f->msched[i]).opt[0];
544 
        if ((opt & ~OPT_DEST) != OPT_CONST) {
545 
          GEN (" or %s", print_op_v (f, t, f->msched[i], 0));
546 
        }
547 
      }
548 
 
549 
    cur_store = 0;
550 
    GEN (")\nbegin\n");
551 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_STORE) {
552 
      char t[30];
553 
      GEN ("  %sif (s_stb[%i]) s_dat_o = %s;\n", cur_store == 0 ? "" : "else ", cur_store,
554 
                      print_op_v (f, t, f->msched[i], 0));
555 
      cur_store++;
556 
      //PRINTF ("msched[%i] = %x (mtype %x) %x\n", i, f->msched[i], f->mtype[i], f->INSN(f->msched[i]).op[0]);
557 
    }
558 
    GEN ("  else s_dat_o = 32'hx;\n");
559 
    GEN ("end\n");
560 
  }
561 
 
562 
  /* Generate load and store state machine */
563 
#if 0
564 
  GEN ("\n/* Load&store state machine */\n");
565 
  GEN ("always @(posedge clk or posedge rst)\n");
566 
  GEN ("  if (rst) begin\n");
567 
  if (nloads) GEN ("    l_stb <= #Tp %i'h0;\n", nloads);
568 
  if (nstores) GEN ("    s_stb <= #Tp %i'h0;\n", nstores);
569 
  GEN ("  end else begin\n");
570 
  for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_LOAD || f->mtype[i] & MT_STORE) {
571 
    int cur = 0;
572 
    dep_list *dep = f->INSN(f->msched[i]).dep;
573 
    assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
574 
    GEN ("    if (");
575 
    print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
576 
    GEN (") begin\n");
577 
    print_turn_off_dep (fo, f, dep);
578 
    GEN ("      %c_stb[%i] <= #Tp 1'b1;\n", f->mtype[i] & MT_LOAD ? 'l' : 's', cur++);
579 
    GEN ("    end\n");
580 
  }
581 
  GEN ("    if (%c_end[%i]) %c_stb <= #Tp %i'h0;\n", c, cur - 1, c, cur);
582 
  GEN ("  end\n");
583 
#endif
584 
 
585 
  /* Generate state generator machine */
586 
  for (j = 0; j < 2; j++) {
587 
    char c;
588 
    char *s;
589 
 
590 
    switch (j) {
591 
      case 0: c = 'l'; s = "Load"; break;
592 
      case 1: c = 's'; s = "Store"; break;
593 
      case 2: c = 'c'; s = "Calls"; break;
594 
    }
595 
    if (j == 0 && nloads
596 
     || j == 1 && nstores
597 
     || j == 2 && ncalls) {
598 
      int cur = 0;
599 
      char t[30];
600 
 
601 
      GEN ("\n/* %s state generator machine */\n", s);
602 
      GEN ("always @(");
603 
      for (i = 0; i < f->nmsched; i++) {
604 
        print_op_v (f, t, f->msched[i], 1);
605 
        GEN ("%s or ", t);
606 
      }
607 
      GEN ("bb_start_r");
608 
      if (nloads) GEN (" or l_end");
609 
      if (nstores) GEN (" or s_end");
610 
      GEN (")\n");
611 
      GEN ("begin\n  ");
612 
      cucdebug (1, "%s\n", s);
613 
      for (i = 0; i < f->nmsched; i++)
614 
        if (j == 0 && f->mtype[i] & MT_LOAD
615 
         || j == 1 && f->mtype[i] & MT_STORE
616 
         || j == 2 && f->mtype[i] & MT_CALL) {
617 
        cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
618 
        assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
619 
        GEN ("if (");
620 
        print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
621 
        GEN (") begin\n");
622 
        GEN ("    %c_req_o = 1'b1;\n", c);
623 
        GEN ("    %c_sel_o[3:0] = 4'b", c);
624 
        switch (f->mtype[i] & MT_WIDTH) {
625 
          case 1: GEN ("0001 << (%s & 32'h3);\n",
626 
                                  print_op_v (f, t, f->msched[i], 1)); break;
627 
          case 2: GEN ("0011 << ((%s & 32'h1) << 1);\n",
628 
                                  print_op_v (f, t, f->msched[i], 1)); break;
629 
          case 4: GEN ("1111;\n"); break;
630 
          default: assert (0);
631 
        }
632 
        GEN ("    %c_linbrst_o = 1'b%i;\n", c,
633 
                      (f->mtype[i] & MT_BURST) && !(f->mtype[i] & MT_BURSTE) ? 1 : 0);
634 1308 phoenix 
        GEN ("    %c_adr_o = t%lx_%lx & ~32'h3;\n", c,
635 1244 hpanther 
                      REF_BB(f->INSN(f->msched[i]).op[1]), REF_I(f->INSN(f->msched[i]).op[1]));
636 
        GEN ("  end else ");
637 
      }
638 
      GEN ("if (%c_end[%i]) begin\n", c, cur - 1);
639 
      GEN ("    %c_req_o = 1'b0;\n", c);
640 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
641 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
642 
      GEN ("    %c_adr_o = 32'hx;\n", c);
643 
      GEN ("  end else begin\n");
644 
      GEN ("    %c_req_o = 1'b0;\n", c);
645 
      GEN ("    %c_sel_o[3:0] = 4'bx;\n", c);
646 
      GEN ("    %c_linbrst_o = 1'b0;\n", c);
647 
      GEN ("    %c_adr_o = 32'hx;\n", c);
648 
      GEN ("  end\n");
649 
      GEN ("end\n");
650 
    }
651 
  }
652 
 
653 
  if (ncalls) {
654 
    int cur_call = 0;
655 
    GEN ("\n/* Function calls state machine */\n");
656 
    GEN ("always @(posedge clk or posedge rst)\n");
657 
    GEN ("begin\n");
658 
    GEN ("  if (rst) begin\n");
659 
    GEN ("    f_stb <= #Tp %i'h0;\n", nstores);
660 
    for (i = 0; i < 6; i++) GEN ("    fr%i_o <= #Tp 32'h0;\n", i + 3);
661 
    if (log2_int(ncalls)) GEN ("    fid_o <= #Tp %i'h0;\n", log2_int (f->nfdeps));
662 
    GEN ("    fstart_o <= #Tp 1'b0;\n");
663 
    //GEN ("    f11_r <= #Tp 32'h0;\n");
664 
    GEN ("  end else begin\n");
665 
    cucdebug (1, "calls \n");
666 
    for (i = 0; i < f->nmsched; i++) if (f->mtype[i] & MT_CALL) {
667 
      dep_list *dep = f->INSN(f->msched[i]).dep;
668 
      cucdebug (1, "msched[%i] = %x (mtype %x)\n", i, f->msched[i], f->mtype[i]);
669 
      assert (f->INSN(f->msched[i]).opt[1] & (OPT_REF | OPT_REGISTER));
670 
      GEN ("    if (");
671 
      print_deps (fo, f, REF_BB(f->msched[i]), f->INSN(f->msched[i]).dep, 1);
672 
      GEN (") begin\n");
673 
      print_turn_off_dep (fo, f, dep);
674 
      GEN ("      f_stb[%i] <= #Tp 1'b1;\n", cur_call++);
675 
      GEN ("      fstart_o <= #Tp 1'b1;\n");
676 
      if (log2_int (f->nfdeps))
677 
        GEN ("      fid_o <= #Tp %i'h%x;\n", log2_int (f->nfdeps), func_index (f, f->msched[i]));
678 
 
679 
      for (j = 0; j < 6; j++)
680 
        GEN ("      fr%i_o <= #Tp t%x_%x;\n", j + 3,
681 
                       REF_BB (f->msched[i]), REF_I (f->msched[i]) - 6 + i);
682 
      GEN ("    end\n");
683 
    }
684 
    GEN ("    if (f_end[%i]) begin\n", ncalls - 1);
685 
    GEN ("      f_stb <= #Tp %i'h0;\n", ncalls);
686 
    GEN ("      f_start_o <= #Tp 1'b0;\n");
687 
    GEN ("    end\n");
688 
    GEN ("  end\n");
689 
    GEN ("end\n");
690 
  }
691 
 
692 
  GEN ("\n/* Basic blocks state machine */\n");
693 
  GEN ("always @(posedge clk or posedge rst)\n");
694 
  GEN ("begin\n");
695 
  GEN ("  if (rst) bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
696 
  GEN ("  else if (end_o) begin\n");
697 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
698 
  for (i = 0; i < f->num_bb; i++) {
699 
    GEN ("  end else if (bb_start[%i]) begin\n", i);
700 
    GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 1 << i);
701 
  }
702 
  GEN ("  end else if (end_o) begin\n");
703 
  GEN ("    bb_stb <= #Tp %i'h%x;\n", f->num_bb, 0);
704 
  GEN ("  end\n");
705 
  GEN ("end\n");
706 
 
707 
  /* output footer */
708 
  GEN ("\nendmodule\n");
709 
 
710 
  fclose (fo);
711 
}
712 
 
713 
void generate_main (int nfuncs, cuc_func **f, char *filename)
714 
{
715 
  FILE *fo;
716 
  int i, j, nrf, first;
717 
  char tmp[256];
718 
  int ncallees[MAX_FUNCS];
719 
  int nl[MAX_FUNCS], ns[MAX_FUNCS];
720 
  int maxncallees = 0;
721 
  sprintf (tmp, "%s_top.v", filename);
722 
 
723 
  for (i = 0, nrf = 0; i < nfuncs; i++) {
724 
    nl[i] = ns[i] = 0;
725 
    ncallees[i] = 0;
726 
    if (f[i]) {
727 
      f[i]->tmp = nrf++;
728 
      for (j = 0; j < f[i]->nmsched; j++)
729 
        if (f[i]->mtype[j] & MT_LOAD) nl[i]++;
730 
        else if (f[i]->mtype[j] & MT_STORE) ns[i]++;
731 
      for (j = 0; j < f[i]->nfdeps; j++)
732 
        ncallees[f[i]->fdeps[j]->tmp]++;
733 
    }
734 
  }
735 
  if (!nrf) return;
736 
 
737 
  for (i = 0; i < nrf; i++)
738 
    if (maxncallees < ncallees[i]) maxncallees = ncallees[i];
739 
 
740 
  log ("Generating verilog file \"%s\"\n", tmp);
741 
  PRINTF ("Generating verilog file \"%s\"\n", tmp);
742 
  if ((fo = fopen (tmp, "wt+")) == NULL) {
743 
    fprintf (stderr, "Cannot open '%s'\n", tmp);
744 
    exit (1);
745 
  }
746 
 
747 
  /* output header */
748 
  GEN ("/* %s -- generated by Custom Unit Compiler\n", tmp);
749 
  GEN ("   (C) 2002 Opencores */\n\n");
750 
  GEN ("/* Includes %i functions:", nrf);
751 
  for (i = 0; i < nfuncs; i++) if (f[i])
752 
    GEN ("\n%s", prof_func[i].name);
753 
  GEN (" */\n\n");
754 
 
755 
  GEN ("`include \"timescale.v\"\n\n");
756 
  GEN ("module %s (clk, rst,\n", filename);
757 
  GEN ("              /* Load and store master Wishbone ports */\n");
758 
  GEN ("              l_adr_o, l_dat_i, l_cyc_o, l_stb_o,\n");
759 
  GEN ("              l_sel_o, l_linbrst_o, l_rdy_i, l_we_o,\n");
760 
  GEN ("              s_adr_o, s_dat_o, s_cyc_o, s_stb_o,\n");
761 
  GEN ("              s_sel_o, s_linbrst_o, s_rdy_i, s_we_o,\n\n");
762 
  GEN ("              /* cuc interface */\n");
763 
  GEN ("              cuc_stb_i, cuc_adr_i, cuc_dat_i, cuc_dat_o, cuc_we_i, cuc_rdy_o);\n\n");
764 
 
765 
  GEN ("parameter Tp = 1;\n");
766 
  GEN ("\n/* module ports */\n");
767 
  GEN ("input         clk, rst, cuc_stb_i, cuc_we_i;\n");
768 
  GEN ("input         l_rdy_i, s_rdy_i;\n");
769 
  GEN ("output        l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
770 
  GEN ("reg           l_cyc_o, l_stb_o, l_we_o, l_linbrst_o;\n");
771 
  GEN ("output        s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
772 
  GEN ("reg           s_cyc_o, s_stb_o, s_we_o, s_linbrst_o;\n");
773 
  GEN ("output        cuc_rdy_o; /* Not registered ! */\n");
774 
  GEN ("output  [3:0] l_sel_o, s_sel_o;\n");
775 
  GEN ("reg     [3:0] l_sel_o, s_sel_o;\n");
776 
  GEN ("output [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
777 
  GEN ("reg    [31:0] l_adr_o, s_adr_o, s_dat_o, cuc_dat_o;\n");
778 
  GEN ("input  [15:0] cuc_adr_i;\n");
779 
  GEN ("input  [31:0] l_dat_i, cuc_dat_i;\n\n");
780 
 
781 
  GEN ("wire   [%2i:0] i_we, i_re, i_finish, i_selected, i_first_reg;\n", nrf - 1);
782 
  GEN ("wire   [%2i:0] i_bidok, i_start_bid, i_start_bidok, main_start, main_end;\n", nrf - 1);
783 
  GEN ("wire   [%2i:0] i_start, i_end, i_start_block, i_busy;\n", nrf - 1);
784 
  GEN ("wire   [%2i:0] i_l_req, i_s_req;\n", nrf - 1);
785 
  GEN ("reg    [%2i:0] i_go_bsy, main_start_r;\n", nrf - 1);
786 
 
787 
  GEN ("assign i_selected = {\n");
788 
  for (i = 0; i < nrf; i++)
789 
    GEN ("    cuc_adr_i[15:6] == %i%s\n", i, i < nrf - 1 ? "," : "};");
790 
 
791 
  GEN ("assign i_first_reg = {\n");
792 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
793 
    for (j = 0; j <= MAX_REGS; j++) if (f[i]->used_regs[j]) break;
794 
    GEN ("    cuc_adr_i[5:0] == %i%s\n", j, f[i]->tmp < nrf - 1 ? "," : "};");
795 
  }
796 
 
797 
  GEN ("assign i_we = {%i{cuc_stb_i && cuc_we_i}} & i_selected;\n", nrf);
798 
  GEN ("assign i_re = {%i{cuc_stb_i && !cuc_we_i}} & i_selected;\n", nrf);
799 
 
800 
  GEN ("assign i_start = i_go_bsy & {%i{cuc_rdy_o}};\n", nrf);
801 
  GEN ("assign i_start_bidok = {\n");
802 
  for (i = 0; i < nrf; i++)
803 
    GEN ("    i_start_bid[%i] < %i%s\n", i, i, i < nrf - 1 ? "," : "};");
804 
  GEN ("assign main_start = i_start & i_selected & i_first_reg & i_we;\n");
805 
  GEN ("assign main_end = {%i{i_end}} & i_selected;\n");
806 
 
807 
  GEN ("\nalways @(posedge clk or posedge rst)\n");
808 
  GEN ("begin\n");
809 
  GEN ("  if (rst) i_go_bsy <= #Tp %i'b0;\n", nrf);
810 
  GEN ("  else i_go_bsy <= #Tp i_we | ~i_finish & i_go_bsy;\n");
811 
  GEN ("end\n");
812 
 
813 
 
814 
  /* Function specific data */
815 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
816 
    int ci = 0, co = 0;
817 
    int fn = f[i]->tmp;
818 
    GEN ("\n/* Registers for function %s */\n", prof_func[i].name);
819 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j]) {
820 
      GEN ("%s i%i_r%ii", first ? "/* inputs */\nreg    [31:0]" : ",", fn, j);
821 
      first = 0;
822 
      ci++;
823 
    }
824 
    if (ci) GEN (";\n");
825 
 
826 
    for (j = 0, first = 1; j < MAX_REGS; j++)
827 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) {
828 
        GEN ("%s i%i_r%io", first ? "/* outputs */\nwire   [31:0]" : ",", fn, j);
829 
        first = 0;
830 
        co++;
831 
      }
832 
    if (co) GEN (";\n");
833 
    GEN ("wire [31:0] i%i_l_adr, i%i_s_adr;\n", fn, fn);
834 
 
835 
    GEN ("always @(posedge clk or posedge rst)\n");
836 
    GEN ("  if (rst) main_start_r <= #Tp %i'b0;\n", nrf);
837 
    GEN ("  else main_start_r <= #Tp main_start & i_start_bidok | i_busy | ~i_end & main_start_r;\n");
838 
 
839 
    if (ci) {
840 
      GEN ("\n/* write register access */\n");
841 
      GEN ("always @(posedge clk or posedge rst)\n");
842 
      GEN ("begin\n");
843 
      GEN ("  if (rst) begin\n");
844 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
845 
        GEN ("    i%i_r%ii <= #Tp 32'h0;\n", fn, j);
846 
      GEN ("  end else if (!i_go_bsy[%i] && i_we[%i])\n", fn, fn);
847 
      GEN ("    case (cuc_adr_i[5:0])\n");
848 
      for (j = 0; j < MAX_REGS; j++) if (f[i]->used_regs[j])
849 
        GEN ("      %-2i: i%i_r%ii <= #Tp cuc_dat_i;\n", j, fn, j);
850 
      GEN ("    endcase\n");
851 
      GEN ("end\n");
852 
    }
853 
 
854 
    GEN ("\n");
855 
  }
856 
 
857 
  /* Generate machine for reading all function registers. Register read can be
858 
     delayed till function completion */
859 
  {
860 
    int co;
861 
    GEN ("/* read register access - data */\n");
862 
    GEN ("always @(posedge clk or posedge rst)\n");
863 
    GEN ("  if (rst) cuc_dat_o <= #Tp 32'h0;\n");
864 
    GEN ("  else if (cuc_stb_i && cuc_we_i) begin\n");
865 
    GEN ("    ");
866 
 
867 
    for (i = 0; i < nfuncs; i++) if (f[i]) {
868 
      co = 0;
869 
      for (j = 0; j < MAX_REGS; j++)
870 
        if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j]) co++;
871 
 
872 
      GEN ("if (cuc_adr_i[15:6] == %i)", f[i]->tmp);
873 
      if (co) {
874 
        first = 1;
875 
        GEN ("\n      case (cuc_adr_i[5:0])\n");
876 
        for (j = 0; j < MAX_REGS; j++)
877 
          if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
878 
            GEN ("        %-2i: cuc_dat_o <= #Tp i%i_r%io;\n", j, f[i]->tmp, j);
879 
        GEN ("      endcase\n");
880 
      } else {
881 
        GEN ("      cuc_dat_o <= #Tp 32'hx;\n");
882 
      }
883 
      GEN ("    else ");
884 
    }
885 
    GEN ("cuc_dat_o <= #Tp 32'hx;\n");
886 
    GEN ("  end else cuc_dat_o <= #Tp 32'hx;\n");
887 
 
888 
    GEN ("\n/* read register access - acknowledge */\n");
889 
    GEN ("assign cuc_rdy_o = cuc_stb_i && cuc_we_i && |(i_selected & main_end);\n");
890 
  }
891 
 
892 
  /* Store/load Wishbone bridge */
893 
  for (j = 0; j < 2; j++) {
894 
    char t = j ? 's' : 'l';
895 
    GEN ("\n/* %s Wishbone bridge */\n", j ? "store" : "load");
896 
    GEN ("reg [%i:0] %cm_sel;\n", log2_int (nrf), t);
897 
    GEN ("reg [%i:0] %cm_bid;\n", log2_int (nrf), t);
898 
    GEN ("reg       %ccyc_ip;\n\n", t);
899 
    GEN ("always @(posedge clk)\n");
900 
    GEN ("begin\n");
901 
    GEN ("  %c_we_o <= #Tp 1'b%i;\n", t, j);
902 
    GEN ("  %c_cyc_o <= #Tp |i_%c_req;\n", t, t);
903 
    GEN ("  %c_stb_o <= #Tp |i_%c_req;\n", t, t);
904 
    GEN ("end\n");
905 
 
906 
    GEN ("\n/* highest bid */\n");
907 
    GEN ("always @(");
908 
    for (i = 0; i < nrf; i++) GEN ("%si_%c_req", i > 0 ? " or " : "", t);
909 
    GEN (")\n");
910 
    for (i = 0; i < nrf; i++) GEN ("  %sif (i_%c_req) %cm_bid = %i'h%x;\n",
911 
                    i ? "else " : "", t, t, log2_int (nrf) + 1, i);
912 
 
913 
    GEN ("\n/* selected transfer */\n");
914 
    GEN ("always @(posedge clk or posedge rst)\n");
915 
    GEN ("  if (rst) %cm_sel <= #Tp %i'h0;\n", t, log2_int (nrf) + 1);
916 
    GEN ("  else if (%c_rdy_i) %cm_sel <= #Tp %i'h0;\n", t, t, log2_int (nrf) + 1);
917 
    GEN ("  else if (!%ccyc_ip) %cm_sel <= #Tp %cm_bid;\n", t, t, t);
918 
 
919 
    GEN ("\n/* Cycle */\n");
920 
    GEN ("\nalways @(posedge clk or posedge rst)\n");
921 
    GEN ("  if (rst) %ccyc_ip <= #Tp 1'b0;\n", t);
922 
    GEN ("  else if (%c_rdy_i) %ccyc_ip <= #Tp 1'b0;\n", t, t);
923 
    GEN ("  else %ccyc_ip <= #Tp %c_cyc_o;\n", t, t);
924 
  }
925 
 
926 
  GEN ("\n/* Acknowledge */\n");
927 
  for (i = 0; i < nrf; i++) {
928 
    GEN ("wire i%i_s_rdy = ((sm_bid == %i & !scyc_ip) | sm_sel == %i) & s_rdy_i;\n", i, i, i);
929 
    GEN ("wire i%i_l_rdy = ((lm_bid == %i & !lcyc_ip) | lm_sel == %i) & l_rdy_i;\n", i, i, i);
930 
  }
931 
 
932 
  GEN ("\n/* data, address selects and burst enables */\n");
933 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_s_dat;\n", i);
934 
  for (i = 0; i < nrf; i++) GEN ("wire i%i_s_linbrst, i%i_l_linbrst;\n", i, i);
935 
  for (i = 0; i < nrf; i++) GEN ("wire [3:0]  i%i_s_sel, i%i_l_sel;\n", i, i);
936 
  for (i = 0; i < nrf; i++) GEN ("wire [31:0] i%i_l_dat = l_dat_i;\n", i);
937 
  GEN ("\nalways @(posedge clk)\n");
938 
  GEN ("begin\n");
939 
  GEN ("  s_dat_o <= #Tp ");
940 
  for (i = 0; i < nrf - 1; i++)
941 
    GEN ("\n    sm_bid == %i ? i%i_s_dat : ", i, i);
942 
  GEN ("i%i_s_dat;\n", nrf - 1);
943 
  GEN ("  s_adr_o <= #Tp ");
944 
  for (i = 0; i < nrf - 1; i++)
945 
    GEN ("\n    sm_bid == %i ? i%i_s_adr : ", i, i);
946 
  GEN ("i%i_s_adr;\n", nrf - 1);
947 
  GEN ("  s_sel_o <= #Tp ");
948 
  for (i = 0; i < nrf - 1; i++)
949 
    GEN ("\n    sm_bid == %i ? i%i_s_sel : ", i, i);
950 
  GEN ("i%i_s_sel;\n", nrf - 1);
951 
  GEN ("  s_linbrst_o <= #Tp ");
952 
  for (i = 0; i < nrf - 1; i++)
953 
    GEN ("\n    sm_bid == %i ? i%i_s_linbrst : ", i, i);
954 
  GEN ("i%i_s_linbrst;\n", nrf - 1);
955 
  GEN ("end\n\n");
956 
 
957 
  GEN ("always @(posedge clk)\n");
958 
  GEN ("begin\n");
959 
  GEN ("  l_adr_o <= #Tp ");
960 
  for (i = 0; i < nrf - 1; i++)
961 
    GEN ("\n    lm_bid == %i ? i%i_l_adr : ", i, i);
962 
  GEN ("i%i_l_adr;\n", nrf - 1);
963 
  GEN ("  l_sel_o <= #Tp ");
964 
  for (i = 0; i < nrf - 1; i++)
965 
    GEN ("\n    lm_bid == %i ? i%i_l_sel : ", i, i);
966 
  GEN ("i%i_l_sel;\n", nrf - 1);
967 
  GEN ("  l_linbrst_o <= #Tp ");
968 
  for (i = 0; i < nrf - 1; i++)
969 
    GEN ("\n    lm_bid == %i ? i%i_l_linbrst : ", i, i);
970 
  GEN ("i%i_l_linbrst;\n", nrf - 1);
971 
  GEN ("end\n\n");
972 
 
973 
  /* start/end signals */
974 
  GEN ("\n\n/* start/end signals */\n");
975 
  for (i = 0; i < nrf; i++) {
976 
    if (log2_int (maxncallees + 1))
977 
      GEN ("wire [%i:0] i%i_current = i%i_busy ? i%i_current_r : i%i_start_bid;\n",
978 
        log2_int (maxncallees + 1), i, i, i, i, i);
979 
    else GEN ("wire i%i_current = 0;\n", i);
980 
  }
981 
  GEN ("\n");
982 
 
983 
  for (i = 0, j = 0; i < nfuncs; i++) if (f[i]) {
984 
    if (log2_int (ncallees[i])) {
985 
      GEN ("reg [%i:0] i%i_start_bid;\n", log2_int (ncallees[i]), j);
986 
      GEN ("always @(start%i", f[i]->tmp);
987 
      for (j = 0, first = 1; j < f[i]->nfdeps; j++)
988 
        if (f[i]->fdeps[j]) GEN (", ");
989 
      GEN (")\n");
990 
      GEN ("begin !!!\n"); //TODO
991 
      GEN ("  \n");
992 
      GEN ("end\n");
993 
    }
994 
    GEN ("wire i%i_start = main_start[%i];\n", j, j);
995 
    j++;
996 
  }
997 
  GEN ("\n");
998 
 
999 
  for (i = 0; i < nfuncs; i++) if (f[i]) {
1000 
    int nf = f[i]->tmp;
1001 
    GEN ("\n%s%s i%i(.clk(clk), .rst(rst),\n", filename, prof_func[i].name, nf);
1002 
    GEN ("  .l_adr_o(i%i_l_adr), .l_dat_i(i%i_l_dat), .l_req_o(i_l_req[%i]),\n",
1003 
                    nf, nf, nf);
1004 
    GEN ("  .l_sel_o(i%i_l_sel), .l_linbrst_o(i%i_l_linbrst), .l_rdy_i(i%i_l_rdy),\n",
1005 
                    nf, nf, nf);
1006 
    GEN ("  .s_adr_o(i%i_s_adr), .s_dat_o(i%i_s_dat), .s_req_o(i_s_req[%i]),\n",
1007 
                    nf, nf, nf);
1008 
    GEN ("  .s_sel_o(i%i_s_sel), .s_linbrst_o(i%i_s_linbrst), .s_rdy_i(i%i_s_rdy),\n",
1009 
                    nf, nf, nf);
1010 
    GEN ("  ");
1011 
    for (j = 0, first = 1; j < MAX_REGS; j++) if (f[i]->used_regs[j])
1012 
      GEN (".r%i_i(i%i_r%ii), ", j, nf, j), first = 0;
1013 
 
1014 
    if (first) GEN ("\n  ");
1015 
    for (j = 0, first = 1; j < MAX_REGS; j++)
1016 
      if (f[i]->lur[j] >= 0 && !f[i]->saved_regs[j])
1017 
        GEN (".r%i_o(i%i_r%io), ", j, nf, j), first = 0;
1018 
    if (first) GEN ("\n  ");
1019 
    if (f[i]->nfdeps) {
1020 
      GEN (".fstart_o(i_fstart[%i]), .fend_i(i_fend[%i]), .fid_o(i%i_fid),\n", i, i, i),
1021 
      GEN ("  .fr3_o(i%i_fr3), .fr4_o(i%i_fr4), .fr5_o(i%i_fr5), .fr6_o(i%i_fr6),\n");
1022 
      GEN ("  .fr7_o(i%i_fr7), .fr8_o(i%i_fr8), .fr11_i(i%i_fr11i),\n  ");
1023 
    }
1024 
    GEN (".start_i(i_start[%i]), .end_o(i_end[%i]), .busy_o(i_busy[%i]));\n", nf, nf, nf);
1025 
  }
1026 
 
1027 
  /* output footer */
1028 
  GEN ("\nendmodule\n");
1029 
 
1030 
  fclose (fo);
1031 
}
1032 
 

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