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/* dumpverilog.c -- Dumps memory region as Verilog representation

   or as hex code

   Copyright (C) 2000 Damjan Lampret, lampret@opencores.org

This file is part of OpenRISC 1000 Architectural Simulator.

This program is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 2 of the License, or

(at your option) any later version.

This program is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

You should have received a copy of the GNU General Public License

along with this program; if not, write to the Free Software

Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */

/* Verilog dump can be used for stimulating OpenRISC Verilog RTL models. */

#include <stdio.h>

#include <ctype.h>

#include <string.h>

#include "config.h"

#ifdef HAVE_INTTYPES_H

#include <inttypes.h>

#endif

#include "port.h"

#include "arch.h"

#include "sim-config.h"

#include "parse.h"

#include "abstract.h"

#include "opcode/or32.h"

#include "spr_defs.h"

#include "labels.h"

#include "execute.h"

#include "sprs.h"

#include "stats.h"

#include "except.h"

#include "dumpverilog.h"

extern char rcsrev[];

extern char *disassembled;

void dumpverilog(char *verilog_modname, unsigned int from, unsigned int to)

{

  unsigned int i, done = 0;

  struct label_entry *tmp;

  char dis[DISWIDTH + 100];

  PRINTF("// This file was generated by or1ksim %s\n", rcsrev);

  PRINTF(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8)));

  for(i = from; i < to; i++)

    {

      unsigned int _insn = evalsim_mem32 (i);

      int index = insn_decode(_insn);

      if (index >= 0)

        {

          if (verify_memoryarea(i) && (tmp = get_label(i)))

          if (tmp)

            PRINTF("\n//\t%s%s", tmp->name, LABELEND_CHAR);

          PRINTF("\n\tmem['h%x] = %d'h%.8"PRIx32";", i/DWQ, DW, evalsim_mem32(i));

          disassemble_insn (_insn);

          strcpy (dis, disassembled);

          if (strlen(dis) < DISWIDTH)

            memset(dis + strlen(dis), ' ', DISWIDTH);

          dis[DISWIDTH] = '\0';

          PRINTF("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis);

          dis[0] = '\0';

          i += insn_len(index) - 1;

        } else {

          if (i % 64 == 0)

            PRINTF("\n");

          PRINTF("\n\tmem['h%x] = 'h%.2x;", i/DWQ, evalsim_mem8(i));

        }

      done = 1;

    }

  if (done)

    {

      PRINTF(OR1K_MEM_VERILOG_FOOTER);

      return;

    }

  /* this needs to be fixed */

  for(i = from; i < to; i++)

    {

      if (i % 8 == 0)

        PRINTF("\n%.8x:  ", i);

      /* don't print ascii chars below 0x20. */

      if (evalsim_mem32(i) < 0x20)

        PRINTF("0x%.2x     ", (unsigned char)evalsim_mem32(i));

      else

        PRINTF("0x%.2x'%c'  ", (unsigned char)evalsim_mem32(i), (unsigned char)evalsim_mem32(i));

    }

  PRINTF(OR1K_MEM_VERILOG_FOOTER);

}

void dumphex(unsigned int from, unsigned int to)

{

  unsigned int i;

  for(i = from; i < to; i++) {

    unsigned int _insn = evalsim_mem32 (i);

    int index = insn_decode(_insn);

    if (index >= 0)

      {

              PRINTF("%.8"PRIx32"\n", evalsim_mem32(i));

              i += insn_len(index) - 1;

      }

    else

      PRINTF("%.2x\n", evalsim_mem8(i));

  }

}