OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_70/] [or1ksim/] [testbench/] [mc_dram.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 454 ivang 
/* mc_dram.h - Memory Controller testbench SDRAM defines
2 
         Copyright (C) 2001 by Ivan Guzvinec, ivang@opencores.org
3 
 
4 
         This file is part of OpenRISC 1000 Architectural Simulator.
5 
 
6 
         This program is free software; you can redistribute it and/or modify
7 
         it under the terms of the GNU General Public License as published by
8 
         the Free Software Foundation; either version 2 of the License, or
9 
         (at your option) any later version.
10 
 
11 
         This program is distributed in the hope that it will be useful,
12 
         but WITHOUT ANY WARRANTY; without even the implied warranty of
13 
         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
14 
         GNU General Public License for more details.
15 
 
16 
         You should have received a copy of the GNU General Public License
17 
         along with this program; if not, write to the Free Software
18 
         Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 
*/
20 
 
21 
#ifndef __MC_DRAM_H
22 
#define __MC_DRAM_H
23 
 
24 552 ivang 
/* should configuration be read from MC? */
25 
#define  MC_READ_CONF
26 
 
27 454 ivang 
/* TEMPLATE SELECTION       */
28 
/* change #undef to #define */
29 552 ivang 
#undef  _MC_TEST_TEMPLATE1
30 
#define _MC_TEST_TEMPLATE2
31 454 ivang 
#undef  _MC_TEST_TEMPLATE3
32 
/* ------------------------ */
33 
 
34 
 
35 552 ivang 
/* memory configuration that must reflect sim.cfg */
36 454 ivang 
#define MC_SDRAM_CSMASK 0x02    /* 8 bit mask for 8 chip selects. 1 SDRAM at CS, 0 something else at CS */
37 
                                /* bits: CS7|CS6|CS5|CS4|CS3|CS2|CS1|CS0 */
38 
typedef struct MC_SDRAM_CS
39 
{
40 
  unsigned long BW;
41 
  unsigned long MS;
42 
  unsigned long M;
43 
} MC_SDRAM_CS;
44 
 
45 
MC_SDRAM_CS mc_sdram_cs[8] = {
46 
  { 2,    /* Bus Width : 0 - 8bit, 1 - 16bit, 2 - 32bit */
47 552 ivang 
    2,    /* Memory Size : 0 - 64Mbit, 1 - 128Mbit, 2 - 256Mbit */
48 
    0x20  /* SELect mask */
49 454 ivang 
    },
50 552 ivang 
  { 1, 0, 0x20 },
51 454 ivang 
  { 2, 0, 0x06 },
52 
  { 2, 0, 0x08 },
53 
  { 2, 0, 0x0A },
54 
  { 2, 0, 0x0C },
55 
  { 2, 0, 0x0E },
56 
  { 2, 0, 0x10 } };
57 
 
58 
/* SDRAM configuration tests flag defines */
59 
#define MC_SDRAM_TEST0  0x00000001LU /*no parity, close row, BankAfterCol, R/W, single loc, seq. burst 1 */
60 
#define MC_SDRAM_TEST1  0x00000002LU /*parity enabled*/
61 
#define MC_SDRAM_TEST2  0x00000004LU /*keep row*/
62 
#define MC_SDRAM_TEST3  0x00000008LU /*BankAfterRow*/
63 
#define MC_SDRAM_TEST4  0x00000010LU /*RO*/
64 
#define MC_SDRAM_TEST5  0x00000020LU /*prog. burst 1*/
65 
#define MC_SDRAM_TEST6  0x00000040LU /*  -||-  2*/
66 
#define MC_SDRAM_TEST7  0x00000080LU /*  -||-  4*/
67 
#define MC_SDRAM_TEST8  0x00000100LU /*  -||-  8*/
68 
#define MC_SDRAM_TEST9  0x00000200LU /*  -||-  fullpage*/
69 
#define MC_SDRAM_TEST10 0x00000400LU /*prog. burst int. 1*/
70 
#define MC_SDRAM_TEST11 0x00000800LU /*  -||-  2*/
71 
#define MC_SDRAM_TEST12 0x00001000LU /*  -||-  4*/
72 
#define MC_SDRAM_TEST13 0x00002000LU /*  -||-  8*/
73 
#define MC_SDRAM_TEST14 0x00004000LU /*  -||-  fullpage*/
74 
#define MC_SDRAM_TEST15 0x00008000LU /*prog. burst int. fullpage, keep row*/
75 
#define MC_SDRAM_TEST16 0x00010000LU /* NOT DEFINED */
76 
 
77 
/* test type flag defines */
78 
#define MC_SDRAM_SROW   0x00000001LU /* perform sequential row access test */
79 
#define MC_SDRAM_RROW   0x00000010LU /* perform random row access test     */
80 
#define MC_SDRAM_SGRP   0x00000100LU /* perform sequential row-group access test */
81 
#define MC_SDRAM_RGRP   0x00001000LU /* perform random row-group access test */
82 
 
83 
#define MC_SDRAM_ROWSH_0        16
84 
#define MC_SDRAM_ROWSH_1        16
85 
#define MC_SDRAM_ROWSH_2        15
86 
#define MC_SDRAM_ROWSH_3        16
87 
#define MC_SDRAM_ROWSH_4        16
88 
#define MC_SDRAM_ROWSH_5        16
89 
#define MC_SDRAM_ROWSH_6        17
90 
#define MC_SDRAM_ROWSH_7        17
91 
#define MC_SDRAM_ROWSH_8        17
92 
 
93 
 
94 
/* TEMPLATE 1 */
95 
#ifdef _MC_TEST_TEMPLATE1
96 
 #define MC_SDRAM_FLAGS 0x000004A8LU    /* MC_TEST_ flags... see mc_common.h */
97 
 #define MC_SDRAM_TESTS 0x00000001LU    /* mask for SDRAM configuration, see conf. test flag defines */
98 
 #define MC_SDRAM_ACC   0x00001010LU    /* mask for test types */
99 
 
100 
 /* memory sizes*/
101 
 #define MC_SDRAM_GROUPSIZE     5
102 
                                   /* MAX */
103 
 #define MC_SDRAM_ROWSIZE_0     8/*  16 * 1024 * 4 */
104 
 #define MC_SDRAM_ROWSIZE_1     8/*  16 * 1024 * 4 */
105 
 #define MC_SDRAM_ROWSIZE_2     8/*   8 * 1024 * 4 */
106 
 #define MC_SDRAM_ROWSIZE_3     8/*  16 * 1024 * 4 */
107 
 #define MC_SDRAM_ROWSIZE_4     8/*  16 * 1024 * 4 */
108 
 #define MC_SDRAM_ROWSIZE_5     8/*  16 * 1024 * 4 */
109 
 #define MC_SDRAM_ROWSIZE_6     8/*  32 * 1024 * 4 */
110 
 #define MC_SDRAM_ROWSIZE_7     8/*  32 * 1024 * 4 */
111 
 #define MC_SDRAM_ROWSIZE_8     8/*  32 * 1024 * 4 */
112 
                                  /*  MAX */
113 
 #define MC_SDRAM_ROWS_0        25/*  512 */
114 
 #define MC_SDRAM_ROWS_1        25/*  256 */
115 
 #define MC_SDRAM_ROWS_2        25/*  256 */
116 
 #define MC_SDRAM_ROWS_3        25/*  1024 */
117 
 #define MC_SDRAM_ROWS_4        25/*  512 */
118 
 #define MC_SDRAM_ROWS_5        25/*  256 */
119 
 #define MC_SDRAM_ROWS_6        25/*  1024 */
120 
 #define MC_SDRAM_ROWS_7        25/*  512 */
121 
 #define MC_SDRAM_ROWS_8        25/*  256 */
122 
 
123 552 ivang 
 #define MC_SDRAM_ROW_OFF       5
124 454 ivang 
#endif /*_MC_TEST_TEMPLATE1*/
125 
 
126 
/* TEMPLATE 2 */
127 
#ifdef _MC_TEST_TEMPLATE2
128 
 #define MC_SDRAM_FLAGS 0x000004A8LU    /* MC_TEST_ flags... see mc_common.h */
129 
 #define MC_SDRAM_TESTS 0x00000001LU    /* mask for SDRAM configuration, see conf. test flag defines */
130 
 #define MC_SDRAM_ACC   0x00001010LU    /* mask for test types */
131 
 
132 
 /* memory sizes*/
133 
 #define MC_SDRAM_GROUPSIZE     5
134 552 ivang 
 
135 
 #define MC_SDRAM_ROWSIZE_0     16 * 1024 * 4
136 
 #define MC_SDRAM_ROWSIZE_1     16 * 1024 * 4
137 
 #define MC_SDRAM_ROWSIZE_2      8 * 1024 * 4
138 
 #define MC_SDRAM_ROWSIZE_3     16 * 1024 * 4
139 
 #define MC_SDRAM_ROWSIZE_4     16 * 1024 * 4
140 
 #define MC_SDRAM_ROWSIZE_5     16 * 1024 * 4
141 
 #define MC_SDRAM_ROWSIZE_6     32 * 1024 * 4
142 
 #define MC_SDRAM_ROWSIZE_7     32 * 1024 * 4
143 
 #define MC_SDRAM_ROWSIZE_8     32 * 1024 * 4
144 
 
145 
 #define MC_SDRAM_ROWS_0         512
146 
 #define MC_SDRAM_ROWS_1         256
147 
 #define MC_SDRAM_ROWS_2         256
148 
 #define MC_SDRAM_ROWS_3        1024
149 
 #define MC_SDRAM_ROWS_4         512
150 
 #define MC_SDRAM_ROWS_5         256
151 
 #define MC_SDRAM_ROWS_6        1024
152 
 #define MC_SDRAM_ROWS_7         512
153 
 #define MC_SDRAM_ROWS_8         256
154 454 ivang 
 
155 
#endif /*_MC_TEST_TEMPLATE2*/
156 
 
157 
/* TEMPLATE 3 */
158 
#ifdef _MC_TEST_TEMPLATE3
159 
 #define MC_SDRAM_FLAGS 0x000004A8LU    /* MC_TEST_ flags... see mc_common.h */
160 
 #define MC_SDRAM_TESTS 0x00000001LU    /* mask for SDRAM configuration, see conf. test flag defines */
161 
 #define MC_SDRAM_ACC   0x00001010LU    /* mask for test types */
162 
 
163 
 /* memory sizes*/
164 
 #define MC_SDRAM_GROUPSIZE     5
165 
                                 /* MAX */
166 552 ivang 
 #define MC_SDRAM_ROWSIZE_0     16 * 1024 * 4
167 
 #define MC_SDRAM_ROWSIZE_1     16 * 1024 * 4
168 
 #define MC_SDRAM_ROWSIZE_2      8 * 1024 * 4
169 
 #define MC_SDRAM_ROWSIZE_3     16 * 1024 * 4
170 
 #define MC_SDRAM_ROWSIZE_4     16 * 1024 * 4
171 
 #define MC_SDRAM_ROWSIZE_5     16 * 1024 * 4
172 
 #define MC_SDRAM_ROWSIZE_6     32 * 1024 * 4
173 
 #define MC_SDRAM_ROWSIZE_7     32 * 1024 * 4
174 
 #define MC_SDRAM_ROWSIZE_8     32 * 1024 * 4
175 454 ivang 
                                  /*  MAX */
176 552 ivang 
 #define MC_SDRAM_ROWS_0        10/*  512 */
177 
 #define MC_SDRAM_ROWS_1        10/*  256 */
178 
 #define MC_SDRAM_ROWS_2        10/*  256 */
179 
 #define MC_SDRAM_ROWS_3        10/*  1024 */
180 
 #define MC_SDRAM_ROWS_4        10/*  512 */
181 
 #define MC_SDRAM_ROWS_5        10/*  256 */
182 
 #define MC_SDRAM_ROWS_6        10/*  1024 */
183 
 #define MC_SDRAM_ROWS_7        10/*  512 */
184 
 #define MC_SDRAM_ROWS_8        10/*  256 */
185 454 ivang 
 
186 
#endif /*_MC_TEST_TEMPLATE3*/
187 
 
188 
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.