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/* execute.c -- OR1K architecture dependent simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* Most of the OR1K simulation is done in here. */
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <ctype.h>
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#include "arch.h"
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#include "branch_predict.h"
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#include "abstract.h"
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#include "parse.h"
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#include "trace.h"
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#include "execute.h"
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#include "stats.h"
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/* General purpose registers. */
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machword reg[MAX_GPRS];
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/* Instruction queue */
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struct iqueue_entry iqueue[20];
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/* Benchmark multi issue execution */
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int multissue[20];
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int supercycles;
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/* Completition queue */
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struct icomplet_entry icomplet[20];
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/* Program counter */
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unsigned long pc;
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/* Temporary program counter */
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unsigned long pctemp;
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/* CCR */
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int flag;
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/* CCR (for dependency calculation) */
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char ccr_flag[10] = "flag";
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/* Cycles counts fetch stages */
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int cycles;
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/* Implementation specific.
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Get an actual value of a specific register. */
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machword eval_reg(char *regstr)
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{
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int regno;
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regno = atoi(regstr + 1);
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if (regno < MAX_GPRS)
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return reg[regno];
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else {
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printf("\nEXCEPTION: read out of registers\n");
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cont_run = 0;
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return 0;
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}
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}
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/* Implementation specific.
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Set a specific register with value. */
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void set_reg32(char *regstr, unsigned long value)
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{
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int regno;
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#if 0
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if (strcmp(regstr, FRAME_REG) == 0) {
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printf("FP (%s) modified by insn at %x. ", FRAME_REG, pc);
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printf("Old:%.8lx New:%.8lx\n", eval_reg(regstr), value);
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}
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if (strcmp(regstr, STACK_REG) == 0) {
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printf("SP (%s) modified by insn at %x. ", STACK_REG, pc);
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printf("Old:%.8lx New:%.8lx\n", eval_reg(regstr), value);
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}
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#endif
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regno = atoi(regstr + 1);
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if (regno == 0) /* gpr0 is always zero */
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value = 0;
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if (regno < MAX_GPRS)
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reg[regno] = value;
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else {
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printf("\nEXCEPTION: write out of registers\n");
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cont_run = 0;
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}
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return;
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}
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/* Does srcoperand depend on computation of dstoperand? Return
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non-zero if yes.
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Cycle t Cycle t+1
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dst: irrelevant src: immediate always 0
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dst: reg1 direct src: reg2 direct 0 if reg1 != reg2
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dst: reg1 disp src: reg2 direct always 0
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dst: reg1 direct src: reg2 disp 0 if reg1 != reg2
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dst: reg1 disp src: reg2 disp always 1 (store must
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finish before load)
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*/
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int depend_operands(char *dstoperand, char *srcoperand)
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{
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char dst[OPERANDNAME_LEN];
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char src[OPERANDNAME_LEN];
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if (!srcoperand)
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return 0;
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if (!dstoperand)
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return 0;
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strcpy(dst, dstoperand);
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strcpy(src, srcoperand);
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if (*src == '#') /* immediate */
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return 0;
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else
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if (strstr(src, "lo(") || strstr(src, "hi("))
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return 0;
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else
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if (!strstr(src, "("))
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if (*src == 'r') { /* src: reg direct */
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if (!strstr(dst, "("))
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if (*dst == 'r')
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if (strcmp(dst, src) == 0)
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return 1; /* dst: reg direct */
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else
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return 0; /* dst: reg direct */
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else
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return 0; /* dst: addr */
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else
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return 0; /* dst: reg disp */
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} else
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return 0; /* src: addr */
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else { /* src: register disp */
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char *regstr;
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regstr = strstr(src, "(r") + 1; /* regstr == "rXX)" */
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*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
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if (!strstr(dst, "("))
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if (*dst == 'r')
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if (strcmp(dst, regstr) == 0)
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return 1; /* dst: reg direct */
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else
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return 0; /* dst: reg direct */
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else
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return 0; /* dst: addr */
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else
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return 1; /* dst: reg disp */
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}
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return 0;
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}
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/* Implementation specific.
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Get an actual value represented by operand (register direct, register
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indirect (with displacement), immediate etc.).
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#n - immediate n
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rXX - register direct
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XX - relative or absolute address (labels)
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n(XX) - register indirect (with displacement) */
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machword eval_operand(char *srcoperand)
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{
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char operand[OPERANDNAME_LEN];
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strcpy(operand, srcoperand);
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if (*operand == '#') /* immediate */
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return strtoul(&operand[1], NULL, 0);
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else
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if (((*operand == '-') || isdigit(*operand)) && !strstr(operand, "(")) {
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/* immediate */
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return strtoul(operand, NULL, 0);
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} else
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if (strncmp(operand, "lo(", 3) == 0) {
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*strchr(operand, ')') = '\0';
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if ((operand[3] == '-') || isdigit(operand[3]))
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return (unsigned long)strtol(&operand[3], NULL, 0) & 0xffff;
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else
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return eval_operand(&operand[3]) & 0xffff;
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} else
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if (strncmp(operand, "hi(", 3) == 0) {
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*strchr(operand, ')') = '\0';
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if ((operand[3] == '-') || isdigit(operand[3]))
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return (unsigned long)strtol(&operand[3], NULL, 0) >> 16;
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else
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return eval_operand(&operand[3]) >> 16;
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} else
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if (!strstr(operand, "(")) /* not indirect but ...*/
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if (*operand == 'r') /* ... register direct */
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return eval_reg(operand);
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else /* ... rel. or abs. address */
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return eval_label(operand);
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else { /* register indirect */
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int disp; /* with possible displacement */
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char *regstr;
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unsigned int memaddr;
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disp = atoi(operand); /* operand == "nn(rXX)" */
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debug("eval_operand: disp=%u");
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regstr = strstr(operand, "(r") + 1; /* regstr == "rXX)" */
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*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
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debug("eval_operand: regstr=%s", regstr);
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memaddr = eval_reg(regstr) + disp;
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return eval_mem32(memaddr);
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}
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return 0;
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}
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/* Implementation specific.
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Set destination operand (register direct, register indirect
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(with displacement) with value. */
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void set_operand(char *dstoperand, unsigned long value)
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{
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char operand[OPERANDNAME_LEN];
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debug("set_operand %s <= %u\n", dstoperand, value);
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strcpy(operand, dstoperand);
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if (*operand == '#') { /* immediate */
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printf("INTERNAL ERROR: Can't set immediate operand.\n");
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cont_run = 0;
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}
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else
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if (!strstr(operand, "(")) /* not indirect but ...*/
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if (*operand == 'r') /* ... register direct */
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set_reg32(operand, value);
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else { /* ... rel. or abs. address */
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/* printf("INTERNAL ERROR: Can't set addr operand.\n");
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cont_run = 0; */
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set_mem32(eval_label(operand), value);
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}
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else { /* register indirect */
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int disp; /* with possible displacement */
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char *regstr;
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unsigned int memaddr;
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disp = atoi(operand); /* operand == "nn(rXX)" */
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regstr = strstr(operand, "(r") + 1; /* regstr == "rXX)" */
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*strstr(regstr, ")") = '\0'; /* regstr == "rXX" */
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memaddr = eval_reg(regstr) + disp;
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set_mem32(memaddr, value);
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}
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return;
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}
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void reset()
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{
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cycles = 0;
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supercycles = 0;
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memset(reg, 0, sizeof(reg));
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memset(iqueue, 0, sizeof(iqueue));
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memset(icomplet, 0, sizeof(icomplet));
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pctemp = eval_label("_main");
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pc = pctemp;
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debug("reset ...");
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set_reg32(STACK_REG, MEMORY_LEN - STACK_SIZE);
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}
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void fetch()
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{
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/* Cycles after reset. */
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cycles++;
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/* Fetch instruction. */
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strcpy(iqueue[0].insn, mem[pc].insn);
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strcpy(iqueue[0].op1, mem[pc].op1);
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strcpy(iqueue[0].op2, mem[pc].op2);
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strcpy(iqueue[0].op3, mem[pc].op3);
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| 304 |
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strcpy(iqueue[0].op4, mem[pc].op4);
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iqueue[0].insn_addr = pc;
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| 306 |
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iqueue[0].dependdst = NULL;
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| 307 |
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iqueue[0].dependsrc1 = NULL;
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| 308 |
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iqueue[0].dependsrc2 = NULL;
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| 309 |
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| 310 |
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/* Increment program counter. */
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| 311 |
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pc = pctemp;
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pctemp += 4;
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| 314 |
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/* Check for breakpoint. */
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| 315 |
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if (mem[pc].brk)
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cont_run = 0; /* Breakpoint set. */
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| 317 |
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| 318 |
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return;
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| 319 |
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}
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| 320 |
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| 321 |
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void decode(struct iqueue_entry *cur)
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| 322 |
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{
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| 323 |
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| 324 |
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cur->dependdst = cur->op1;
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| 325 |
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cur->dependsrc1 = cur->op2; /* for calculating register */
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| 326 |
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cur->dependsrc2 = cur->op3; /* dependency */
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| 327 |
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| 328 |
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cur->func_unit = unknown;
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| 329 |
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| 330 |
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if (strcmp(cur->insn, "l.stor32") == 0) {
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| 331 |
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cur->func_unit = store;
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| 332 |
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set_operand(cur->op1, eval_operand(cur->op2));
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| 333 |
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} else
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| 334 |
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if (strcmp(cur->insn, "h.stor32") == 0) {
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| 335 |
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cur->func_unit = store;
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| 336 |
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set_operand(cur->op1, eval_operand(cur->op2));
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| 337 |
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} else
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| 338 |
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if (strcmp(cur->insn, "l.stor8") == 0) {
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| 339 |
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cur->func_unit = store;
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| 340 |
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set_operand(cur->op1, (eval_operand(cur->op2) << 24) + (eval_operand(cur->op1) & 0xffffff));
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| 341 |
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} else
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| 342 |
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if (strcmp(cur->insn, "l.stor16") == 0) {
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| 343 |
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cur->func_unit = store;
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| 344 |
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set_operand(cur->op1, (eval_operand(cur->op2) << 16) + (eval_operand(cur->op1) & 0xffff));
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| 345 |
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} else
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| 346 |
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if (strcmp(cur->insn, "l.load32u") == 0) {
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| 347 |
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cur->func_unit = load;
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| 348 |
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set_operand(cur->op1, eval_operand(cur->op2));
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| 349 |
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} else
|
| 350 |
|
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if (strcmp(cur->insn, "h.load32u") == 0) {
|
| 351 |
|
|
cur->func_unit = load;
|
| 352 |
|
|
set_operand(cur->op1, eval_operand(cur->op2));
|
| 353 |
|
|
} else
|
| 354 |
|
|
if (strcmp(cur->insn, "l.load8s") == 0) {
|
| 355 |
|
|
signed char temp = (eval_operand(cur->op2) >> 24);
|
| 356 |
|
|
cur->func_unit = load;
|
| 357 |
|
|
set_operand(cur->op1, temp);
|
| 358 |
|
|
} else
|
| 359 |
|
|
if (strcmp(cur->insn, "l.load8u") == 0) {
|
| 360 |
|
|
unsigned char temp = (eval_operand(cur->op2) >> 24);
|
| 361 |
|
|
cur->func_unit = load;
|
| 362 |
|
|
set_operand(cur->op1, temp);
|
| 363 |
|
|
} else
|
| 364 |
|
|
if (strcmp(cur->insn, "l.load16s") == 0) {
|
| 365 |
|
|
signed short temp = (eval_operand(cur->op2) >> 16);
|
| 366 |
|
|
cur->func_unit = load;
|
| 367 |
|
|
set_operand(cur->op1, temp);
|
| 368 |
|
|
} else
|
| 369 |
|
|
if (strcmp(cur->insn, "l.load16u") == 0) {
|
| 370 |
|
|
unsigned short temp = (eval_operand(cur->op2) >> 16);
|
| 371 |
|
|
cur->func_unit = load;
|
| 372 |
|
|
set_operand(cur->op1, temp);
|
| 373 |
|
|
} else
|
| 374 |
|
|
if (strcmp(cur->insn, "l.immlo16u") == 0) {
|
| 375 |
|
|
cur->func_unit = movimm;
|
| 376 |
|
|
set_operand(cur->op1, (eval_operand(cur->op1) & 0xffff0000) | eval_operand(cur->op2));
|
| 377 |
|
|
} else
|
| 378 |
|
|
if (strcmp(cur->insn, "l.immhi16u") == 0) {
|
| 379 |
|
|
cur->func_unit = movimm;
|
| 380 |
|
|
set_operand(cur->op1, (eval_operand(cur->op1) & 0xffff) | (eval_operand(cur->op2) << 16));
|
| 381 |
|
|
} else
|
| 382 |
|
|
if (strcmp(cur->insn, "h.immch32s") == 0) {
|
| 383 |
|
|
cur->func_unit = movimm;
|
| 384 |
|
|
set_operand(cur->op1, (signed)eval_operand(cur->op2));
|
| 385 |
|
|
} else
|
| 386 |
|
|
if (strcmp(cur->insn, "h.mov32") == 0) {
|
| 387 |
|
|
cur->func_unit = move;
|
| 388 |
|
|
set_operand(cur->op1, eval_operand(cur->op2));
|
| 389 |
|
|
} else
|
| 390 |
|
|
if (strcmp(cur->insn, "l.and32") == 0) {
|
| 391 |
|
|
cur->func_unit = arith;
|
| 392 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) & eval_operand(cur->op3));
|
| 393 |
|
|
} else
|
| 394 |
|
|
if (strcmp(cur->insn, "l.or32") == 0) {
|
| 395 |
|
|
cur->func_unit = arith;
|
| 396 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) | eval_operand(cur->op3));
|
| 397 |
|
|
} else
|
| 398 |
|
|
if (strcmp(cur->insn, "l.xor32") == 0) {
|
| 399 |
|
|
cur->func_unit = arith;
|
| 400 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) ^ eval_operand(cur->op3));
|
| 401 |
|
|
} else
|
| 402 |
|
|
if (strcmp(cur->insn, "l.xori16") == 0) {
|
| 403 |
|
|
cur->func_unit = arith;
|
| 404 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) ^ (eval_operand(cur->op3) & 0xffff));
|
| 405 |
|
|
} else
|
| 406 |
|
|
if (strcmp(cur->insn, "h.ext16s") == 0) {
|
| 407 |
|
|
cur->func_unit = extend;
|
| 408 |
|
|
if ((eval_operand(cur->op1) & 0x8000) == 0x8000)
|
| 409 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) | 0xffff0000);
|
| 410 |
|
|
else
|
| 411 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) & 0x0000ffff);
|
| 412 |
|
|
} else
|
| 413 |
|
|
if (strcmp(cur->insn, "h.ext8s") == 0) {
|
| 414 |
|
|
cur->func_unit = extend;
|
| 415 |
|
|
if ((eval_operand(cur->op1) & 0x80) == 0x80)
|
| 416 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) | 0xffffff00);
|
| 417 |
|
|
else
|
| 418 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) & 0x000000ff);
|
| 419 |
|
|
} else
|
| 420 |
|
|
if (strcmp(cur->insn, "h.ext16z") == 0) {
|
| 421 |
|
|
cur->func_unit = extend;
|
| 422 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) & 0x0000ffff);
|
| 423 |
|
|
} else
|
| 424 |
|
|
if (strcmp(cur->insn, "h.ext8z") == 0) {
|
| 425 |
|
|
cur->func_unit = extend;
|
| 426 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) & 0x000000ff);
|
| 427 |
|
|
} else
|
| 428 |
|
|
if (strcmp(cur->insn, "h.add32s") == 0) {
|
| 429 |
|
|
signed long temp3, temp2, temp1;
|
| 430 |
|
|
signed char temp4;
|
| 431 |
|
|
|
| 432 |
|
|
cur->func_unit = arith;
|
| 433 |
|
|
temp3 = eval_operand(cur->op3);
|
| 434 |
|
|
temp2 = eval_operand(cur->op2);
|
| 435 |
|
|
temp1 = temp2 + temp3;
|
| 436 |
|
|
set_operand(cur->op1, temp1);
|
| 437 |
|
|
|
| 438 |
|
|
temp4 = temp1;
|
| 439 |
|
|
if (temp4 == temp1)
|
| 440 |
|
|
mstats.byteadd++;
|
| 441 |
|
|
} else
|
| 442 |
|
|
if (strcmp(cur->insn, "l.addi32s") == 0) {
|
| 443 |
|
|
signed long temp3, temp2, temp1;
|
| 444 |
|
|
signed char temp4;
|
| 445 |
|
|
|
| 446 |
|
|
cur->func_unit = arith;
|
| 447 |
|
|
temp3 = eval_operand(cur->op3);
|
| 448 |
|
|
temp2 = eval_operand(cur->op2);
|
| 449 |
|
|
temp1 = temp2 + temp3;
|
| 450 |
|
|
set_operand(cur->op1, temp1);
|
| 451 |
|
|
|
| 452 |
|
|
temp4 = temp1;
|
| 453 |
|
|
if (temp4 == temp1)
|
| 454 |
|
|
mstats.byteadd++;
|
| 455 |
|
|
} else
|
| 456 |
|
|
if (strcmp(cur->insn, "l.sub32s") == 0) {
|
| 457 |
|
|
signed long temp3, temp2, temp1;
|
| 458 |
|
|
|
| 459 |
|
|
cur->func_unit = arith;
|
| 460 |
|
|
temp3 = eval_operand(cur->op3);
|
| 461 |
|
|
temp2 = eval_operand(cur->op2);
|
| 462 |
|
|
temp1 = temp2 - temp3;
|
| 463 |
|
|
set_operand(cur->op1, temp1);
|
| 464 |
|
|
} else
|
| 465 |
|
|
if (strcmp(cur->insn, "l.subi32s") == 0) {
|
| 466 |
|
|
signed long temp3, temp2, temp1;
|
| 467 |
|
|
|
| 468 |
|
|
cur->func_unit = arith;
|
| 469 |
|
|
temp3 = eval_operand(cur->op3);
|
| 470 |
|
|
temp2 = eval_operand(cur->op2);
|
| 471 |
|
|
temp1 = temp2 - temp3;
|
| 472 |
|
|
set_operand(cur->op1, temp1);
|
| 473 |
|
|
} else
|
| 474 |
|
|
if (strcmp(cur->insn, "l.mul32s") == 0) {
|
| 475 |
|
|
signed long temp3, temp2, temp1;
|
| 476 |
|
|
|
| 477 |
|
|
cur->func_unit = arith;
|
| 478 |
|
|
temp3 = eval_operand(cur->op3);
|
| 479 |
|
|
temp2 = eval_operand(cur->op2);
|
| 480 |
|
|
temp1 = temp2 * temp3;
|
| 481 |
|
|
set_operand(cur->op1, temp1);
|
| 482 |
|
|
} else
|
| 483 |
|
|
if (strcmp(cur->insn, "l.div32s") == 0) {
|
| 484 |
|
|
signed long temp3, temp2, temp1;
|
| 485 |
|
|
|
| 486 |
|
|
cur->func_unit = arith;
|
| 487 |
|
|
temp3 = eval_operand(cur->op3);
|
| 488 |
|
|
temp2 = eval_operand(cur->op2);
|
| 489 |
|
|
temp1 = temp2 / temp3;
|
| 490 |
|
|
set_operand(cur->op1, temp1);
|
| 491 |
|
|
} else
|
| 492 |
|
|
if (strcmp(cur->insn, "l.div32u") == 0) {
|
| 493 |
|
|
unsigned long temp3, temp2, temp1;
|
| 494 |
|
|
|
| 495 |
|
|
cur->func_unit = arith;
|
| 496 |
|
|
temp3 = eval_operand(cur->op3);
|
| 497 |
|
|
temp2 = eval_operand(cur->op2);
|
| 498 |
|
|
temp1 = temp2 / temp3;
|
| 499 |
|
|
set_operand(cur->op1, temp1);
|
| 500 |
|
|
} else
|
| 501 |
|
|
if (strcmp(cur->insn, "l.shla32") == 0) {
|
| 502 |
|
|
int sign = 1;
|
| 503 |
|
|
cur->func_unit = shift;
|
| 504 |
|
|
debug("shla: op3:%d op4:%d", eval_operand(cur->op3), eval_operand(cur->op4));
|
| 505 |
|
|
debug("shla: op4=%s", cur->op4);
|
| 506 |
|
|
if ((signed)eval_operand(cur->op2) < 0)
|
| 507 |
|
|
sign = -1;
|
| 508 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) << (eval_operand(cur->op3) | eval_operand(cur->op4)));
|
| 509 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) * sign);
|
| 510 |
|
|
} else
|
| 511 |
|
|
if (strcmp(cur->insn, "l.shra32") == 0) {
|
| 512 |
|
|
int sign = 1;
|
| 513 |
|
|
cur->func_unit = shift;
|
| 514 |
|
|
|
| 515 |
|
|
if ((signed)eval_operand(cur->op2) < 0)
|
| 516 |
|
|
sign = -1;
|
| 517 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) >> (eval_operand(cur->op3) | eval_operand(cur->op4)));
|
| 518 |
|
|
set_operand(cur->op1, eval_operand(cur->op1) * sign);
|
| 519 |
|
|
} else
|
| 520 |
|
|
if (strcmp(cur->insn, "l.shrl32") == 0) {
|
| 521 |
|
|
cur->func_unit = shift;
|
| 522 |
|
|
set_operand(cur->op1, eval_operand(cur->op2) >> eval_operand(cur->op3));
|
| 523 |
|
|
} else
|
| 524 |
|
|
if (strcmp(cur->insn, "l.jmp") == 0) {
|
| 525 |
|
|
cur->func_unit = jump;
|
| 526 |
|
|
pctemp = eval_operand(cur->op1);
|
| 527 |
|
|
} else
|
| 528 |
|
|
if (strcmp(cur->insn, "l.jal") == 0) {
|
| 529 |
|
|
cur->func_unit = jump;
|
| 530 |
|
|
pctemp = eval_operand(cur->op1);
|
| 531 |
|
|
set_reg32(LINK_REG, pc + 4);
|
| 532 |
|
|
} else
|
| 533 |
|
|
if (strcmp(cur->insn, "h.jalr") == 0) {
|
| 534 |
|
|
cur->func_unit = jump;
|
| 535 |
|
|
pctemp = eval_operand(cur->op1);
|
| 536 |
|
|
set_reg32(LINK_REG, pc + 4);
|
| 537 |
|
|
} else
|
| 538 |
|
|
if (strcmp(cur->insn, "jr") == 0) {
|
| 539 |
|
|
cur->func_unit = jump;
|
| 540 |
|
|
cur->dependsrc1 = cur->op1;
|
| 541 |
|
|
pctemp = eval_operand(cur->op1);
|
| 542 |
|
|
} else
|
| 543 |
|
|
if (strcmp(cur->insn, "h.nop") == 0) {
|
| 544 |
|
|
cur->func_unit = nop;
|
| 545 |
|
|
} else
|
| 546 |
|
|
if (strcmp(cur->insn, "l.bfeqz") == 0) {
|
| 547 |
|
|
cur->func_unit = branch;
|
| 548 |
|
|
cur->dependsrc1 = ccr_flag;
|
| 549 |
|
|
if (flag == 0) {
|
| 550 |
|
|
pctemp = eval_operand(cur->op1);
|
| 551 |
|
|
mstats.beqz.taken++;
|
| 552 |
|
|
bpb_update(cur->insn_addr, 1);
|
| 553 |
|
|
btic_update(pctemp);
|
| 554 |
|
|
} else {
|
| 555 |
|
|
mstats.beqz.nottaken++;
|
| 556 |
|
|
bpb_update(cur->insn_addr, 0);
|
| 557 |
|
|
btic_update(pc);
|
| 558 |
|
|
}
|
| 559 |
|
|
} else
|
| 560 |
|
|
if (strcmp(cur->insn, "l.bfnez") == 0) {
|
| 561 |
|
|
cur->func_unit = branch;
|
| 562 |
|
|
cur->dependsrc1 = ccr_flag;
|
| 563 |
|
|
if (flag) {
|
| 564 |
|
|
pctemp = eval_operand(cur->op1);
|
| 565 |
|
|
mstats.bnez.taken++;
|
| 566 |
|
|
bpb_update(cur->insn_addr, 1);
|
| 567 |
|
|
btic_update(pctemp);
|
| 568 |
|
|
} else {
|
| 569 |
|
|
mstats.bnez.nottaken++;
|
| 570 |
|
|
bpb_update(cur->insn_addr, 0);
|
| 571 |
|
|
btic_update(pc);
|
| 572 |
|
|
}
|
| 573 |
|
|
} else
|
| 574 |
|
|
if (strcmp(cur->insn, "h.sfeq32") == 0) {
|
| 575 |
|
|
cur->func_unit = compare;
|
| 576 |
|
|
cur->dependsrc2 = cur->op1;
|
| 577 |
|
|
cur->dependdst = ccr_flag;
|
| 578 |
|
|
flag = eval_operand(cur->op1) == eval_operand(cur->op2);
|
| 579 |
|
|
} else
|
| 580 |
|
|
if (strcmp(cur->insn, "h.sfne32") == 0) {
|
| 581 |
|
|
cur->func_unit = compare;
|
| 582 |
|
|
cur->dependsrc2 = cur->op1;
|
| 583 |
|
|
cur->dependdst = ccr_flag;
|
| 584 |
|
|
flag = eval_operand(cur->op1) != eval_operand(cur->op2);
|
| 585 |
|
|
} else
|
| 586 |
|
|
if (strcmp(cur->insn, "h.sfgt32s") == 0) {
|
| 587 |
|
|
cur->func_unit = compare;
|
| 588 |
|
|
cur->dependsrc2 = cur->op1;
|
| 589 |
|
|
cur->dependdst = ccr_flag;
|
| 590 |
|
|
flag = (signed)eval_operand(cur->op1) >
|
| 591 |
|
|
(signed)eval_operand(cur->op2);
|
| 592 |
|
|
} else
|
| 593 |
|
|
if (strcmp(cur->insn, "h.sfge32s") == 0) {
|
| 594 |
|
|
cur->func_unit = compare;
|
| 595 |
|
|
cur->dependsrc2 = cur->op1;
|
| 596 |
|
|
cur->dependdst = ccr_flag;
|
| 597 |
|
|
flag = (signed)eval_operand(cur->op1) >=
|
| 598 |
|
|
(signed)eval_operand(cur->op2);
|
| 599 |
|
|
} else
|
| 600 |
|
|
if (strcmp(cur->insn, "h.sflt32s") == 0) {
|
| 601 |
|
|
cur->func_unit = compare;
|
| 602 |
|
|
cur->dependsrc2 = cur->op1;
|
| 603 |
|
|
cur->dependdst = ccr_flag;
|
| 604 |
|
|
flag = (signed)eval_operand(cur->op1) <
|
| 605 |
|
|
(signed)eval_operand(cur->op2);
|
| 606 |
|
|
} else
|
| 607 |
|
|
if (strcmp(cur->insn, "h.sfle32s") == 0) {
|
| 608 |
|
|
cur->func_unit = compare;
|
| 609 |
|
|
cur->dependsrc2 = cur->op1;
|
| 610 |
|
|
cur->dependdst = ccr_flag;
|
| 611 |
|
|
flag = (signed)eval_operand(cur->op1) <=
|
| 612 |
|
|
(signed)eval_operand(cur->op2);
|
| 613 |
|
|
} else
|
| 614 |
|
|
if (strcmp(cur->insn, "h.sfgt32u") == 0) {
|
| 615 |
|
|
cur->func_unit = compare;
|
| 616 |
|
|
cur->dependsrc2 = cur->op1;
|
| 617 |
|
|
cur->dependdst = ccr_flag;
|
| 618 |
|
|
flag = (unsigned)eval_operand(cur->op1) >
|
| 619 |
|
|
(unsigned)eval_operand(cur->op2);
|
| 620 |
|
|
} else
|
| 621 |
|
|
if (strcmp(cur->insn, "h.sfge32u") == 0) {
|
| 622 |
|
|
cur->func_unit = compare;
|
| 623 |
|
|
cur->dependsrc2 = cur->op1;
|
| 624 |
|
|
cur->dependdst = ccr_flag;
|
| 625 |
|
|
flag = (unsigned)eval_operand(cur->op1) >=
|
| 626 |
|
|
(unsigned) eval_operand(cur->op2);
|
| 627 |
|
|
} else
|
| 628 |
|
|
if (strcmp(cur->insn, "h.sflt32u") == 0) {
|
| 629 |
|
|
cur->func_unit = compare;
|
| 630 |
|
|
cur->dependsrc2 = cur->op1;
|
| 631 |
|
|
cur->dependdst = ccr_flag;
|
| 632 |
|
|
flag = (unsigned)eval_operand(cur->op1) <
|
| 633 |
|
|
(unsigned)eval_operand(cur->op2);
|
| 634 |
|
|
} else
|
| 635 |
|
|
if (strcmp(cur->insn, "h.sfle32u") == 0) {
|
| 636 |
|
|
cur->func_unit = compare;
|
| 637 |
|
|
cur->dependsrc2 = cur->op1;
|
| 638 |
|
|
cur->dependdst = ccr_flag;
|
| 639 |
|
|
flag = (unsigned)eval_operand(cur->op1) <=
|
| 640 |
|
|
(unsigned)eval_operand(cur->op2);
|
| 641 |
|
|
} else
|
| 642 |
|
|
if (strcmp(cur->insn, "simrdtsc") == 0) {
|
| 643 |
|
|
set_operand(cur->op1, supercycles);
|
| 644 |
|
|
} else
|
| 645 |
|
|
if (strcmp(cur->insn, "simprintf") == 0) {
|
| 646 |
|
|
unsigned long stackaddr, fmtaddr, args;
|
| 647 |
|
|
|
| 648 |
|
|
stackaddr = eval_reg(FRAME_REG);
|
| 649 |
|
|
simprintf(stackaddr, eval_reg("r3"));
|
| 650 |
|
|
debug("simprintf %x %x %x\n", stackaddr, fmtaddr, args);
|
| 651 |
|
|
} else {
|
| 652 |
|
|
printf("\nEXCEPTION: illegal opcode %s ", cur->insn);
|
| 653 |
|
|
printf("at %.8lx\n", cur->insn_addr);
|
| 654 |
|
|
cont_run = 0;
|
| 655 |
|
|
}
|
| 656 |
|
|
|
| 657 |
|
|
/* Dynamic, dependency stats. */
|
| 658 |
|
|
adddstats(icomplet[0].insn, iqueue[0].insn, 1, check_depend());
|
| 659 |
|
|
|
| 660 |
|
|
/* Dynamic, functional units stats. */
|
| 661 |
|
|
addfstats(icomplet[0].func_unit, iqueue[0].func_unit, 1, check_depend());
|
| 662 |
|
|
|
| 663 |
|
|
/* Dynamic, single stats. */
|
| 664 |
|
|
addsstats(iqueue[0].insn, 1, 0);
|
| 665 |
|
|
|
| 666 |
|
|
/* Pseudo multiple issue benchmark */
|
| 667 |
|
|
if ((multissue[cur->func_unit] == 0) || (check_depend())) {
|
| 668 |
|
|
int i;
|
| 669 |
|
|
for (i = 0; i < 20; i++)
|
| 670 |
|
|
multissue[i] = 1;
|
| 671 |
|
|
supercycles++;
|
| 672 |
|
|
/* if (check_depend())
|
| 673 |
|
|
supercycles++; */
|
| 674 |
|
|
multissue[move] = 2;
|
| 675 |
|
|
multissue[movimm] = 2;
|
| 676 |
|
|
multissue[arith] = 3;
|
| 677 |
|
|
multissue[store] = 4;
|
| 678 |
|
|
multissue[load] = 2;
|
| 679 |
|
|
}
|
| 680 |
|
|
multissue[cur->func_unit]--;
|
| 681 |
|
|
|
| 682 |
|
|
return;
|
| 683 |
|
|
}
|
| 684 |
|
|
|
| 685 |
|
|
void execute()
|
| 686 |
|
|
{
|
| 687 |
|
|
int i;
|
| 688 |
|
|
|
| 689 |
|
|
/* Here comes real execution someday... */
|
| 690 |
|
|
|
| 691 |
|
|
/* Instruction waits in completition buffer until retired. */
|
| 692 |
|
|
strcpy(icomplet[0].insn, iqueue[0].insn);
|
| 693 |
|
|
strcpy(icomplet[0].op1, iqueue[0].op1);
|
| 694 |
|
|
strcpy(icomplet[0].op2, iqueue[0].op2);
|
| 695 |
|
|
strcpy(icomplet[0].op3, iqueue[0].op3);
|
| 696 |
|
|
strcpy(icomplet[0].op4, iqueue[0].op4);
|
| 697 |
|
|
icomplet[0].func_unit = iqueue[0].func_unit;
|
| 698 |
|
|
icomplet[0].insn_addr = iqueue[0].insn_addr;
|
| 699 |
|
|
|
| 700 |
|
|
if (iqueue[0].dependdst == iqueue[0].op1)
|
| 701 |
|
|
icomplet[0].dependdst = icomplet[0].op1;
|
| 702 |
|
|
else
|
| 703 |
|
|
if (iqueue[0].dependdst == iqueue[0].op2)
|
| 704 |
|
|
icomplet[0].dependdst = icomplet[0].op2;
|
| 705 |
|
|
else
|
| 706 |
|
|
if (iqueue[0].dependdst == iqueue[0].op3)
|
| 707 |
|
|
icomplet[0].dependdst = icomplet[0].op3;
|
| 708 |
|
|
else
|
| 709 |
|
|
icomplet[0].dependdst = NULL;
|
| 710 |
|
|
|
| 711 |
|
|
if (iqueue[0].dependsrc1 == iqueue[0].op1)
|
| 712 |
|
|
icomplet[0].dependsrc1 = icomplet[0].op1;
|
| 713 |
|
|
else
|
| 714 |
|
|
if (iqueue[0].dependsrc1 == iqueue[0].op2)
|
| 715 |
|
|
icomplet[0].dependsrc1 = icomplet[0].op2;
|
| 716 |
|
|
else
|
| 717 |
|
|
if (iqueue[0].dependsrc1 == iqueue[0].op3)
|
| 718 |
|
|
icomplet[0].dependsrc1 = icomplet[0].op3;
|
| 719 |
|
|
else
|
| 720 |
|
|
icomplet[0].dependsrc1 = NULL;
|
| 721 |
|
|
|
| 722 |
|
|
if (iqueue[0].dependsrc2 == iqueue[0].op1)
|
| 723 |
|
|
icomplet[0].dependsrc2 = icomplet[0].op1;
|
| 724 |
|
|
else
|
| 725 |
|
|
if (iqueue[0].dependsrc2 == iqueue[0].op2)
|
| 726 |
|
|
icomplet[0].dependsrc2 = icomplet[0].op2;
|
| 727 |
|
|
else
|
| 728 |
|
|
if (iqueue[0].dependsrc2 == iqueue[0].op3)
|
| 729 |
|
|
icomplet[0].dependsrc2 = icomplet[0].op3;
|
| 730 |
|
|
else
|
| 731 |
|
|
icomplet[0].dependsrc2 = NULL;
|
| 732 |
|
|
|
| 733 |
|
|
/* History of execution */
|
| 734 |
|
|
for (i = HISTEXEC_LEN - 1; i; i--)
|
| 735 |
|
|
histexec[i] = histexec[i - 1];
|
| 736 |
|
|
histexec[0] = icomplet[0].insn_addr; /* add last insn */
|
| 737 |
|
|
|
| 738 |
|
|
return;
|
| 739 |
|
|
}
|
| 740 |
|
|
|
| 741 |
|
|
void dumpreg()
|
| 742 |
|
|
{
|
| 743 |
|
|
int i;
|
| 744 |
|
|
|
| 745 |
|
|
printf("\n\nIQ[0]:");
|
| 746 |
|
|
dumpmemory(iqueue[0].insn_addr, iqueue[0].insn_addr + 4);
|
| 747 |
|
|
printf(" (just executed)\tCYCLE: %u \tSUPERCYCLE: %u\nPC:", cycles, supercycles);
|
| 748 |
|
|
dumpmemory(pc, pc + 4);
|
| 749 |
|
|
printf(" (next insn)");
|
| 750 |
|
|
for(i = 0; i < MAX_GPRS; i++) {
|
| 751 |
|
|
if (i % 4 == 0)
|
| 752 |
|
|
printf("\n");
|
| 753 |
|
|
printf("GPR%.2u: %.8lx ", i, reg[i]);
|
| 754 |
|
|
}
|
| 755 |
|
|
printf("flag: %u\n", flag);
|
| 756 |
|
|
}
|
