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[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1721

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/* op.c -- Micro operations for the recompiler
   Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
 
#include "config.h"
 
#ifdef HAVE_INTTYPES_H
#include <inttypes.h>
#endif
 
#include "port.h"
#include "arch.h"
#include "spr_defs.h"
#include "opcode/or32.h"
#include "sim-config.h"
#include "except.h"
#include "abstract.h"
#include "execute.h"
#include "sprs.h"
#include "sched.h"
#include "immu.h"
 
#include "op_support.h"
 
#include "i386_regs.h"
 
#include "dyn_rec.h"
 
register struct cpu_state *env asm(CPU_STATE_REG);
 
#include "op_i386.h"
 
/*
 * WARNING: Before going of and wildly editing everything in this file remember
 * the following about its contents:
 * 1) The `functions' don't EVER return.  In otherwords haveing return state-
 *    ments _anywere_ in this file is likely not to work.  This is because
 *    dyngen just strips away the ret from the end of the function and just uses
 *    the function `body'.  If a ret statement is executed _anyware_ inside the
 *    dynamicly generated code, then it is undefined were we shall jump to.
 * 2) Because of 1), try not to have overly complicated functions.  In too
 *    complicated functions, gcc may decide to generate premature `exits'.  This
 *    is what passing the -fno-reorder-blocks command line switch to gcc helps
 *    with.  This is ofcourse not desired and is rather flaky as we don't (and
 *    can't) control the kind of code that gcc generates: It may work for one
 *    and break for another.  The less branches there are the less likely it is
 *    that a premature return shall occur.
 * 3) If gcc decides that it is going to be a basterd then it will optimise a
 *    very simple condition (if/switch) with a premature exit.  But gcc can't
 *    fuck ME over!  Just stick a FORCE_RET; at the END of the offending
 *    function.
 * 4) All operations must start with `op_'.  dyngen ignores all other functions.
 * 5) Local variables are depriciated: They hinder performance.
 * 6) Function calls are expensive as the stack has to be shifted (twice).
 */
 
/*#define __or_dynop __attribute__((noreturn))*/
#define __or_dynop
 
/* Temporaries to hold the (simulated) registers in */
register uint32_t t0 asm(T0_REG);
register uint32_t t1 asm(T1_REG);
register uint32_t t2 asm(T2_REG);
 
#define OP_PARAM1 ((uorreg_t)(&__op_param1))
#define OP_PARAM2 ((uorreg_t)(&__op_param2))
#define OP_PARAM3 ((uorreg_t)(&__op_param3))
 
extern uorreg_t __op_param1;
extern uorreg_t __op_param2;
extern uorreg_t __op_param3;
 
 
static inline void save_t_bound(oraddr_t pc)
{
  int reg;
 
  pc = (pc & immu_state->page_offset_mask) / 4;
  reg = env->curr_page->ts_bound[pc];
 
  if(reg & 0x1f)
    env->reg[reg & 0x1f] = t0;
 
  if((reg >> 5) & 0x1f)
    env->reg[(reg >> 5) & 0x1f] = t1;
 
  if((reg >> 10) & 0x1f)
    env->reg[(reg >> 10) & 0x1f] = t2;
}
 
void do_sched_wrap(void)
{
  env->pc += 4;
  //runtime.cpu.instructions++;
  runtime.sim.cycles -= env->cycles_dec;
  scheduler.job_queue->time += env->cycles_dec;
  if(scheduler.job_queue->time <= 0) {
    save_t_bound(env->pc - 4);
    do_scheduler();
  }
}
 
/* do_scheduler wrapper for instructions that are in the delay slot */
void do_sched_wrap_delay(void)
{
  /* FIXME: Can't this be eliminated? */
  env->pc += 4;
  //runtime.cpu.instructions++;
  runtime.sim.cycles -= env->cycles_dec;
  scheduler.job_queue->time += env->cycles_dec;
  if(scheduler.job_queue->time <= 0)
    do_scheduler();
}
 
void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)
{
  uint16_t reg = 0;
  uint32_t t0_reg = t0, t1_reg = t1, t2_reg = t2;
  struct cpu_state *cpu_reg = env;
 
  addr &= immu_state->page_offset_mask;
  addr >>= 2;
 
  if(addr)
    reg = dp->ts_bound[addr - 1];
 
  t0 = cpu_state.reg[reg & 0x1f];
  t1 = cpu_state.reg[(reg >> 5) & 0x1f];
 
  /* Don't we all love gcc?  For some heavenly reason gcc 3.2 _knows_ that if I
   * don't put a condition around the assignment of t2, _all_ the assignments to
   * t{0,1,2} are useless and not needed.  I'm pleasently happy that gcc is so
   * bright, but on the other hand, t{0,1,2} are globals (!) how can you assume
   * that the value of a global won't be used in a function further up or
   * further down the stack?? */
  if(addr)
    t2 = cpu_state.reg[(reg >> 10) & 0x1f];
 
  env = &cpu_state;
 
  ((gen_code_ent *)dp->locs)[addr]();
  t0 = t0_reg;
  t1 = t1_reg;
  t2 = t2_reg;
  env = (struct cpu_state *)cpu_reg;
}
 
__or_dynop void op_set_pc_pc_delay(void)
{
  env->sprs[SPR_PPC] = env->pc;
  /* pc_delay is pulled back 4 since imediatly after this is run, the scheduler
   * runs which also increments it by 4 */
  env->pc = env->pc_delay - 4;
}
 
__or_dynop void op_set_pc_delay_imm(void)
{
  env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
  env->delay_insn = 1;
}
 
__or_dynop void op_set_pc_delay_pc(void)
{
  env->pc_delay = env->pc;
  env->delay_insn = 1;
}
 
__or_dynop void op_clear_pc_delay(void)
{
  env->pc_delay = 0;
  env->delay_insn = 1;
}
 
__or_dynop void op_do_jump(void)
{
  RET_FROM_DYN_CODE;
}
 
__or_dynop void op_do_jump_delay(void)
{
  env->pc = env->pc_delay;
  RET_FROM_DYN_CODE;
}
 
__or_dynop void op_clear_delay_insn(void)
{
  env->delay_insn = 0;
}
 
__or_dynop void op_set_delay_insn(void)
{
  env->delay_insn = 1;
}
 
__or_dynop void op_check_delay_slot(void)
{
  if(!env->delay_insn)
    OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_jmp_imm(void)
{
  OP_JUMP(OP_PARAM1);
}
 
__or_dynop void op_set_flag(void)
{
  env->sprs[SPR_SR] |= SPR_SR_F;
}
 
__or_dynop void op_clear_flag(void)
{
  env->sprs[SPR_SR] &= ~SPR_SR_F;
}
 
/* Used for the l.bf instruction.  Therefore if the flag is not set, jump over
 * all the jumping stuff */
__or_dynop void op_check_flag(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    SPEEDY_CALL(do_sched_wrap);
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bf if the delay slot instruction is on another page */
__or_dynop void op_check_flag_delay(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    env->delay_insn = 1;
    env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
  }
}
 
/* Used for the l.bnf instruction.  Therefore if the flag is set, jump over all
 * the jumping stuff */
__or_dynop void op_check_not_flag(void)
{
  if(env->sprs[SPR_SR] & SPR_SR_F) {
    SPEEDY_CALL(do_sched_wrap);
    OP_JUMP(OP_PARAM1);
  }
}
 
/* Used for l.bnf if the delay slot instruction is on another page */
__or_dynop void op_check_not_flag_delay(void)
{
  if(!(env->sprs[SPR_SR] & SPR_SR_F)) {
    env->delay_insn = 1;
    env->pc_delay = env->pc + (orreg_t)OP_PARAM1;
  }
}
 
__or_dynop void op_add_pc(void)
{
  env->pc += OP_PARAM1;
}
 
__or_dynop void op_nop_exit(void)
{
  op_support_nop_exit();
  FORCE_RET;
}
 
__or_dynop void op_nop_reset(void)
{
  op_support_nop_reset();
  env->pc = EXCEPT_RESET;
  RET_FROM_DYN_CODE;
}
 
__or_dynop void op_nop_printf(void)
{
  op_support_nop_printf();
  FORCE_RET;
}
 
__or_dynop void op_nop_report(void)
{
  op_support_nop_report();
  FORCE_RET;
}
 
__or_dynop void op_nop_report_imm(void)
{
  op_support_nop_report_imm(OP_PARAM1);
}
 
/* FIXME: Create another 2 sched functions that to the actual analysis call
 * instead of bloating the recompiled code with this */
__or_dynop void op_analysis(void)
{
  SPEEDY_CALL(op_support_analysis);
}
 
__or_dynop void op_move_gpr1_pc_delay(void)
{
  env->pc_delay = env->reg[1];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr2_pc_delay(void)
{
  env->pc_delay = env->reg[2];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr3_pc_delay(void)
{
  env->pc_delay = env->reg[3];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr4_pc_delay(void)
{
  env->pc_delay = env->reg[4];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr5_pc_delay(void)
{
  env->pc_delay = env->reg[5];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr6_pc_delay(void)
{
  env->pc_delay = env->reg[6];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr7_pc_delay(void)
{
  env->pc_delay = env->reg[7];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr8_pc_delay(void)
{
  env->pc_delay = env->reg[8];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr9_pc_delay(void)
{
  env->pc_delay = env->reg[9];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr10_pc_delay(void)
{
  env->pc_delay = env->reg[10];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr11_pc_delay(void)
{
  env->pc_delay = env->reg[11];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr12_pc_delay(void)
{
  env->pc_delay = env->reg[12];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr13_pc_delay(void)
{
  env->pc_delay = env->reg[13];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr14_pc_delay(void)
{
  env->pc_delay = env->reg[14];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr15_pc_delay(void)
{
  env->pc_delay = env->reg[15];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr16_pc_delay(void)
{
  env->pc_delay = env->reg[16];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr17_pc_delay(void)
{
  env->pc_delay = env->reg[17];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr18_pc_delay(void)
{
  env->pc_delay = env->reg[18];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr19_pc_delay(void)
{
  env->pc_delay = env->reg[19];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr20_pc_delay(void)
{
  env->pc_delay = env->reg[20];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr21_pc_delay(void)
{
  env->pc_delay = env->reg[21];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr22_pc_delay(void)
{
  env->pc_delay = env->reg[22];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr23_pc_delay(void)
{
  env->pc_delay = env->reg[23];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr24_pc_delay(void)
{
  env->pc_delay = env->reg[24];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr25_pc_delay(void)
{
  env->pc_delay = env->reg[25];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr26_pc_delay(void)
{
  env->pc_delay = env->reg[26];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr27_pc_delay(void)
{
  env->pc_delay = env->reg[27];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr28_pc_delay(void)
{
  env->pc_delay = env->reg[28];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr29_pc_delay(void)
{
  env->pc_delay = env->reg[29];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr30_pc_delay(void)
{
  env->pc_delay = env->reg[30];
  env->delay_insn = 1;
}
 
__or_dynop void op_move_gpr31_pc_delay(void)
{
  env->pc_delay = env->reg[31];
  env->delay_insn = 1;
}
 
#define OP_FILE "op_1t_op.h"
#include "op_1t.h"
#undef OP_FILE
 
#define OP_FILE "op_2t_op.h"
#include "op_2t.h"
#undef OP_FILE
 
#define OP_FILE "op_3t_op.h"
#include "op_3t.h"
#undef OP_FILE
 
#define OP_FILE "op_arith_op.h"
#define OP_EXTRA
 
#define OP /
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME div
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP /
#define OP_CAST(x) (x)
#define OP_NAME divu
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(x) (x)
#define OP_NAME mulu
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP -
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sub
#include "op_3t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
 
#define OP_EXTRA + ((env->sprs[SPR_SR] & SPR_SR_CY) >> 10)
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME addc
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#define OP_EXTRA
 
#define OP +
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME add
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP &
#define OP_CAST(x) (x)
#define OP_NAME and
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP *
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME mul
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP |
#define OP_CAST(x) (x)
#define OP_NAME or
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP <<
#define OP_CAST(x) (x)
#define OP_NAME sll
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(x) (orreg_t)(x)
#define OP_NAME sra
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP >>
#define OP_CAST(x) (x)
#define OP_NAME srl
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#define OP ^
#define OP_CAST(x) (x)
#define OP_NAME xor
#include "op_3t.h"
#include "op_2t.h"
#undef OP_NAME
#undef OP_CAST
#undef OP
 
#undef OP_EXTRA
#undef OP_FILE
 
#define OP_FILE "op_extend_op.h"
 
#define EXT_NAME extbs
#define EXT_TYPE int8_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME extbz
#define EXT_TYPE uint8_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exths
#define EXT_TYPE int16_t
#define EXT_CAST (orreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#define EXT_NAME exthz
#define EXT_TYPE uint16_t
#define EXT_CAST (uorreg_t)
#include "op_2t.h"
#undef EXT_CAST
#undef EXT_TYPE
#undef EXT_NAME
 
#undef OP_FILE
 
#define OP_FILE "op_comp_op.h"
 
#define COMP ==
#define COMP_NAME sfeq
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP !=
#define COMP_NAME sfne
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgtu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfgeu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sfltu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfleu
#define COMP_CAST(x) (x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >
#define COMP_NAME sfgts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP >=
#define COMP_NAME sfges
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <
#define COMP_NAME sflts
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#define COMP <=
#define COMP_NAME sfles
#define COMP_CAST(x) (orreg_t)(x)
#include "op_2t.h"
#include "op_1t.h"
#undef COMP_CAST
#undef COMP_NAME
#undef COMP
 
#undef OP_FILE
 
#define OP_FILE "op_t_reg_mov_op.h"
#include "op_1t.h"
#undef OP_FILE
 
#define OP_FILE "op_mftspr_op.h"
#include "op_1t.h"
#include "op_2t.h"
#undef OP_FILE
#include "op_mftspr_op.h"
 
#define OP_FILE "op_mac_op.h"
 
#define OP +=
#define OP_NAME mac
#include "op_2t.h"
#undef OP_NAME
#undef OP
 
#define OP -=
#define OP_NAME msb
#include "op_2t.h"
#undef OP_NAME
#undef OP
 
#undef OP_FILE
 
#define OP_FILE "op_lwhb_op.h"
 
#define LS_OP_NAME lbz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem8
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lbs
#define LS_OP_CAST (int8_t)
#define LS_OP_FUNC eval_mem8
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem16
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lhs
#define LS_OP_CAST (int16_t)
#define LS_OP_FUNC eval_mem16
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lwz
#define LS_OP_CAST
#define LS_OP_FUNC eval_mem32
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#define LS_OP_NAME lws
#define LS_OP_CAST (int32_t)
#define LS_OP_FUNC eval_mem32
#include "op_2t.h"
#include "op_1t.h"
#undef LS_OP_FUNC
#undef LS_OP_CAST
#undef LS_OP_NAME
 
#undef OP_FILE
 
#define OP_FILE "op_swhb_op.h"
 
#define S_OP_NAME sb
#define S_FUNC set_mem8
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sh
#define S_FUNC set_mem16
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
#define S_OP_NAME sw
#define S_FUNC set_mem32
#include "op_swhb_op.h"
#include "op_2t.h"
#include "op_1t.h"
#undef S_FUNC
#undef S_OP_NAME
 
__or_dynop void op_join_mem_cycles(void)
{
  runtime.sim.cycles += runtime.sim.mem_cycles;
  scheduler.job_queue->time -= runtime.sim.mem_cycles;
  runtime.sim.mem_cycles = 0;
}
 
__or_dynop void op_store_link_addr_gpr(void)
{
  env->reg[LINK_REGNO] = env->pc + 8;
}
 
__or_dynop void op_prep_rfe(void)
{
  env->sprs[SPR_SR] = env->sprs[SPR_ESR_BASE] | SPR_SR_FO;
  env->sprs[SPR_PPC] = env->pc;
  env->pc = env->sprs[SPR_EPCR_BASE] - 4;
}
 
static inline void prep_except(oraddr_t epcr_base)
{
  env->sprs[SPR_EPCR_BASE] = epcr_base;
 
  env->sprs[SPR_ESR_BASE] = env->sprs[SPR_SR];
 
  /* Address translation is always disabled when starting exception. */
  env->sprs[SPR_SR] &= ~SPR_SR_DME;
  env->sprs[SPR_SR] &= ~SPR_SR_IME;
 
  env->sprs[SPR_SR] &= ~SPR_SR_OVE;   /* Disable overflow flag exception. */
 
  env->sprs[SPR_SR] |= SPR_SR_SM;     /* SUPV mode */
  env->sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE);    /* Disable interrupts. */
}
 
/* Before the code in op_{sys,trap}{,_delay} gets run, the scheduler runs.
 * Therefore the pc will point to the instruction after the l.sys or l.trap
 * instruction */
__or_dynop void op_prep_sys_delay(void)
{
  env->delay_insn = 0;
  prep_except(env->pc - 4);
  env->pc = EXCEPT_SYSCALL - 4;
}
 
__or_dynop void op_prep_sys(void)
{
  prep_except(env->pc + 4);
  env->pc = EXCEPT_SYSCALL - 4;
}
 
__or_dynop void op_prep_trap_delay(void)
{
  env->delay_insn = 0;
  prep_except(env->pc - 4);
  env->pc = EXCEPT_TRAP - 4;
}
 
__or_dynop void op_prep_trap(void)
{
  prep_except(env->pc);
  env->pc = EXCEPT_TRAP - 4;
}
 
/* FIXME: This `instruction' should be split up like the l.trap and l.sys
 * instructions are done */
__or_dynop void op_illegal_delay(void)
{
  env->delay_insn = 0;
  env->sprs[SPR_EEAR_BASE] = env->pc - 4;
  env->pc = EXCEPT_ILLEGAL - 4;
  RET_FROM_DYN_CODE;
}
 
__or_dynop void op_illegal(void)
{
  env->sprs[SPR_EEAR_BASE] = env->pc;
  env->pc = EXCEPT_ILLEGAL;
  RET_FROM_DYN_CODE;
}
 
__or_dynop void op_do_sched(void)
{
  SPEEDY_CALL(do_sched_wrap);
}
 
__or_dynop void op_do_sched_delay(void)
{
  SPEEDY_CALL(do_sched_wrap_delay);
}
 
__or_dynop void op_macc(void)
{
  env->sprs[SPR_MACLO] = 0;
  env->sprs[SPR_MACHI] = 0;
}
 
__or_dynop void op_store_insn_ea(void)
{
  env->insn_ea = OP_PARAM1;
}
 

Line No.	Rev	Author	Line
1	1452	nogj	`/* op.c -- Micro operations for the recompiler`
2			Copyright (C) 2005 Gy�rgy `nog' Jeney, nog@sdf.lonestar.org
3
4			`This file is part of OpenRISC 1000 Architectural Simulator.`
5
6			`This program is free software; you can redistribute it and/or modify`
7			`it under the terms of the GNU General Public License as published by`
8			`the Free Software Foundation; either version 2 of the License, or`
9			`(at your option) any later version.`
10
11			`This program is distributed in the hope that it will be useful,`
12			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
13			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
14			`GNU General Public License for more details.`
15
16			`You should have received a copy of the GNU General Public License`
17			`along with this program; if not, write to the Free Software`
18			`Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */`
19
20
21			`#include <stdio.h>`
22			`#include <stdint.h>`
23			`#include <stdlib.h>`
24
25			`#include "config.h"`
26
27			`#ifdef HAVE_INTTYPES_H`
28			`#include <inttypes.h>`
29			`#endif`
30
31			`#include "port.h"`
32			`#include "arch.h"`
33			`#include "spr_defs.h"`
34			`#include "opcode/or32.h"`
35			`#include "sim-config.h"`
36			`#include "except.h"`
37			`#include "abstract.h"`
38			`#include "execute.h"`
39			`#include "sprs.h"`
40			`#include "sched.h"`
41	1717	nogj	`#include "immu.h"`
42	1452	nogj
43			`#include "op_support.h"`
44
45			`#include "i386_regs.h"`
46
47			`#include "dyn_rec.h"`
48
49			`register struct cpu_state *env asm(CPU_STATE_REG);`
50
51			`#include "op_i386.h"`
52
53			`/*`
54	1549	nogj	`* WARNING: Before going of and wildly editing everything in this file remember`
55	1452	nogj	`* the following about its contents:`
56			* 1) The `functions' don't EVER return. In otherwords haveing return state-
57			`* ments _anywere_ in this file is likely not to work. This is because`
58			`* dyngen just strips away the ret from the end of the function and just uses`
59			* the function `body'. If a ret statement is executed _anyware_ inside the
60			`* dynamicly generated code, then it is undefined were we shall jump to.`
61			`* 2) Because of 1), try not to have overly complicated functions. In too`
62			* complicated functions, gcc may decide to generate premature `exits'. This
63			`* is what passing the -fno-reorder-blocks command line switch to gcc helps`
64			`* with. This is ofcourse not desired and is rather flaky as we don't (and`
65			`* can't) control the kind of code that gcc generates: It may work for one`
66			`* and break for another. The less branches there are the less likely it is`
67			`* that a premature return shall occur.`
68			`* 3) If gcc decides that it is going to be a basterd then it will optimise a`
69			`* very simple condition (if/switch) with a premature exit. But gcc can't`
70			`* fuck ME over! Just stick a FORCE_RET; at the END of the offending`
71			`* function.`
72			* 4) All operations must start with `op_'. dyngen ignores all other functions.
73			`* 5) Local variables are depriciated: They hinder performance.`
74			`* 6) Function calls are expensive as the stack has to be shifted (twice).`
75			`*/`
76
77			`/#define __or_dynop __attribute__((noreturn))/`
78			`#define __or_dynop`
79
80			`/* Temporaries to hold the (simulated) registers in */`
81			`register uint32_t t0 asm(T0_REG);`
82			`register uint32_t t1 asm(T1_REG);`
83			`register uint32_t t2 asm(T2_REG);`
84
85			`#define OP_PARAM1 ((uorreg_t)(&__op_param1))`
86			`#define OP_PARAM2 ((uorreg_t)(&__op_param2))`
87			`#define OP_PARAM3 ((uorreg_t)(&__op_param3))`
88
89			`extern uorreg_t __op_param1;`
90			`extern uorreg_t __op_param2;`
91			`extern uorreg_t __op_param3;`
92
93
94	1678	nogj	`static inline void save_t_bound(oraddr_t pc)`
95	1452	nogj	`{`
96	1678	nogj	`int reg;`
97
98	1717	nogj	`pc = (pc & immu_state->page_offset_mask) / 4;`
99	1678	nogj	`reg = env->curr_page->ts_bound[pc];`
100
101			`if(reg & 0x1f)`
102			`env->reg[reg & 0x1f] = t0;`
103
104			`if((reg >> 5) & 0x1f)`
105			`env->reg[(reg >> 5) & 0x1f] = t1;`
106
107			`if((reg >> 10) & 0x1f)`
108			`env->reg[(reg >> 10) & 0x1f] = t2;`
109	1452	nogj	`}`
110
111			`void do_sched_wrap(void)`
112			`{`
113	1687	nogj	`env->pc += 4;`
114			`//runtime.cpu.instructions++;`
115			`runtime.sim.cycles -= env->cycles_dec;`
116			`scheduler.job_queue->time += env->cycles_dec;`
117			`if(scheduler.job_queue->time <= 0) {`
118			`save_t_bound(env->pc - 4);`
119			`do_scheduler();`
120			`}`
121	1452	nogj	`}`
122
123	1481	nogj	`/* do_scheduler wrapper for instructions that are in the delay slot */`
124			`void do_sched_wrap_delay(void)`
125			`{`
126	1687	nogj	`/* FIXME: Can't this be eliminated? */`
127			`env->pc += 4;`
128			`//runtime.cpu.instructions++;`
129			`runtime.sim.cycles -= env->cycles_dec;`
130			`scheduler.job_queue->time += env->cycles_dec;`
131			`if(scheduler.job_queue->time <= 0)`
132			`do_scheduler();`
133	1481	nogj	`}`
134
135			`void enter_dyn_code(oraddr_t addr, struct dyn_page *dp)`
136			`{`
137	1678	nogj	`uint16_t reg = 0;`
138	1692	nogj	`uint32_t t0_reg = t0, t1_reg = t1, t2_reg = t2;`
139			`struct cpu_state *cpu_reg = env;`
140	1481	nogj
141	1717	nogj	`addr &= immu_state->page_offset_mask;`
142	1481	nogj	`addr >>= 2;`
143
144	1678	nogj	`if(addr)`
145			`reg = dp->ts_bound[addr - 1];`
146	1481	nogj
147	1691	nogj	`t0 = cpu_state.reg[reg & 0x1f];`
148			`t1 = cpu_state.reg[(reg >> 5) & 0x1f];`
149	1481	nogj
150	1691	nogj	`/* Don't we all love gcc? For some heavenly reason gcc 3.2 _knows_ that if I`
151			`* don't put a condition around the assignment of t2, _all_ the assignments to`
152			`* t{0,1,2} are useless and not needed. I'm pleasently happy that gcc is so`
153			`* bright, but on the other hand, t{0,1,2} are globals (!) how can you assume`
154			`* that the value of a global won't be used in a function further up or`
155			`* further down the stack?? */`
156			`if(addr)`
157	1481	nogj	`t2 = cpu_state.reg[(reg >> 10) & 0x1f];`
158
159	1692	nogj	`env = &cpu_state;`
160
161			`((gen_code_ent *)dp->locs)[addr]();`
162			`t0 = t0_reg;`
163			`t1 = t1_reg;`
164			`t2 = t2_reg;`
165			`env = (struct cpu_state *)cpu_reg;`
166	1481	nogj	`}`
167
168			`__or_dynop void op_set_pc_pc_delay(void)`
169	1452	nogj	`{`
170	1687	nogj	`env->sprs[SPR_PPC] = env->pc;`
171	1481	nogj	`/* pc_delay is pulled back 4 since imediatly after this is run, the scheduler`
172			`* runs which also increments it by 4 */`
173	1687	nogj	`env->pc = env->pc_delay - 4;`
174	1452	nogj	`}`
175
176			`__or_dynop void op_set_pc_delay_imm(void)`
177			`{`
178	1687	nogj	`env->pc_delay = env->pc + (orreg_t)OP_PARAM1;`
179	1452	nogj	`env->delay_insn = 1;`
180			`}`
181
182			`__or_dynop void op_set_pc_delay_pc(void)`
183			`{`
184	1687	nogj	`env->pc_delay = env->pc;`
185	1452	nogj	`env->delay_insn = 1;`
186			`}`
187
188			`__or_dynop void op_clear_pc_delay(void)`
189			`{`
190			`env->pc_delay = 0;`
191			`env->delay_insn = 1;`
192			`}`
193
194			`__or_dynop void op_do_jump(void)`
195			`{`
196	1692	nogj	`RET_FROM_DYN_CODE;`
197	1481	nogj	`}`
198
199			`__or_dynop void op_do_jump_delay(void)`
200			`{`
201	1692	nogj	`env->pc = env->pc_delay;`
202			`RET_FROM_DYN_CODE;`
203	1452	nogj	`}`
204
205	1481	nogj	`__or_dynop void op_clear_delay_insn(void)`
206	1452	nogj	`{`
207	1481	nogj	`env->delay_insn = 0;`
208	1452	nogj	`}`
209
210	1481	nogj	`__or_dynop void op_set_delay_insn(void)`
211	1452	nogj	`{`
212	1481	nogj	`env->delay_insn = 1;`
213	1452	nogj	`}`
214
215	1481	nogj	`__or_dynop void op_check_delay_slot(void)`
216	1452	nogj	`{`
217	1481	nogj	`if(!env->delay_insn)`
218			`OP_JUMP(OP_PARAM1);`
219	1452	nogj	`}`
220
221			`__or_dynop void op_jmp_imm(void)`
222			`{`
223			`OP_JUMP(OP_PARAM1);`
224			`}`
225
226			`__or_dynop void op_set_flag(void)`
227			`{`
228			`env->sprs[SPR_SR] \|= SPR_SR_F;`
229			`}`
230
231			`__or_dynop void op_clear_flag(void)`
232			`{`
233			`env->sprs[SPR_SR] &= ~SPR_SR_F;`
234			`}`
235
236	1481	nogj	`/* Used for the l.bf instruction. Therefore if the flag is not set, jump over`
237			`* all the jumping stuff */`
238	1452	nogj	`__or_dynop void op_check_flag(void)`
239			`{`
240	1481	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
241	1687	nogj	`SPEEDY_CALL(do_sched_wrap);`
242	1481	nogj	`OP_JUMP(OP_PARAM1);`
243			`}`
244			`}`
245
246			`/* Used for l.bf if the delay slot instruction is on another page */`
247			`__or_dynop void op_check_flag_delay(void)`
248			`{`
249	1452	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
250	1481	nogj	`env->delay_insn = 1;`
251	1687	nogj	`env->pc_delay = env->pc + (orreg_t)OP_PARAM1;`
252	1452	nogj	`}`
253			`}`
254
255	1481	nogj	`/* Used for the l.bnf instruction. Therefore if the flag is set, jump over all`
256			`* the jumping stuff */`
257	1452	nogj	`__or_dynop void op_check_not_flag(void)`
258			`{`
259	1481	nogj	`if(env->sprs[SPR_SR] & SPR_SR_F) {`
260	1687	nogj	`SPEEDY_CALL(do_sched_wrap);`
261	1481	nogj	`OP_JUMP(OP_PARAM1);`
262			`}`
263			`}`
264
265			`/* Used for l.bnf if the delay slot instruction is on another page */`
266			`__or_dynop void op_check_not_flag_delay(void)`
267			`{`
268	1452	nogj	`if(!(env->sprs[SPR_SR] & SPR_SR_F)) {`
269	1481	nogj	`env->delay_insn = 1;`
270	1687	nogj	`env->pc_delay = env->pc + (orreg_t)OP_PARAM1;`
271	1452	nogj	`}`
272			`}`
273
274	1481	nogj	`__or_dynop void op_add_pc(void)`
275	1452	nogj	`{`
276	1687	nogj	`env->pc += OP_PARAM1;`
277	1452	nogj	`}`
278
279			`__or_dynop void op_nop_exit(void)`
280			`{`
281			`op_support_nop_exit();`
282			`FORCE_RET;`
283			`}`
284
285			`__or_dynop void op_nop_reset(void)`
286			`{`
287			`op_support_nop_reset();`
288	1692	nogj	`env->pc = EXCEPT_RESET;`
289			`RET_FROM_DYN_CODE;`
290	1452	nogj	`}`
291
292			`__or_dynop void op_nop_printf(void)`
293			`{`
294			`op_support_nop_printf();`
295			`FORCE_RET;`
296			`}`
297
298			`__or_dynop void op_nop_report(void)`
299			`{`
300			`op_support_nop_report();`
301			`FORCE_RET;`
302			`}`
303
304			`__or_dynop void op_nop_report_imm(void)`
305			`{`
306			`op_support_nop_report_imm(OP_PARAM1);`
307			`}`
308
309	1721	nogj	`/* FIXME: Create another 2 sched functions that to the actual analysis call`
310			`* instead of bloating the recompiled code with this */`
311	1657	nogj	`__or_dynop void op_analysis(void)`
312	1452	nogj	`{`
313	1721	nogj	`SPEEDY_CALL(op_support_analysis);`
314	1452	nogj	`}`
315
316	1657	nogj	`__or_dynop void op_move_gpr1_pc_delay(void)`
317			`{`
318			`env->pc_delay = env->reg[1];`
319			`env->delay_insn = 1;`
320			`}`
321	1452	nogj
322	1657	nogj	`__or_dynop void op_move_gpr2_pc_delay(void)`
323	1452	nogj	`{`
324	1657	nogj	`env->pc_delay = env->reg[2];`
325			`env->delay_insn = 1;`
326	1452	nogj	`}`
327
328	1657	nogj	`__or_dynop void op_move_gpr3_pc_delay(void)`
329	1452	nogj	`{`
330	1657	nogj	`env->pc_delay = env->reg[3];`
331			`env->delay_insn = 1;`
332	1452	nogj	`}`
333
334	1657	nogj	`__or_dynop void op_move_gpr4_pc_delay(void)`
335			`{`
336			`env->pc_delay = env->reg[4];`
337			`env->delay_insn = 1;`
338			`}`
339	1452	nogj
340	1657	nogj	`__or_dynop void op_move_gpr5_pc_delay(void)`
341	1452	nogj	`{`
342	1657	nogj	`env->pc_delay = env->reg[5];`
343			`env->delay_insn = 1;`
344	1452	nogj	`}`
345
346	1657	nogj	`__or_dynop void op_move_gpr6_pc_delay(void)`
347	1452	nogj	`{`
348	1657	nogj	`env->pc_delay = env->reg[6];`
349			`env->delay_insn = 1;`
350	1452	nogj	`}`
351
352	1657	nogj	`__or_dynop void op_move_gpr7_pc_delay(void)`
353	1452	nogj	`{`
354	1657	nogj	`env->pc_delay = env->reg[7];`
355			`env->delay_insn = 1;`
356	1452	nogj	`}`
357
358	1657	nogj	`__or_dynop void op_move_gpr8_pc_delay(void)`
359	1452	nogj	`{`
360	1657	nogj	`env->pc_delay = env->reg[8];`
361			`env->delay_insn = 1;`
362	1452	nogj	`}`
363
364	1657	nogj	`__or_dynop void op_move_gpr9_pc_delay(void)`
365			`{`
366			`env->pc_delay = env->reg[9];`
367			`env->delay_insn = 1;`
368			`}`
369
370			`__or_dynop void op_move_gpr10_pc_delay(void)`
371			`{`
372			`env->pc_delay = env->reg[10];`
373			`env->delay_insn = 1;`
374			`}`
375
376			`__or_dynop void op_move_gpr11_pc_delay(void)`
377			`{`
378			`env->pc_delay = env->reg[11];`
379			`env->delay_insn = 1;`
380			`}`
381
382			`__or_dynop void op_move_gpr12_pc_delay(void)`
383			`{`
384			`env->pc_delay = env->reg[12];`
385			`env->delay_insn = 1;`
386			`}`
387
388			`__or_dynop void op_move_gpr13_pc_delay(void)`
389			`{`
390			`env->pc_delay = env->reg[13];`
391			`env->delay_insn = 1;`
392			`}`
393
394			`__or_dynop void op_move_gpr14_pc_delay(void)`
395			`{`
396			`env->pc_delay = env->reg[14];`
397			`env->delay_insn = 1;`
398			`}`
399
400			`__or_dynop void op_move_gpr15_pc_delay(void)`
401			`{`
402			`env->pc_delay = env->reg[15];`
403			`env->delay_insn = 1;`
404			`}`
405
406			`__or_dynop void op_move_gpr16_pc_delay(void)`
407			`{`
408			`env->pc_delay = env->reg[16];`
409			`env->delay_insn = 1;`
410			`}`
411
412			`__or_dynop void op_move_gpr17_pc_delay(void)`
413			`{`
414			`env->pc_delay = env->reg[17];`
415			`env->delay_insn = 1;`
416			`}`
417
418			`__or_dynop void op_move_gpr18_pc_delay(void)`
419			`{`
420			`env->pc_delay = env->reg[18];`
421			`env->delay_insn = 1;`
422			`}`
423
424			`__or_dynop void op_move_gpr19_pc_delay(void)`
425			`{`
426			`env->pc_delay = env->reg[19];`
427			`env->delay_insn = 1;`
428			`}`
429
430			`__or_dynop void op_move_gpr20_pc_delay(void)`
431			`{`
432			`env->pc_delay = env->reg[20];`
433			`env->delay_insn = 1;`
434			`}`
435
436			`__or_dynop void op_move_gpr21_pc_delay(void)`
437			`{`
438			`env->pc_delay = env->reg[21];`
439			`env->delay_insn = 1;`
440			`}`
441
442			`__or_dynop void op_move_gpr22_pc_delay(void)`
443			`{`
444			`env->pc_delay = env->reg[22];`
445			`env->delay_insn = 1;`
446			`}`
447
448			`__or_dynop void op_move_gpr23_pc_delay(void)`
449			`{`
450			`env->pc_delay = env->reg[23];`
451			`env->delay_insn = 1;`
452			`}`
453
454			`__or_dynop void op_move_gpr24_pc_delay(void)`
455			`{`
456			`env->pc_delay = env->reg[24];`
457			`env->delay_insn = 1;`
458			`}`
459
460			`__or_dynop void op_move_gpr25_pc_delay(void)`
461			`{`
462			`env->pc_delay = env->reg[25];`
463			`env->delay_insn = 1;`
464			`}`
465
466			`__or_dynop void op_move_gpr26_pc_delay(void)`
467			`{`
468			`env->pc_delay = env->reg[26];`
469			`env->delay_insn = 1;`
470			`}`
471
472			`__or_dynop void op_move_gpr27_pc_delay(void)`
473			`{`
474			`env->pc_delay = env->reg[27];`
475			`env->delay_insn = 1;`
476			`}`
477
478			`__or_dynop void op_move_gpr28_pc_delay(void)`
479			`{`
480			`env->pc_delay = env->reg[28];`
481			`env->delay_insn = 1;`
482			`}`
483
484			`__or_dynop void op_move_gpr29_pc_delay(void)`
485			`{`
486			`env->pc_delay = env->reg[29];`
487			`env->delay_insn = 1;`
488			`}`
489
490			`__or_dynop void op_move_gpr30_pc_delay(void)`
491			`{`
492			`env->pc_delay = env->reg[30];`
493			`env->delay_insn = 1;`
494			`}`
495
496			`__or_dynop void op_move_gpr31_pc_delay(void)`
497			`{`
498			`env->pc_delay = env->reg[31];`
499			`env->delay_insn = 1;`
500			`}`

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[/] [or1k/] [tags/] [rel-0-3-0-rc1/] [or1ksim/] [cpu/] [or32/] [op.c] - Blame information for rev 1721