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/* immu.c -- Instruction MMU simulation
 
   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
   Copyright (C) 2008 Embecosm Limited
 
   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.
 
   This program is free software; you can redistribute it and/or modify it
   under the terms of the GNU General Public License as published by the Free
   Software Foundation; either version 3 of the License, or (at your option)
   any later version.
 
   This program is distributed in the hope that it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
 
   You should have received a copy of the GNU General Public License along
   with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
/* This program is commented throughout in a fashion suitable for processing
   with Doxygen. */
 
 
/* Autoconf and/or portability configuration */
#include "config.h"
 
/* System includes */
#include <stdlib.h>
 
/* Package includes */
#include "immu.h"
#include "sim-config.h"
#include "execute.h"
#include "debug.h"
#include "stats.h"
#include "except.h"
#include "spr-dump.h"
#include "misc.h"
#include "sim-cmd.h"
 
 
DEFAULT_DEBUG_CHANNEL (immu);
 
struct immu *immu_state;
 
/* Insn MMU */
 
static uorreg_t *
immu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** itlbmr_lru, struct immu *immu)
{
  int set;
  int i;
  oraddr_t vpn;
  uorreg_t *itlbmr;
 
  /* Which set to check out? */
  set = IADDR_PAGE (virtaddr) >> immu->pagesize_log2;
  set &= immu->set_mask;
  vpn = virtaddr & immu->vpn_mask;
 
  itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE (0) + set];
  *itlbmr_lru = itlbmr;
 
  /* Scan all ways and try to find a matching way. */
  /* FIXME: Should this be reversed? */
  for (i = immu->nways; i; i--, itlbmr += (128 * 2))
    {
      if (((*itlbmr & immu->vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
        return itlbmr;
    }
 
  return NULL;
}
 
oraddr_t
immu_translate (oraddr_t virtaddr)
{
  int i;
  uorreg_t *itlbmr;
  uorreg_t *itlbtr;
  uorreg_t *itlbmr_lru;
  struct immu *immu = immu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
    {
      insn_ci = (virtaddr >= 0x80000000);
      return virtaddr;
    }
 
  itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);
 
  /* Did we find our tlb entry? */
  if (itlbmr)
    {                           /* Yes, we did. */
      immu_stats.fetch_tlbhit++;
      TRACE ("ITLB hit (virtaddr=%" PRIxADDR ").\n", virtaddr);
 
      itlbtr = itlbmr + 128;
 
      /* Set LRUs */
      for (i = 0; i < immu->nways; i++, itlbmr_lru += (128 * 2))
        {
          if (*itlbmr_lru & SPR_ITLBMR_LRU)
            *itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
              ((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
        }
 
      /* This is not necessary `*itlbmr &= ~SPR_ITLBMR_LRU;' since SPR_DTLBMR_LRU
       * is always decremented and the number of sets is always a power of two and
       * as such lru_reload has all bits set that get touched during decrementing
       * SPR_DTLBMR_LRU */
      *itlbmr |= immu->lru_reload;
 
      /* Check if page is cache inhibited */
      insn_ci = *itlbtr & SPR_ITLBTR_CI;
 
      runtime.sim.mem_cycles += immu->hitdelay;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if (!(*itlbtr & SPR_ITLBTR_SXE))
            except_handle (EXCEPT_IPF, virtaddr);
        }
      else
        {
          if (!(*itlbtr & SPR_ITLBTR_UXE))
            except_handle (EXCEPT_IPF, virtaddr);
        }
 
      TRACE ("Returning physical address %" PRIxADDR "\n",
             (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->
                                           page_offset_mask));
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
    }
 
  /* No, we didn't. */
  immu_stats.fetch_tlbmiss++;
#if 0
  for (i = 0; i < immu->nways; i++)
    if (((cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] & SPR_ITLBMR_LRU) >> 6) <
        minlru)
      minway = i;
 
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] &= ~SPR_ITLBMR_VPN;
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= vpn << 12;
  for (i = 0; i < immu->nways; i++)
    {
      uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE (i) + set];
      if (lru & SPR_ITLBMR_LRU)
        {
          lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
          cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] = lru;
        }
    }
  cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] &= ~SPR_ITLBMR_LRU;
  cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] |= (immu->nsets - 1) << 6;
 
  /* 1 to 1 mapping */
  cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] &= ~SPR_ITLBTR_PPN;
  cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] |= vpn << 12;
 
  cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= SPR_ITLBMR_V;
#endif
 
  /* if tlb refill implemented in HW */
  /* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */
  runtime.sim.mem_cycles += immu->missdelay;
 
  except_handle (EXCEPT_ITLBMISS, virtaddr);
  return 0;
}
 
/* DESC: try to find EA -> PA transaltion without changing
 *       any of precessor states. if this is not passible gives up
 *       (without triggering exceptions).
 *
 * PRMS: virtaddr  - EA for which to find translation
 *
 * RTRN: 0         - no IMMU, IMMU disabled or ITLB miss
 *       else      - appropriate PA (note it IMMU is not present
 *                   PA === EA)
 */
oraddr_t
peek_into_itlb (oraddr_t virtaddr)
{
  uorreg_t *itlbmr;
  uorreg_t *itlbtr;
  uorreg_t *itlbmr_lru;
  struct immu *immu = immu_state;
 
  if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
      !(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
    {
      return (virtaddr);
    }
 
  itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);
 
  /* Did we find our tlb entry? */
  if (itlbmr)
    {                           /* Yes, we did. */
      itlbtr = itlbmr + 128;
 
      /* Test for page fault */
      if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)
        {
          if (!(*itlbtr & SPR_ITLBTR_SXE))
            {
              /* no luck, giving up */
              return (0);
            }
        }
      else
        {
          if (!(*itlbtr & SPR_ITLBTR_UXE))
            {
              /* no luck, giving up */
              return (0);
            }
        }
 
      return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr & immu->page_offset_mask);
    }
 
  return (0);
}
 
 
/* FIXME: Check validity */
/* First check if virtual address is covered by ITLB and if it is:
    - increment ITLB read hit stats,
    - set 'lru' at this way to immu->ustates - 1 and
      decrement 'lru' of other ways unless they have reached 0,
    - check page access attributes and invoke IMMU page fault exception
      handler if necessary
   and if not:
    - increment ITLB read miss stats
    - find lru way and entry and invoke ITLB miss exception handler
    - set 'lru' with immu->ustates - 1 and decrement 'lru' of other
      ways unless they have reached 0
*/
 
static void
itlb_status (void *dat)
{
  struct immu *immu = dat;
  int set;
  int way;
  int end_set = immu->nsets;
 
  if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))
    {
      PRINTF ("IMMU not implemented. Set UPR[IMP].\n");
      return;
    }
 
  if (0 < end_set)
    PRINTF ("\nIMMU: ");
  /* Scan set(s) and way(s). */
  for (set = 0; set < end_set; set++)
    {
      for (way = 0; way < immu->nways; way++)
        {
          PRINTF ("%s\n", dump_spr (SPR_ITLBMR_BASE (way) + set,
                                    cpu_state.sprs[SPR_ITLBMR_BASE (way) +
                                                   set]));
          PRINTF ("%s\n",
                  dump_spr (SPR_ITLBTR_BASE (way) + set,
                            cpu_state.sprs[SPR_ITLBTR_BASE (way) + set]));
        }
    }
  if (0 < end_set)
    PRINTF ("\n");
}
 
/*---------------------------------------------------[ IMMU configuration ]---*/
 
/*---------------------------------------------------------------------------*/
/*!Enable or disable the IMMU
 
   Set the corresponding field in the UPR
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_enabled (union param_val val, void *dat)
{
  struct immu *immu = dat;
 
  if (val.int_val)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
    }
 
  immu->enabled = val.int_val;
}
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of DMMU sets
 
   Value must be a power of 2 <= 256. Ignore any other values with a
   warning. Set the corresponding IMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_nsets (union param_val  val,
            void            *dat)
{
  struct immu *immu = dat;
 
  if (is_power2 (val.int_val) && (val.int_val <= 128))
    {
      int  set_bits = log2_int (val.int_val);
 
      immu->nsets = val.int_val;
 
      cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
      cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
    }
  else
    {
      fprintf (stderr, "Warning IMMU nsets not a power of 2 <= 128: ignored\n");
    }
}       /* immu_nsets() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of IMMU ways
 
   Value must be in the range 1-4. Ignore other values with a warning.  Set
   the corresponding IMMU configuration flags.
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_nways (union param_val  val,
            void            *dat)
{
  struct immu *immu = dat;
 
  if (val.int_val >= 1 && val.int_val <= 4)
    {
      int  way_bits = val.int_val - 1;
 
      immu->nways = val.int_val;
 
      cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
      cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
    }
  else
    {
      fprintf (stderr, "Warning IMMU nways not in range 1-4: ignored\n");
    }
}       /* immu_nways() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the IMMU page size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_pagesize (union param_val  val,
               void            *dat)
{
  struct immu *immu = dat;
 
  if (is_power2 (val.int_val))
    {
      immu->pagesize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning IMMU page size must be power of 2: ignored\n");
    }
}       /* immu_pagesize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the IMMU entry size
 
   Value must be a power of 2. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_entrysize (union param_val  val,
                void            *dat)
{
  struct immu *immu = dat;
 
  if (is_power2 (val.int_val))
    {
      immu->entrysize = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning IMMU entry size must be power of 2: ignored\n");
    }
}       /* immu_entrysize() */
 
 
/*---------------------------------------------------------------------------*/
/*!Set the number of IMMU usage states
 
   Value must be 2, 3 or 4. Ignore other values with a warning
 
   @param[in] val  The value to use
   @param[in] dat  The config data structure                                 */
/*---------------------------------------------------------------------------*/
static void
immu_ustates (union param_val  val,
              void            *dat)
{
  struct immu *immu = dat;
 
  if ((val.int_val >= 2) && (val.int_val <= 4))
    {
      immu->ustates = val.int_val;
    }
  else
    {
      fprintf (stderr, "Warning number of IMMU usage states must be 2, 3 or 4:"
               "ignored\n");
    }
}       /* immu_ustates() */
 
 
static void
immu_missdelay (union param_val val, void *dat)
{
  struct immu *immu = dat;
 
  immu->missdelay = val.int_val;
}
 
static void
immu_hitdelay (union param_val val, void *dat)
{
  struct immu *immu = dat;
 
  immu->hitdelay = val.int_val;
}
 
/*---------------------------------------------------------------------------*/
/*!Initialize a new DMMU configuration
 
   ALL parameters are set explicitly to default values.                      */
/*---------------------------------------------------------------------------*/
static void *
immu_start_sec ()
{
  struct immu *immu;
  int          set_bits;
  int          way_bits;
 
  if (NULL == (immu = malloc (sizeof (struct immu))))
    {
      fprintf (stderr, "OOM\n");
      exit (1);
    }
 
  immu->enabled   = 0;
  immu->nsets     = 1;
  immu->nways     = 1;
  immu->pagesize  = 8192;
  immu->entrysize = 1;          /* Not currently used */
  immu->ustates   = 2;
  immu->hitdelay  = 1;
  immu->missdelay = 1;
 
  if (immu->enabled)
    {
      cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
    }
  else
    {
      cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
    }
 
  set_bits = log2_int (immu->nsets);
  cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
  cpu_state.sprs[SPR_IMMUCFGR] |= set_bits << SPR_IMMUCFGR_NTS_OFF;
 
  way_bits = immu->nways - 1;
  cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
  cpu_state.sprs[SPR_IMMUCFGR] |= way_bits << SPR_IMMUCFGR_NTW_OFF;
 
  immu_state = immu;
  return immu;
 
}       /* immu_start_sec() */
 
 
static void
immu_end_sec (void *dat)
{
  struct immu *immu = dat;
 
  /* Precalculate some values for use during address translation */
  immu->pagesize_log2 = log2_int (immu->pagesize);
  immu->page_offset_mask = immu->pagesize - 1;
  immu->page_mask = ~immu->page_offset_mask;
  immu->vpn_mask = ~((immu->pagesize * immu->nsets) - 1);
  immu->set_mask = immu->nsets - 1;
  immu->lru_reload = (immu->set_mask << 6) & SPR_ITLBMR_LRU;
 
  if (immu->enabled)
    {
      PRINTF ("Insn MMU %dKB: %d ways, %d sets, entry size %d bytes\n",
              immu->nsets * immu->entrysize * immu->nways / 1024, immu->nways,
              immu->nsets, immu->entrysize);
      reg_sim_stat (itlb_status, immu);
    }
}
 
void
reg_immu_sec (void)
{
  struct config_section *sec = reg_config_sec ("immu", immu_start_sec,
                                               immu_end_sec);
 
  reg_config_param (sec, "enabled", paramt_int, immu_enabled);
  reg_config_param (sec, "nsets", paramt_int, immu_nsets);
  reg_config_param (sec, "nways", paramt_int, immu_nways);
  reg_config_param (sec, "pagesize", paramt_int, immu_pagesize);
  reg_config_param (sec, "entrysize", paramt_int, immu_entrysize);
  reg_config_param (sec, "ustates", paramt_int, immu_ustates);
  reg_config_param (sec, "missdelay", paramt_int, immu_missdelay);
  reg_config_param (sec, "hitdelay", paramt_int, immu_hitdelay);
}

Line No.	Rev	Author	Line
1	74	lampret	`/* immu.c -- Instruction MMU simulation`
2	1748	jeremybenn
3	74	lampret	`Copyright (C) 1999 Damjan Lampret, lampret@opencores.org`
4	1748	jeremybenn	`Copyright (C) 2008 Embecosm Limited`
5	74	lampret
6	1748	jeremybenn	`Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>`
7	74	lampret
8	1748	jeremybenn	`This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.`
9	74	lampret
10	1748	jeremybenn	`This program is free software; you can redistribute it and/or modify it`
11			`under the terms of the GNU General Public License as published by the Free`
12			`Software Foundation; either version 3 of the License, or (at your option)`
13			`any later version.`
14	74	lampret
15	1748	jeremybenn	`This program is distributed in the hope that it will be useful, but WITHOUT`
16			`ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
18			`more details.`
19	74	lampret
20	1748	jeremybenn	`You should have received a copy of the GNU General Public License along`
21			`with this program. If not, see <http://www.gnu.org/licenses/>. */`
22
23			`/* This program is commented throughout in a fashion suitable for processing`
24			`with Doxygen. */`
25
26
27			`/* Autoconf and/or portability configuration */`
28	1350	nogj	`#include "config.h"`
29
30	1748	jeremybenn	`/* System includes */`
31			`#include <stdlib.h>`
32	1350	nogj
33	1748	jeremybenn	`/* Package includes */`
34	74	lampret	`#include "immu.h"`
35	1748	jeremybenn	`#include "sim-config.h"`
36	1432	nogj	`#include "execute.h"`
37	1748	jeremybenn	`#include "debug.h"`
38	74	lampret	`#include "stats.h"`
39			`#include "except.h"`
40	1748	jeremybenn	`#include "spr-dump.h"`
41	1555	nogj	`#include "misc.h"`
42	1748	jeremybenn	`#include "sim-cmd.h"`
43	74	lampret
44	1416	nogj
45	1748	jeremybenn	`DEFAULT_DEBUG_CHANNEL (immu);`
46
47	1717	nogj	`struct immu *immu_state;`
48
49	74	lampret	`/* Insn MMU */`
50
51	1748	jeremybenn	`static uorreg_t *`
52			`immu_find_tlbmr (oraddr_t virtaddr, uorreg_t ** itlbmr_lru, struct immu *immu)`
53	1538	nogj	`{`
54			`int set;`
55	430	markom	`int i;`
56	1538	nogj	`oraddr_t vpn;`
57			`uorreg_t *itlbmr;`
58	884	markom
59	1538	nogj	`/* Which set to check out? */`
60	1748	jeremybenn	`set = IADDR_PAGE (virtaddr) >> immu->pagesize_log2;`
61	1717	nogj	`set &= immu->set_mask;`
62			`vpn = virtaddr & immu->vpn_mask;`
63	1538	nogj
64	1748	jeremybenn	`itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE (0) + set];`
65	1538	nogj	`*itlbmr_lru = itlbmr;`
66
67			`/* Scan all ways and try to find a matching way. */`
68			`/* FIXME: Should this be reversed? */`
69	1748	jeremybenn	`for (i = immu->nways; i; i--, itlbmr += (128 * 2))`
70			`{`
71			`if (((itlbmr & immu->vpn_mask) == vpn) && (itlbmr & SPR_ITLBMR_V))`
72			`return itlbmr;`
73			`}`
74	1538	nogj
75			`return NULL;`
76			`}`
77
78	1748	jeremybenn	`oraddr_t`
79			`immu_translate (oraddr_t virtaddr)`
80	1538	nogj	`{`
81			`int i;`
82			`uorreg_t *itlbmr;`
83			`uorreg_t *itlbtr;`
84			`uorreg_t *itlbmr_lru;`
85	1717	nogj	`struct immu *immu = immu_state;`
86	1538	nogj
87	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) \|\|`
88	1748	jeremybenn	`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))`
89			`{`
90			`insn_ci = (virtaddr >= 0x80000000);`
91			`return virtaddr;`
92			`}`
93	430	markom
94	1748	jeremybenn	`itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);`
95	1416	nogj
96	430	markom	`/* Did we find our tlb entry? */`
97	1748	jeremybenn	`if (itlbmr)`
98			`{ /* Yes, we did. */`
99			`immu_stats.fetch_tlbhit++;`
100			`TRACE ("ITLB hit (virtaddr=%" PRIxADDR ").\n", virtaddr);`
101	1506	nogj
102	1748	jeremybenn	`itlbtr = itlbmr + 128;`
103	1538	nogj
104	1748	jeremybenn	`/* Set LRUs */`
105			`for (i = 0; i < immu->nways; i++, itlbmr_lru += (128 * 2))`
106			`{`
107			`if (*itlbmr_lru & SPR_ITLBMR_LRU)`
108			`itlbmr_lru = (itlbmr_lru & ~SPR_ITLBMR_LRU) \|`
109			`((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);`
110			`}`
111	638	simons
112	1748	jeremybenn	/* This is not necessary `*itlbmr &= ~SPR_ITLBMR_LRU;' since SPR_DTLBMR_LRU
113			`* is always decremented and the number of sets is always a power of two and`
114			`* as such lru_reload has all bits set that get touched during decrementing`
115			`* SPR_DTLBMR_LRU */`
116			`*itlbmr \|= immu->lru_reload;`
117	1418	nogj
118	1748	jeremybenn	`/* Check if page is cache inhibited */`
119			`insn_ci = *itlbtr & SPR_ITLBTR_CI;`
120
121			`runtime.sim.mem_cycles += immu->hitdelay;`
122
123			`/* Test for page fault */`
124			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
125			`{`
126			`if (!(*itlbtr & SPR_ITLBTR_SXE))`
127			`except_handle (EXCEPT_IPF, virtaddr);`
128			`}`
129			`else`
130			`{`
131			`if (!(*itlbtr & SPR_ITLBTR_UXE))`
132			`except_handle (EXCEPT_IPF, virtaddr);`
133			`}`
134
135			`TRACE ("Returning physical address %" PRIxADDR "\n",`
136			`(*itlbtr & SPR_ITLBTR_PPN) \| (virtaddr & immu->`
137			`page_offset_mask));`
138			`return (*itlbtr & SPR_ITLBTR_PPN) \| (virtaddr & immu->page_offset_mask);`
139	1418	nogj	`}`
140
141	1538	nogj	`/* No, we didn't. */`
142			`immu_stats.fetch_tlbmiss++;`
143	430	markom	`#if 0`
144	1717	nogj	`for (i = 0; i < immu->nways; i++)`
145	1748	jeremybenn	`if (((cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] & SPR_ITLBMR_LRU) >> 6) <`
146			`minlru)`
147	1538	nogj	`minway = i;`
148	1748	jeremybenn
149			`cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] &= ~SPR_ITLBMR_VPN;`
150			`cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] \|= vpn << 12;`
151			`for (i = 0; i < immu->nways; i++)`
152			`{`
153			`uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE (i) + set];`
154			`if (lru & SPR_ITLBMR_LRU)`
155			`{`
156			`lru = (lru & ~SPR_ITLBMR_LRU) \| ((lru & SPR_ITLBMR_LRU) - 0x40);`
157			`cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] = lru;`
158			`}`
159	1506	nogj	`}`
160	1748	jeremybenn	`cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] &= ~SPR_ITLBMR_LRU;`
161			`cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] \|= (immu->nsets - 1) << 6;`
162	1506	nogj
163	1538	nogj	`/* 1 to 1 mapping */`
164	1748	jeremybenn	`cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] &= ~SPR_ITLBTR_PPN;`
165			`cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] \|= vpn << 12;`
166	1506	nogj
167	1748	jeremybenn	`cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] \|= SPR_ITLBMR_V;`
168	430	markom	`#endif`
169	1418	nogj
170	1538	nogj	`/* if tlb refill implemented in HW */`
171	1717	nogj	`/* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */`
172			`runtime.sim.mem_cycles += immu->missdelay;`
173	1418	nogj
174	1748	jeremybenn	`except_handle (EXCEPT_ITLBMISS, virtaddr);`
175	1538	nogj	`return 0;`
176	430	markom	`}`
177
178	1174	phoenix	`/* DESC: try to find EA -> PA transaltion without changing`
179			`* any of precessor states. if this is not passible gives up`
180	1446	nogj	`* (without triggering exceptions).`
181	1174	phoenix	`*`
182			`* PRMS: virtaddr - EA for which to find translation`
183			`*`
184			`* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss`
185			`* else - appropriate PA (note it IMMU is not present`
186			`* PA === EA)`
187			`*/`
188	1748	jeremybenn	`oraddr_t`
189			`peek_into_itlb (oraddr_t virtaddr)`
190	1174	phoenix	`{`
191	1538	nogj	`uorreg_t *itlbmr;`
192			`uorreg_t *itlbtr;`
193			`uorreg_t *itlbmr_lru;`
194	1717	nogj	`struct immu *immu = immu_state;`
195	1174	phoenix
196	1506	nogj	`if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) \|\|`
197	1748	jeremybenn	`!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))`
198			`{`
199			`return (virtaddr);`
200			`}`
201	1174	phoenix
202	1748	jeremybenn	`itlbmr = immu_find_tlbmr (virtaddr, &itlbmr_lru, immu);`
203	1174	phoenix
204			`/* Did we find our tlb entry? */`
205	1748	jeremybenn	`if (itlbmr)`
206			`{ /* Yes, we did. */`
207			`itlbtr = itlbmr + 128;`
208	1538	nogj
209	1748	jeremybenn	`/* Test for page fault */`
210			`if (cpu_state.sprs[SPR_SR] & SPR_SR_SM)`
211			`{`
212			`if (!(*itlbtr & SPR_ITLBTR_SXE))`
213			`{`
214			`/* no luck, giving up */`
215			`return (0);`
216			`}`
217			`}`
218			`else`
219			`{`
220			`if (!(*itlbtr & SPR_ITLBTR_UXE))`
221			`{`
222			`/* no luck, giving up */`
223			`return (0);`
224			`}`
225			`}`
226
227			`return (*itlbtr & SPR_ITLBTR_PPN) \| (virtaddr & immu->page_offset_mask);`
228	1174	phoenix	`}`
229
230	1748	jeremybenn	`return (0);`
231	1174	phoenix	`}`
232
233
234	1717	nogj	`/* FIXME: Check validity */`
235	74	lampret	`/* First check if virtual address is covered by ITLB and if it is:`
236			`- increment ITLB read hit stats,`
237	1717	nogj	`- set 'lru' at this way to immu->ustates - 1 and`
238	74	lampret	`decrement 'lru' of other ways unless they have reached 0,`
239			`- check page access attributes and invoke IMMU page fault exception`
240			`handler if necessary`
241			`and if not:`
242			`- increment ITLB read miss stats`
243			`- find lru way and entry and invoke ITLB miss exception handler`
244	1717	nogj	`- set 'lru' with immu->ustates - 1 and decrement 'lru' of other`
245	74	lampret	`ways unless they have reached 0`
246			`*/`
247
248	1748	jeremybenn	`static void`
249			`itlb_status (void *dat)`
250	74	lampret	`{`
251	1717	nogj	`struct immu *immu = dat;`
252	429	markom	`int set;`
253			`int way;`
254	1717	nogj	`int end_set = immu->nsets;`
255	74	lampret
256	1748	jeremybenn	`if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP))`
257			`{`
258			`PRINTF ("IMMU not implemented. Set UPR[IMP].\n");`
259			`return;`
260			`}`
261	102	lampret
262	1748	jeremybenn	`if (0 < end_set)`
263			`PRINTF ("\nIMMU: ");`
264	429	markom	`/* Scan set(s) and way(s). */`
265	1748	jeremybenn	`for (set = 0; set < end_set; set++)`
266			`{`
267			`for (way = 0; way < immu->nways; way++)`
268			`{`
269			`PRINTF ("%s\n", dump_spr (SPR_ITLBMR_BASE (way) + set,`
270			`cpu_state.sprs[SPR_ITLBMR_BASE (way) +`
271			`set]));`
272			`PRINTF ("%s\n",`
273			`dump_spr (SPR_ITLBTR_BASE (way) + set,`
274			`cpu_state.sprs[SPR_ITLBTR_BASE (way) + set]));`
275			`}`
276	429	markom	`}`
277	1748	jeremybenn	`if (0 < end_set)`
278			`PRINTF ("\n");`
279	74	lampret	`}`
280	1358	nogj
281			`/---------------------------------------------------[ IMMU configuration ]---/`
282	1748	jeremybenn
283			`/---------------------------------------------------------------------------/`
284			`/*!Enable or disable the IMMU`
285
286			`Set the corresponding field in the UPR`
287
288			`@param[in] val The value to use`
289			`@param[in] dat The config data structure */`
290			`/---------------------------------------------------------------------------/`
291			`static void`
292			`immu_enabled (union param_val val, void *dat)`
293	1358	nogj	`{`
294	1717	nogj	`struct immu *immu = dat;`
295
296	1748	jeremybenn	`if (val.int_val)`
297			`{`
298			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_IMP;`
299			`}`
300	1506	nogj	`else`
301	1748	jeremybenn	`{`
302			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;`
303			`}`
304
305	1717	nogj	`immu->enabled = val.int_val;`
306	1358	nogj	`}`
307
308	1748	jeremybenn
309			`/---------------------------------------------------------------------------/`
310			`/*!Set the number of DMMU sets`
311
312			`Value must be a power of 2 <= 256. Ignore any other values with a`
313			`warning. Set the corresponding IMMU configuration flags.`
314
315			`@param[in] val The value to use`
316			`@param[in] dat The config data structure */`
317			`/---------------------------------------------------------------------------/`
318			`static void`
319			`immu_nsets (union param_val val,`
320			`void *dat)`
321	1358	nogj	`{`
322	1717	nogj	`struct immu *immu = dat;`
323
324	1748	jeremybenn	`if (is_power2 (val.int_val) && (val.int_val <= 128))`
325			`{`
326			`int set_bits = log2_int (val.int_val);`
327
328			`immu->nsets = val.int_val;`
329
330			`cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;`
331			`cpu_state.sprs[SPR_IMMUCFGR] \|= set_bits << SPR_IMMUCFGR_NTS_OFF;`
332			`}`
333	1358	nogj	`else`
334	1748	jeremybenn	`{`
335			`fprintf (stderr, "Warning IMMU nsets not a power of 2 <= 128: ignored\n");`
336			`}`
337			`} /* immu_nsets() */`
338	1358	nogj
339	1748	jeremybenn
340			`/---------------------------------------------------------------------------/`
341			`/*!Set the number of IMMU ways`
342
343			`Value must be in the range 1-4. Ignore other values with a warning. Set`
344			`the corresponding IMMU configuration flags.`
345
346			`@param[in] val The value to use`
347			`@param[in] dat The config data structure */`
348			`/---------------------------------------------------------------------------/`
349			`static void`
350			`immu_nways (union param_val val,`
351			`void *dat)`
352	1358	nogj	`{`
353	1717	nogj	`struct immu *immu = dat;`
354
355	1748	jeremybenn	`if (val.int_val >= 1 && val.int_val <= 4)`
356			`{`
357			`int way_bits = val.int_val - 1;`
358
359			`immu->nways = val.int_val;`
360
361			`cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;`
362			`cpu_state.sprs[SPR_IMMUCFGR] \|= way_bits << SPR_IMMUCFGR_NTW_OFF;`
363			`}`
364	1358	nogj	`else`
365	1748	jeremybenn	`{`
366			`fprintf (stderr, "Warning IMMU nways not in range 1-4: ignored\n");`
367			`}`
368			`} /* immu_nways() */`
369	1358	nogj
370	1748	jeremybenn
371			`/---------------------------------------------------------------------------/`
372			`/*!Set the IMMU page size`
373
374			`Value must be a power of 2. Ignore other values with a warning`
375
376			`@param[in] val The value to use`
377			`@param[in] dat The config data structure */`
378			`/---------------------------------------------------------------------------/`
379			`static void`
380			`immu_pagesize (union param_val val,`
381			`void *dat)`
382	1358	nogj	`{`
383	1717	nogj	`struct immu *immu = dat;`
384
385	1748	jeremybenn	`if (is_power2 (val.int_val))`
386			`{`
387			`immu->pagesize = val.int_val;`
388			`}`
389	1358	nogj	`else`
390	1748	jeremybenn	`{`
391			`fprintf (stderr, "Warning IMMU page size must be power of 2: ignored\n");`
392			`}`
393			`} /* immu_pagesize() */`
394	1358	nogj
395	1748	jeremybenn
396			`/---------------------------------------------------------------------------/`
397			`/*!Set the IMMU entry size`
398
399			`Value must be a power of 2. Ignore other values with a warning`
400
401			`@param[in] val The value to use`
402			`@param[in] dat The config data structure */`
403			`/---------------------------------------------------------------------------/`
404			`static void`
405			`immu_entrysize (union param_val val,`
406			`void *dat)`
407	1358	nogj	`{`
408	1717	nogj	`struct immu *immu = dat;`
409
410	1748	jeremybenn	`if (is_power2 (val.int_val))`
411			`{`
412			`immu->entrysize = val.int_val;`
413			`}`
414	1358	nogj	`else`
415	1748	jeremybenn	`{`
416			`fprintf (stderr, "Warning IMMU entry size must be power of 2: ignored\n");`
417			`}`
418			`} /* immu_entrysize() */`
419	1358	nogj
420	1748	jeremybenn
421			`/---------------------------------------------------------------------------/`
422			`/*!Set the number of IMMU usage states`
423
424			`Value must be 2, 3 or 4. Ignore other values with a warning`
425
426			`@param[in] val The value to use`
427			`@param[in] dat The config data structure */`
428			`/---------------------------------------------------------------------------/`
429			`static void`
430			`immu_ustates (union param_val val,`
431			`void *dat)`
432	1358	nogj	`{`
433	1717	nogj	`struct immu *immu = dat;`
434
435	1748	jeremybenn	`if ((val.int_val >= 2) && (val.int_val <= 4))`
436			`{`
437			`immu->ustates = val.int_val;`
438			`}`
439	1358	nogj	`else`
440	1748	jeremybenn	`{`
441			`fprintf (stderr, "Warning number of IMMU usage states must be 2, 3 or 4:"`
442			`"ignored\n");`
443			`}`
444			`} /* immu_ustates() */`
445	1358	nogj
446	1748	jeremybenn
447			`static void`
448			`immu_missdelay (union param_val val, void *dat)`
449	1358	nogj	`{`
450	1717	nogj	`struct immu *immu = dat;`
451
452			`immu->missdelay = val.int_val;`
453	1358	nogj	`}`
454
455	1748	jeremybenn	`static void`
456			`immu_hitdelay (union param_val val, void *dat)`
457	1358	nogj	`{`
458	1717	nogj	`struct immu *immu = dat;`
459
460			`immu->hitdelay = val.int_val;`
461	1358	nogj	`}`
462
463	1748	jeremybenn	`/---------------------------------------------------------------------------/`
464			`/*!Initialize a new DMMU configuration`
465
466			`ALL parameters are set explicitly to default values. */`
467			`/---------------------------------------------------------------------------/`
468			`static void *`
469			`immu_start_sec ()`
470	1654	nogj	`{`
471	1717	nogj	`struct immu *immu;`
472	1748	jeremybenn	`int set_bits;`
473			`int way_bits;`
474	1717	nogj
475	1748	jeremybenn	`if (NULL == (immu = malloc (sizeof (struct immu))))`
476			`{`
477			`fprintf (stderr, "OOM\n");`
478			`exit (1);`
479			`}`
480	1717	nogj
481	1748	jeremybenn	`immu->enabled = 0;`
482			`immu->nsets = 1;`
483			`immu->nways = 1;`
484			`immu->pagesize = 8192;`
485			`immu->entrysize = 1; /* Not currently used */`
486			`immu->ustates = 2;`
487			`immu->hitdelay = 1;`
488	1717	nogj	`immu->missdelay = 1;`
489
490	1748	jeremybenn	`if (immu->enabled)`
491			`{`
492			`cpu_state.sprs[SPR_UPR] \|= SPR_UPR_IMP;`
493			`}`
494			`else`
495			`{`
496			`cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;`
497			`}`
498
499			`set_bits = log2_int (immu->nsets);`
500			`cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;`

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