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/* 16450.c -- Simulation of 8250/16450 serial UART

   Copyright (C) 1999 Damjan Lampret, lampret@opencores.org

   Copyright (C) 2008 Embecosm Limited

   Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>

   This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator.

   This program is free software; you can redistribute it and/or modify it

   under the terms of the GNU General Public License as published by the Free

   Software Foundation; either version 3 of the License, or (at your option)

   any later version.

   This program is distributed in the hope that it will be useful, but WITHOUT

   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for

   more details.

   You should have received a copy of the GNU General Public License along

   with this program.  If not, see <http://www.gnu.org/licenses/>.  */

/* This program is commented throughout in a fashion suitable for processing

   with Doxygen. */

/* This is functional simulation of 8250/16450/16550 UARTs. Since we RX/TX

   data via file streams, we can't simulate modem control lines coming from

   the DCE and similar details of communication with the DCE.

   This simulated UART device is intended for basic UART device driver

   verification. From device driver perspective this device looks like a

   regular UART but never reports any modem control lines changes (the

   only DCE responses are incoming characters from the file stream). */

/* Autoconf and/or portability configuration */

#include "config.h"

#include "port.h"

/* System includes */

#include <stdlib.h>

/* Package includes */

#include "sim-config.h"

#include "debug.h"

#include "arch.h"

#include "pic.h"

#include "sched.h"

#include "vapi.h"

#include "channel.h"

#include "abstract.h"

#include "toplevel-support.h"

#include "sim-cmd.h"

DEFAULT_DEBUG_CHANNEL (uart);

#define MIN(a,b) ((a) < (b) ? (a) : (b))

/* Definitions */

#define UART_ADDR_SPACE        8        /*!< UART addr space size in bytes */

#define UART_MAX_FIFO_LEN     16        /*!< rx FIFO for uart 16550 */

#define MAX_SKEW               1        /*!< max. clock skew in subclocks */

#define UART_VAPI_BUF_LEN    128        /*!< Size of VAPI command buffer */

#define UART_CLOCK_DIVIDER    16        /*!< UART clock divider */

#define UART_FGETC_SLOWDOWN  100        /*!< fgetc() slowdown factor */

/*

 * Addresses of visible registers

 *

 */

#define UART_RXBUF  0           /* R: Rx buffer, DLAB=0 */

#define UART_TXBUF  0           /* W: Tx buffer, DLAB=0 */

#define UART_DLL  0             /* R/W: Divisor Latch Low, DLAB=1 */

#define UART_DLH  1             /* R/W: Divisor Latch High, DLAB=1 */

#define UART_IER  1             /* R/W: Interrupt Enable Register */

#define UART_IIR  2             /* R: Interrupt ID Register */

#define UART_FCR  2             /* W: FIFO Control Register */

#define UART_LCR  3             /* R/W: Line Control Register */

#define UART_MCR  4             /* W: Modem Control Register */

#define UART_LSR  5             /* R: Line Status Register */

#define UART_MSR  6             /* R: Modem Status Register */

#define UART_SCR  7             /* R/W: Scratch Register */

/*

 * R/W masks for valid bits in 8250/16450 (mask out 16550 and later bits)

 *

 */

#define UART_VALID_LCR  0xff

#define UART_VALID_LSR  0xff

#define UART_VALID_IIR  0x0f

#define UART_VALID_FCR  0xc0

#define UART_VALID_IER  0x0f

#define UART_VALID_MCR  0x1f

#define UART_VALID_MSR  0xff

/*

 * Bit definitions for the Line Control Register

 *

 */

#define UART_LCR_DLAB 0x80      /* Divisor latch access bit */

#define UART_LCR_SBC  0x40      /* Set break control */

#define UART_LCR_SPAR 0x20      /* Stick parity (?) */

#define UART_LCR_EPAR 0x10      /* Even parity select */

#define UART_LCR_PARITY 0x08    /* Parity Enable */

#define UART_LCR_STOP 0x04      /* Stop bits: 0=1 stop bit, 1= 2 stop bits */

#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */

#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */

#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */

#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */

#define UART_LCR_RESET  0x03

/*

 * Bit definitions for the Line Status Register

 */

#define UART_LSR_RXERR  0x80    /* Error in rx fifo */

#define UART_LSR_TXSERE 0x40    /* Transmitter serial register empty */

#define UART_LSR_TXBUFE 0x20    /* Transmitter buffer register empty */

#define UART_LSR_BREAK  0x10    /* Break interrupt indicator */

#define UART_LSR_FRAME  0x08    /* Frame error indicator */

#define UART_LSR_PARITY 0x04    /* Parity error indicator */

#define UART_LSR_OVRRUN 0x02    /* Overrun error indicator */

#define UART_LSR_RDRDY  0x01    /* Receiver data ready */

/*

 * Bit definitions for the Interrupt Identification Register

 */

#define UART_IIR_NO_INT 0x01    /* No interrupts pending */

#define UART_IIR_ID 0x06        /* Mask for the interrupt ID */

#define UART_IIR_MSI  0x00      /* Modem status interrupt (Low priority) */

#define UART_IIR_THRI 0x02      /* Transmitter holding register empty */

#define UART_IIR_RDI  0x04      /* Receiver data interrupt */

#define UART_IIR_RLSI 0x06      /* Receiver line status interrupt (High p.) */

#define UART_IIR_CTI  0x0c      /* Character timeout */

/*

 * Bit Definitions for the FIFO Control Register

 */

#define UART_FCR_FIE  0x01      /* FIFO enable */

#define UART_FCR_RRXFI 0x02     /* Reset rx FIFO */

#define UART_FCR_RTXFI 0x04     /* Reset tx FIFO */

#define UART_FIFO_TRIGGER(x) /* Trigger values for indexes 0..3 */\

  ((x) == 0 ? 1\

  :(x) == 1 ? 4\

  :(x) == 2 ? 8\

  :(x) == 3 ? 14 : 0)

/*

 * Bit definitions for the Interrupt Enable Register

 */

#define UART_IER_MSI  0x08      /* Enable Modem status interrupt */

#define UART_IER_RLSI 0x04      /* Enable receiver line status interrupt */

#define UART_IER_THRI 0x02      /* Enable Transmitter holding register int. */

#define UART_IER_RDI  0x01      /* Enable receiver data interrupt */

/*

 * Bit definitions for the Modem Control Register

 */

#define UART_MCR_LOOP 0x10      /* Enable loopback mode */

#define UART_MCR_AUX2 0x08      /* Auxilary 2  */

#define UART_MCR_AUX1 0x04      /* Auxilary 1 */

#define UART_MCR_RTS  0x02      /* Force RTS */

#define UART_MCR_DTR  0x01      /* Force DTR */

/*

 * Bit definitions for the Modem Status Register

 */

#define UART_MSR_DCD  0x80      /* Data Carrier Detect */

#define UART_MSR_RI   0x40      /* Ring Indicator */

#define UART_MSR_DSR  0x20      /* Data Set Ready */

#define UART_MSR_CTS  0x10      /* Clear to Send */

#define UART_MSR_DDCD 0x08      /* Delta DCD */

#define UART_MSR_TERI 0x04      /* Trailing edge ring indicator */

#define UART_MSR_DDSR 0x02      /* Delta DSR */

#define UART_MSR_DCTS 0x01      /* Delta CTS */

/*

 * Various definitions

 */

#define UART_BREAK_COUNT   1    /* # of chars to count when doing break */

#define UART_CHAR_TIMEOUT  4    /* # of chars to count when doing timeout int */

/* Registers */

struct dev_16450

{

  struct

  {

    uint8_t   txbuf[UART_MAX_FIFO_LEN];

    uint16_t  rxbuf[UART_MAX_FIFO_LEN]; /* Upper 8-bits is the LCR modifier */

    uint8_t   dll;

    uint8_t   dlh;

    uint8_t   ier;

    uint8_t   iir;

    uint8_t   fcr;

    uint8_t   lcr;

    uint8_t   mcr;

    uint8_t   lsr;

    uint8_t   msr;

    uint8_t   scr;

  } regs;                       /* Visible registers */

  struct

  {

    uint8_t   txser;            /* Character just sending */

    uint16_t  rxser;            /* Character just receiving */

    uint8_t   loopback;

  } iregs;                      /* Internal registers */

  struct

  {

    int           txbuf_head;

    int           txbuf_tail;

    int           rxbuf_head;

    int           rxbuf_tail;

    unsigned int  txbuf_full;

    unsigned int  rxbuf_full;

    int           receiveing;   /* Receiving a char */

    int           recv_break;   /* Receiving a break */

    int           ints;         /* Which interrupts are pending */

  } istat;                      /* Internal status */

  /* Clocks per char */

  unsigned long  char_clks;

  /* VAPI internal registers */

  struct

  {

    unsigned long  char_clks;

    uint8_t        dll;

    uint8_t        dlh;

    uint8_t        lcr;

    int            skew;

  } vapi;

  /* Required by VAPI - circular buffer to store incoming chars, since we

     cannothandle them so fast - we are serial. */

  unsigned long   vapi_buf[UART_VAPI_BUF_LEN];  /* Buffer */

  int             vapi_buf_head_ptr;            /* Where we write to */

  int             vapi_buf_tail_ptr;            /* Where we read from */

  /* Length of FIFO, 16 for 16550, 1 for 16450 */

  int             fifo_len;

  struct channel *channel;

  /* Configuration */

  int             enabled;

  int             jitter;

  oraddr_t        baseaddr;

  int             irq;

  unsigned long   vapi_id;

  int             uart16550;

  char           *channel_str;

};

/* Forward declarations of static functions */

static void uart_recv_break (void *dat);

static void uart_recv_char (void *dat);

static void uart_check_char (void *dat);

static void uart_sched_recv_check (struct dev_16450 *uart);

static void uart_vapi_cmd (void *dat);

static void uart_clear_int (struct dev_16450 *uart, int intr);

static void uart_tx_send (void *dat);

/* Number of clock cycles (one clock cycle is when UART_CLOCK_DIVIDER simulator

 * cycles have elapsed) before a single character is transmitted or received. */

static unsigned long

char_clks (int dll, int dlh, int lcr)

{

  unsigned int bauds_per_char = 2;

  unsigned long char_clks = ((dlh << 8) + dll);

  if (lcr & UART_LCR_PARITY)

    bauds_per_char += 2;

  /* stop bits 1 or two */

  if (lcr & UART_LCR_STOP)

    bauds_per_char += 4;

  else if ((lcr & 0x3) != 0)

    bauds_per_char += 2;

  else

    bauds_per_char += 3;

  bauds_per_char += 10 + ((lcr & 0x3) << 1);

  return (char_clks * bauds_per_char) >> 1;

}

/*---------------------------------------------------[ Interrupt handling ]---*/

/* Signals the specified interrupt.  If a higher priority interrupt is already

 * pending, do nothing */

static void

uart_int_msi (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->istat.ints |= 1 << UART_IIR_MSI;

  if (!(uart->regs.ier & UART_IER_MSI))

    return;

  if ((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI))

    {

      TRACE ("Raiseing modem status interrupt\n");

      uart->regs.iir = UART_IIR_MSI;

      report_interrupt (uart->irq);

    }

}

static void

uart_int_thri (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->istat.ints |= 1 << UART_IIR_THRI;

  if (!(uart->regs.ier & UART_IER_THRI))

    return;

  if ((uart->regs.iir & UART_IIR_NO_INT) || (uart->regs.iir == UART_IIR_MSI)

      || (uart->regs.iir == UART_IIR_THRI))

    {

      TRACE ("Raiseing transmitter holding register interrupt\n");

      uart->regs.iir = UART_IIR_THRI;

      report_interrupt (uart->irq);

    }

}

static void

uart_int_cti (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->istat.ints |= 1 << UART_IIR_CTI;

  if (!(uart->regs.ier & UART_IER_RDI))

    return;

  if ((uart->regs.iir != UART_IIR_RLSI) && (uart->regs.iir != UART_IIR_RDI))

    {

      TRACE ("Raiseing character timeout interrupt\n");

      uart->regs.iir = UART_IIR_CTI;

      report_interrupt (uart->irq);

    }

}

static void

uart_int_rdi (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->istat.ints |= 1 << UART_IIR_RDI;

  if (!(uart->regs.ier & UART_IER_RDI))

    return;

  if (uart->regs.iir != UART_IIR_RLSI)

    {

      TRACE ("Raiseing receiver data interrupt\n");

      uart->regs.iir = UART_IIR_RDI;

      report_interrupt (uart->irq);

    }

}

static void

uart_int_rlsi (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->istat.ints |= 1 << UART_IIR_RLSI;

  if (!(uart->regs.ier & UART_IER_RLSI))

    return;

  TRACE ("Raiseing receiver line status interrupt\n");

  /* Highest priority interrupt */

  uart->regs.iir = UART_IIR_RLSI;

  report_interrupt (uart->irq);

}

/* Checks to see if an RLSI interrupt is due and schedules one if need be */

static void

uart_check_rlsi (void *dat)

{

  struct dev_16450 *uart = dat;

  if (uart->regs.lsr & (UART_LSR_OVRRUN | UART_LSR_PARITY | UART_LSR_FRAME |

                        UART_LSR_BREAK))

    uart_int_rlsi (uart);

}

/* Checks to see if an RDI interrupt is due and schedules one if need be */

static void

uart_check_rdi (void *dat)

{

  struct dev_16450 *uart = dat;

  if (uart->istat.rxbuf_full >= UART_FIFO_TRIGGER (uart->regs.fcr >> 6))

    {

      TRACE ("FIFO trigger level reached %i\n",

             UART_FIFO_TRIGGER (uart->regs.fcr >> 6));

      uart_int_rdi (uart);

    }

}

/* Raises the next highest priority interrupt */

static void

uart_next_int (struct dev_16450 *uart)

{

  /* Interrupt detection in proper priority order. */

  if ((uart->istat.ints & (1 << UART_IIR_RLSI)) &&

      (uart->regs.ier & UART_IER_RLSI))

    uart_int_rlsi (uart);

  else if ((uart->istat.ints & (1 << UART_IIR_RDI)) &&

           (uart->regs.ier & UART_IER_RDI))

    uart_int_rdi (uart);

  else if ((uart->istat.ints & (1 << UART_IIR_CTI)) &&

           (uart->regs.ier & UART_IER_RDI))

    uart_int_cti (uart);

  else if ((uart->istat.ints & (1 << UART_IIR_THRI)) &&

           (uart->regs.ier & UART_IER_THRI))

    uart_int_thri (uart);

  else if ((uart->istat.ints & (1 << UART_IIR_MSI)) &&

           (uart->regs.ier & UART_IER_MSI))

    uart_int_msi (uart);

  else

    {

      clear_interrupt (uart->irq);

      uart->regs.iir = UART_IIR_NO_INT;

    }

}

/* Clears potentially pending interrupts */

static void

uart_clear_int (struct dev_16450 *uart, int intr)

{

  uart->istat.ints &= ~(1 << intr);

  TRACE ("Interrupt pending was %x\n", uart->regs.iir);

  /* Some stuff schedule uart_int_cti, therefore remove it here */

  if (intr == UART_IIR_CTI)

    SCHED_FIND_REMOVE (uart_int_cti, uart);

  if (intr != uart->regs.iir)

    return;

  TRACE ("Clearing interrupt 0x%x\n", intr);

  uart_next_int (uart);

}

/*----------------------------------------------------[ Loopback handling ]---*/

static void

uart_loopback (struct dev_16450 *uart)

{

  if (!(uart->regs.mcr & UART_MCR_LOOP))

    return;

  if ((uart->regs.mcr & UART_MCR_AUX2) !=

      ((uart->regs.msr & UART_MSR_DCD) >> 4))

    uart->regs.msr |= UART_MSR_DDCD;

  if ((uart->regs.mcr & UART_MCR_AUX1) <

      ((uart->regs.msr & UART_MSR_RI) >> 4))

    uart->regs.msr |= UART_MSR_TERI;

  if ((uart->regs.mcr & UART_MCR_RTS) !=

      ((uart->regs.msr & UART_MSR_CTS) >> 3))

    uart->regs.msr |= UART_MSR_DCTS;

  if ((uart->regs.mcr & UART_MCR_DTR) !=

      ((uart->regs.msr & UART_MSR_DSR) >> 5))

    uart->regs.msr |= UART_MSR_DDSR;

  uart->regs.msr &=

    ~(UART_MSR_DCD | UART_MSR_RI | UART_MSR_DSR | UART_MSR_CTS);

  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX2) << 4);

  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_AUX1) << 4);

  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_RTS) << 3);

  uart->regs.msr |= ((uart->regs.mcr & UART_MCR_DTR) << 5);

  if (uart->regs.msr & (UART_MSR_DCTS | UART_MSR_DDSR | UART_MSR_TERI |

                        UART_MSR_DDCD))

    uart_int_msi (uart);

}

/*----------------------------------------------------[ Transmitter logic ]---*/

/* Sends the data in the shift register to the outside world */

static void

send_char (struct dev_16450 *uart, int bits_send)

{

  PRINTF ("%c", (char) uart->iregs.txser);

  TRACE ("TX \'%c\' via UART at %" PRIxADDR "\n", (char) uart->iregs.txser,

         uart->baseaddr);

  if (uart->regs.mcr & UART_MCR_LOOP)

    uart->iregs.loopback = uart->iregs.txser;

  else

    {

      /* Send to either VAPI or to file */

      if (uart->vapi_id)

        {

          int par, pe, fe, nbits;

          int j, data;

          unsigned long packet = 0;

          nbits = MIN (bits_send, (uart->regs.lcr & UART_LCR_WLEN8) + 5);

          /* Encode a packet */

          packet = uart->iregs.txser & ((1 << nbits) - 1);

          /* Calculate parity */

          for (j = 0, par = 0; j < nbits; j++)

            par ^= (packet >> j) & 1;

          if (uart->regs.lcr & UART_LCR_PARITY)

            {

              if (uart->regs.lcr & UART_LCR_SPAR)

                {

                  packet |= 1 << nbits;

                }

              else

                {

                  if (uart->regs.lcr & UART_LCR_EPAR)

                    packet |= par << nbits;

                  else

                    packet |= (par ^ 1) << nbits;

                }

              nbits++;

            }

          packet |= 1 << (nbits++);

          if (uart->regs.lcr & UART_LCR_STOP)

            packet |= 1 << (nbits++);

          /* Decode a packet */

          nbits = (uart->vapi.lcr & UART_LCR_WLEN8) + 5;

          data = packet & ((1 << nbits) - 1);

          /* Calculate parity, including parity bit */

          for (j = 0, par = 0; j < nbits + 1; j++)

            par ^= (packet >> j) & 1;

          if (uart->vapi.lcr & UART_LCR_PARITY)

            {

              if (uart->vapi.lcr & UART_LCR_SPAR)

                {

                  pe = !((packet >> nbits) & 1);

                }

              else

                {

                  if (uart->vapi.lcr & UART_LCR_EPAR)

                    pe = par != 0;

                  else

                    pe = par != 1;

                }

              nbits++;

            }

          else

            pe = 0;

          fe = ((packet >> (nbits++)) & 1) ^ 1;

          if (uart->vapi.lcr & UART_LCR_STOP)

            fe |= ((packet >> (nbits++)) & 1) ^ 1;

          TRACE ("lcr vapi %02x, uart %02x\n", uart->vapi.lcr,

                 uart->regs.lcr);

          data |=

            (uart->vapi.lcr << 8) | (pe << 16) | (fe << 17) | (uart->vapi.

                                                               lcr << 8);

          TRACE ("vapi_send (%08lx, %08x)\n", uart->vapi_id, data);

          vapi_send (uart->vapi_id, data);

        }

      else

        {

          char buffer[1] = { uart->iregs.txser & 0xFF };

          channel_write (uart->channel, buffer, 1);

        }

    }

}

/* Called when all the bits have been shifted out of the shift register */

void

uart_char_clock (void *dat)

{

  struct dev_16450 *uart = dat;

  TRACE ("Sending data in shift reg: 0x%02" PRIx8 "\n", uart->iregs.txser);

  /* We've sent all bits */

  send_char (uart, (uart->regs.lcr & UART_LCR_WLEN8) + 5);

  if (!uart->istat.txbuf_full)

    uart->regs.lsr |= UART_LSR_TXSERE;

  else

    uart_tx_send (uart);

}

/* Called when a break has been shifted out of the shift register */

void

uart_send_break (void *dat)

{

  struct dev_16450 *uart = dat;

  TRACE ("Sending break\n");

#if 0

  /* Send broken frame */

  int nbits_sent =

    ((uart->regs.lcr & UART_LCR_WLEN8) + 5) * (uart->istat.txser_clks -

                                               1) / uart->char_clks;

  send_char (i, nbits_sent);

#endif

  /* Send one break signal */

  vapi_send (uart->vapi_id, UART_LCR_SBC << 8);

  /* Send the next char (if there is one) */

  if (!uart->istat.txbuf_full)

    uart->regs.lsr |= UART_LSR_TXSERE;

  else

    uart_tx_send (uart);

}

/* Scheduled whenever the TX buffer has characters in it and we aren't sending

 * a character. */

void

uart_tx_send (void *dat)

{

  struct dev_16450 *uart = dat;

  uart->iregs.txser = uart->regs.txbuf[uart->istat.txbuf_tail];

  uart->istat.txbuf_tail = (uart->istat.txbuf_tail + 1) % uart->fifo_len;

  uart->istat.txbuf_full--;

  uart->regs.lsr &= ~UART_LSR_TXSERE;

  TRACE ("Moveing head of TX fifo (fill: %i) to shift reg 0x%02" PRIx8 "\n",

         uart->istat.txbuf_full, uart->iregs.txser);

  /* Schedules a char_clock to run in the correct amount of time */

  if (!(uart->regs.lcr & UART_LCR_SBC))

    {

      SCHED_ADD (uart_char_clock, uart, uart->char_clks * UART_CLOCK_DIVIDER);

    }

  else

    {

      TRACE ("Sending break not char\n");

      SCHED_ADD (uart_send_break, uart, 0);

    }

  /* When UART is in either character mode, i.e. 16450 emulation mode, or FIFO

   * mode, the THRE interrupt is raised when THR transitions from full to empty.

   */

  if (!uart->istat.txbuf_full)

    {

      uart->regs.lsr |= UART_LSR_TXBUFE;

      uart_int_thri (uart);

    }

}

/*-------------------------------------------------------[ Receiver logic ]---*/

/* Adds a character to the RX FIFO */

static void

uart_add_char (struct dev_16450 *uart, int ch)

{

  uart->regs.lsr |= UART_LSR_RDRDY;

  uart_clear_int (uart, UART_IIR_CTI);

  SCHED_ADD (uart_int_cti, uart,